1//=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// 10//===----------------------------------------------------------------------===// 11 12//===----------------------------------------------------------------------===// 13// Target-independent interfaces which we are implementing. 14//===----------------------------------------------------------------------===// 15 16include "llvm/Target/Target.td" 17 18//===----------------------------------------------------------------------===// 19// AArch64 Subtarget features. 20// 21 22def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true", 23 "Enable ARMv8 FP">; 24 25def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", 26 "Enable Advanced SIMD instructions", [FeatureFPARMv8]>; 27 28def FeatureSM4 : SubtargetFeature< 29 "sm4", "HasSM4", "true", 30 "Enable SM3 and SM4 support", [FeatureNEON]>; 31 32def FeatureSHA2 : SubtargetFeature< 33 "sha2", "HasSHA2", "true", 34 "Enable SHA1 and SHA256 support", [FeatureNEON]>; 35 36def FeatureSHA3 : SubtargetFeature< 37 "sha3", "HasSHA3", "true", 38 "Enable SHA512 and SHA3 support", [FeatureNEON, FeatureSHA2]>; 39 40def FeatureAES : SubtargetFeature< 41 "aes", "HasAES", "true", 42 "Enable AES support", [FeatureNEON]>; 43 44// Crypto has been split up and any combination is now valid (see the 45// crypto defintions above). Also, crypto is now context sensitive: 46// it has a different meaning for e.g. Armv8.4 than it has for Armv8.2. 47// Therefore, we rely on Clang, the user interacing tool, to pass on the 48// appropriate crypto options. But here in the backend, crypto has very little 49// meaning anymore. We kept the Crypto defintion here for backward 50// compatibility, and now imply features SHA2 and AES, which was the 51// "traditional" meaning of Crypto. 52def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", 53 "Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>; 54 55def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", 56 "Enable ARMv8 CRC-32 checksum instructions">; 57 58def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true", 59 "Enable ARMv8 Reliability, Availability and Serviceability Extensions">; 60 61def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true", 62 "Enable ARMv8.1 Large System Extension (LSE) atomic instructions">; 63 64def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true", 65 "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions">; 66 67def FeaturePAN : SubtargetFeature< 68 "pan", "HasPAN", "true", 69 "Enables ARM v8.1 Privileged Access-Never extension">; 70 71def FeatureLOR : SubtargetFeature< 72 "lor", "HasLOR", "true", 73 "Enables ARM v8.1 Limited Ordering Regions extension">; 74 75def FeatureVH : SubtargetFeature< 76 "vh", "HasVH", "true", 77 "Enables ARM v8.1 Virtual Host extension">; 78 79def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", 80 "Enable ARMv8 PMUv3 Performance Monitors extension">; 81 82def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true", 83 "Full FP16", [FeatureFPARMv8]>; 84 85def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true", 86 "Enable FP16 FML instructions", [FeatureFullFP16]>; 87 88def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true", 89 "Enable Statistical Profiling extension">; 90 91def FeaturePAN_RWV : SubtargetFeature< 92 "pan-rwv", "HasPAN_RWV", "true", 93 "Enable v8.2 PAN s1e1R and s1e1W Variants", 94 [FeaturePAN]>; 95 96// UAO PState 97def FeaturePsUAO : SubtargetFeature< "uaops", "HasPsUAO", "true", 98 "Enable v8.2 UAO PState">; 99 100def FeatureCCPP : SubtargetFeature<"ccpp", "HasCCPP", 101 "true", "Enable v8.2 data Cache Clean to Point of Persistence" >; 102 103def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true", 104 "Enable Scalable Vector Extension (SVE) instructions">; 105 106def FeatureSVE2 : SubtargetFeature<"sve2", "HasSVE2", "true", 107 "Enable Scalable Vector Extension 2 (SVE2) instructions", [FeatureSVE]>; 108 109def FeatureSVE2AES : SubtargetFeature<"sve2-aes", "HasSVE2AES", "true", 110 "Enable AES SVE2 instructions", [FeatureSVE2, FeatureAES]>; 111 112def FeatureSVE2SM4 : SubtargetFeature<"sve2-sm4", "HasSVE2SM4", "true", 113 "Enable SM4 SVE2 instructions", [FeatureSVE2, FeatureSM4]>; 114 115def FeatureSVE2SHA3 : SubtargetFeature<"sve2-sha3", "HasSVE2SHA3", "true", 116 "Enable SHA3 SVE2 instructions", [FeatureSVE2, FeatureSHA3]>; 117 118def FeatureSVE2BitPerm : SubtargetFeature<"sve2-bitperm", "HasSVE2BitPerm", "true", 119 "Enable bit permutation SVE2 instructions", [FeatureSVE2]>; 120 121def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true", 122 "Has zero-cycle register moves">; 123def FeatureZCZeroingGP : SubtargetFeature<"zcz-gp", "HasZeroCycleZeroingGP", "true", 124 "Has zero-cycle zeroing instructions for generic registers">; 125 126def FeatureZCZeroingFP : SubtargetFeature<"zcz-fp", "HasZeroCycleZeroingFP", "true", 127 "Has zero-cycle zeroing instructions for FP registers">; 128 129def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true", 130 "Has zero-cycle zeroing instructions", 131 [FeatureZCZeroingGP, FeatureZCZeroingFP]>; 132 133/// ... but the floating-point version doesn't quite work in rare cases on older 134/// CPUs. 135def FeatureZCZeroingFPWorkaround : SubtargetFeature<"zcz-fp-workaround", 136 "HasZeroCycleZeroingFPWorkaround", "true", 137 "The zero-cycle floating-point zeroing instruction has a bug">; 138 139def FeatureStrictAlign : SubtargetFeature<"strict-align", 140 "StrictAlign", "true", 141 "Disallow all unaligned memory " 142 "access">; 143 144foreach i = {1-7,9-15,18,20-28} in 145 def FeatureReserveX#i : SubtargetFeature<"reserve-x"#i, "ReserveXRegister["#i#"]", "true", 146 "Reserve X"#i#", making it unavailable " 147 "as a GPR">; 148 149foreach i = {8-15,18} in 150 def FeatureCallSavedX#i : SubtargetFeature<"call-saved-x"#i, 151 "CustomCallSavedXRegs["#i#"]", "true", "Make X"#i#" callee saved.">; 152 153def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true", 154 "Use alias analysis during codegen">; 155 156def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps", 157 "true", 158 "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">; 159 160def FeaturePredictableSelectIsExpensive : SubtargetFeature< 161 "predictable-select-expensive", "PredictableSelectIsExpensive", "true", 162 "Prefer likely predicted branches over selects">; 163 164def FeatureCustomCheapAsMoveHandling : SubtargetFeature<"custom-cheap-as-move", 165 "CustomAsCheapAsMove", "true", 166 "Use custom handling of cheap instructions">; 167 168def FeatureExynosCheapAsMoveHandling : SubtargetFeature<"exynos-cheap-as-move", 169 "ExynosAsCheapAsMove", "true", 170 "Use Exynos specific handling of cheap instructions", 171 [FeatureCustomCheapAsMoveHandling]>; 172 173def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler", 174 "UsePostRAScheduler", "true", "Schedule again after register allocation">; 175 176def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store", 177 "Misaligned128StoreIsSlow", "true", "Misaligned 128 bit stores are slow">; 178 179def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128", 180 "Paired128IsSlow", "true", "Paired 128 bit loads and stores are slow">; 181 182def FeatureSlowSTRQro : SubtargetFeature<"slow-strqro-store", "STRQroIsSlow", 183 "true", "STR of Q register with register offset is slow">; 184 185def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature< 186 "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern", 187 "true", "Use alternative pattern for sextload convert to f32">; 188 189def FeatureArithmeticBccFusion : SubtargetFeature< 190 "arith-bcc-fusion", "HasArithmeticBccFusion", "true", 191 "CPU fuses arithmetic+bcc operations">; 192 193def FeatureArithmeticCbzFusion : SubtargetFeature< 194 "arith-cbz-fusion", "HasArithmeticCbzFusion", "true", 195 "CPU fuses arithmetic + cbz/cbnz operations">; 196 197def FeatureFuseAddress : SubtargetFeature< 198 "fuse-address", "HasFuseAddress", "true", 199 "CPU fuses address generation and memory operations">; 200 201def FeatureFuseAES : SubtargetFeature< 202 "fuse-aes", "HasFuseAES", "true", 203 "CPU fuses AES crypto operations">; 204 205def FeatureFuseArithmeticLogic : SubtargetFeature< 206 "fuse-arith-logic", "HasFuseArithmeticLogic", "true", 207 "CPU fuses arithmetic and logic operations">; 208 209def FeatureFuseCCSelect : SubtargetFeature< 210 "fuse-csel", "HasFuseCCSelect", "true", 211 "CPU fuses conditional select operations">; 212 213def FeatureFuseCryptoEOR : SubtargetFeature< 214 "fuse-crypto-eor", "HasFuseCryptoEOR", "true", 215 "CPU fuses AES/PMULL and EOR operations">; 216 217def FeatureFuseLiterals : SubtargetFeature< 218 "fuse-literals", "HasFuseLiterals", "true", 219 "CPU fuses literal generation operations">; 220 221def FeatureDisableLatencySchedHeuristic : SubtargetFeature< 222 "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true", 223 "Disable latency scheduling heuristic">; 224 225def FeatureForce32BitJumpTables 226 : SubtargetFeature<"force-32bit-jump-tables", "Force32BitJumpTables", "true", 227 "Force jump table entries to be 32-bits wide except at MinSize">; 228 229def FeatureRCPC : SubtargetFeature<"rcpc", "HasRCPC", "true", 230 "Enable support for RCPC extension">; 231 232def FeatureUseRSqrt : SubtargetFeature< 233 "use-reciprocal-square-root", "UseRSqrt", "true", 234 "Use the reciprocal square root approximation">; 235 236def FeatureDotProd : SubtargetFeature< 237 "dotprod", "HasDotProd", "true", 238 "Enable dot product support">; 239 240def FeaturePA : SubtargetFeature< 241 "pa", "HasPA", "true", 242 "Enable v8.3-A Pointer Authentication enchancement">; 243 244def FeatureJS : SubtargetFeature< 245 "jsconv", "HasJS", "true", 246 "Enable v8.3-A JavaScript FP conversion enchancement", 247 [FeatureFPARMv8]>; 248 249def FeatureCCIDX : SubtargetFeature< 250 "ccidx", "HasCCIDX", "true", 251 "Enable v8.3-A Extend of the CCSIDR number of sets">; 252 253def FeatureComplxNum : SubtargetFeature< 254 "complxnum", "HasComplxNum", "true", 255 "Enable v8.3-A Floating-point complex number support", 256 [FeatureNEON]>; 257 258def FeatureNV : SubtargetFeature< 259 "nv", "HasNV", "true", 260 "Enable v8.4-A Nested Virtualization Enchancement">; 261 262def FeatureRASv8_4 : SubtargetFeature< 263 "rasv8_4", "HasRASv8_4", "true", 264 "Enable v8.4-A Reliability, Availability and Serviceability extension", 265 [FeatureRAS]>; 266 267def FeatureMPAM : SubtargetFeature< 268 "mpam", "HasMPAM", "true", 269 "Enable v8.4-A Memory system Partitioning and Monitoring extension">; 270 271def FeatureDIT : SubtargetFeature< 272 "dit", "HasDIT", "true", 273 "Enable v8.4-A Data Independent Timing instructions">; 274 275def FeatureTRACEV8_4 : SubtargetFeature< 276 "tracev8.4", "HasTRACEV8_4", "true", 277 "Enable v8.4-A Trace extension">; 278 279def FeatureAM : SubtargetFeature< 280 "am", "HasAM", "true", 281 "Enable v8.4-A Activity Monitors extension">; 282 283def FeatureSEL2 : SubtargetFeature< 284 "sel2", "HasSEL2", "true", 285 "Enable v8.4-A Secure Exception Level 2 extension">; 286 287def FeatureTLB_RMI : SubtargetFeature< 288 "tlb-rmi", "HasTLB_RMI", "true", 289 "Enable v8.4-A TLB Range and Maintenance Instructions">; 290 291def FeatureFMI : SubtargetFeature< 292 "fmi", "HasFMI", "true", 293 "Enable v8.4-A Flag Manipulation Instructions">; 294 295// 8.4 RCPC enchancements: LDAPR & STLR instructions with Immediate Offset 296def FeatureRCPC_IMMO : SubtargetFeature<"rcpc-immo", "HasRCPC_IMMO", "true", 297 "Enable v8.4-A RCPC instructions with Immediate Offsets", 298 [FeatureRCPC]>; 299 300def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates", 301 "NegativeImmediates", "false", 302 "Convert immediates and instructions " 303 "to their negated or complemented " 304 "equivalent when the immediate does " 305 "not fit in the encoding.">; 306 307def FeatureLSLFast : SubtargetFeature< 308 "lsl-fast", "HasLSLFast", "true", 309 "CPU has a fastpath logical shift of up to 3 places">; 310 311def FeatureAggressiveFMA : 312 SubtargetFeature<"aggressive-fma", 313 "HasAggressiveFMA", 314 "true", 315 "Enable Aggressive FMA for floating-point.">; 316 317def FeatureAltFPCmp : SubtargetFeature<"altnzcv", "HasAlternativeNZCV", "true", 318 "Enable alternative NZCV format for floating point comparisons">; 319 320def FeatureFRInt3264 : SubtargetFeature<"fptoint", "HasFRInt3264", "true", 321 "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to " 322 "an integer (in FP format) forcing it to fit into a 32- or 64-bit int" >; 323 324def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict", 325 "true", "Enable architectural speculation restriction" >; 326 327def FeatureSB : SubtargetFeature<"sb", "HasSB", 328 "true", "Enable v8.5 Speculation Barrier" >; 329 330def FeatureSSBS : SubtargetFeature<"ssbs", "HasSSBS", 331 "true", "Enable Speculative Store Bypass Safe bit" >; 332 333def FeaturePredRes : SubtargetFeature<"predres", "HasPredRes", "true", 334 "Enable v8.5a execution and data prediction invalidation instructions" >; 335 336def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP", 337 "true", "Enable v8.5 Cache Clean to Point of Deep Persistence" >; 338 339def FeatureBranchTargetId : SubtargetFeature<"bti", "HasBTI", 340 "true", "Enable Branch Target Identification" >; 341 342def FeatureRandGen : SubtargetFeature<"rand", "HasRandGen", 343 "true", "Enable Random Number generation instructions" >; 344 345def FeatureMTE : SubtargetFeature<"mte", "HasMTE", 346 "true", "Enable Memory Tagging Extension" >; 347 348//===----------------------------------------------------------------------===// 349// Architectures. 350// 351 352def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", 353 "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM, 354 FeaturePAN, FeatureLOR, FeatureVH]>; 355 356def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true", 357 "Support ARM v8.2a instructions", [HasV8_1aOps, FeaturePsUAO, 358 FeaturePAN_RWV, FeatureRAS, FeatureCCPP]>; 359 360def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true", 361 "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC, FeaturePA, 362 FeatureJS, FeatureCCIDX, FeatureComplxNum]>; 363 364def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", 365 "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd, 366 FeatureNV, FeatureRASv8_4, FeatureMPAM, FeatureDIT, 367 FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeatureTLB_RMI, 368 FeatureFMI, FeatureRCPC_IMMO]>; 369 370def HasV8_5aOps : SubtargetFeature< 371 "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions", 372 [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict, 373 FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist, 374 FeatureBranchTargetId] 375>; 376 377//===----------------------------------------------------------------------===// 378// Register File Description 379//===----------------------------------------------------------------------===// 380 381include "AArch64RegisterInfo.td" 382include "AArch64RegisterBanks.td" 383include "AArch64CallingConvention.td" 384 385//===----------------------------------------------------------------------===// 386// Instruction Descriptions 387//===----------------------------------------------------------------------===// 388 389include "AArch64Schedule.td" 390include "AArch64InstrInfo.td" 391include "AArch64SchedPredicates.td" 392include "AArch64SchedPredExynos.td" 393 394def AArch64InstrInfo : InstrInfo; 395 396//===----------------------------------------------------------------------===// 397// Named operands for MRS/MSR/TLBI/... 398//===----------------------------------------------------------------------===// 399 400include "AArch64SystemOperands.td" 401 402//===----------------------------------------------------------------------===// 403// Access to privileged registers 404//===----------------------------------------------------------------------===// 405 406foreach i = 1-3 in 407def FeatureUseEL#i#ForTP : SubtargetFeature<"tpidr-el"#i, "UseEL"#i#"ForTP", 408 "true", "Permit use of TPIDR_EL"#i#" for the TLS base">; 409 410//===----------------------------------------------------------------------===// 411// AArch64 Processors supported. 412// 413 414//===----------------------------------------------------------------------===// 415// Unsupported features to disable for scheduling models 416//===----------------------------------------------------------------------===// 417 418class AArch64Unsupported { list<Predicate> F; } 419 420def SVEUnsupported : AArch64Unsupported { 421 let F = [HasSVE, HasSVE2, HasSVE2AES, HasSVE2SM4, HasSVE2SHA3, 422 HasSVE2BitPerm]; 423} 424 425include "AArch64SchedA53.td" 426include "AArch64SchedA57.td" 427include "AArch64SchedCyclone.td" 428include "AArch64SchedFalkor.td" 429include "AArch64SchedKryo.td" 430include "AArch64SchedExynosM1.td" 431include "AArch64SchedExynosM3.td" 432include "AArch64SchedExynosM4.td" 433include "AArch64SchedThunderX.td" 434include "AArch64SchedThunderX2T99.td" 435 436def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35", 437 "Cortex-A35 ARM processors", [ 438 FeatureCRC, 439 FeatureCrypto, 440 FeatureFPARMv8, 441 FeatureNEON, 442 FeaturePerfMon 443 ]>; 444 445def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", 446 "Cortex-A53 ARM processors", [ 447 FeatureBalanceFPOps, 448 FeatureCRC, 449 FeatureCrypto, 450 FeatureCustomCheapAsMoveHandling, 451 FeatureFPARMv8, 452 FeatureFuseAES, 453 FeatureNEON, 454 FeaturePerfMon, 455 FeaturePostRAScheduler, 456 FeatureUseAA 457 ]>; 458 459def ProcA55 : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55", 460 "Cortex-A55 ARM processors", [ 461 HasV8_2aOps, 462 FeatureCrypto, 463 FeatureFPARMv8, 464 FeatureFuseAES, 465 FeatureNEON, 466 FeatureFullFP16, 467 FeatureDotProd, 468 FeatureRCPC, 469 FeaturePerfMon 470 ]>; 471 472def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", 473 "Cortex-A57 ARM processors", [ 474 FeatureBalanceFPOps, 475 FeatureCRC, 476 FeatureCrypto, 477 FeatureCustomCheapAsMoveHandling, 478 FeatureFPARMv8, 479 FeatureFuseAES, 480 FeatureFuseLiterals, 481 FeatureNEON, 482 FeaturePerfMon, 483 FeaturePostRAScheduler, 484 FeaturePredictableSelectIsExpensive 485 ]>; 486 487def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72", 488 "Cortex-A72 ARM processors", [ 489 FeatureCRC, 490 FeatureCrypto, 491 FeatureFPARMv8, 492 FeatureFuseAES, 493 FeatureNEON, 494 FeaturePerfMon 495 ]>; 496 497def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73", 498 "Cortex-A73 ARM processors", [ 499 FeatureCRC, 500 FeatureCrypto, 501 FeatureFPARMv8, 502 FeatureFuseAES, 503 FeatureNEON, 504 FeaturePerfMon 505 ]>; 506 507def ProcA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75", 508 "Cortex-A75 ARM processors", [ 509 HasV8_2aOps, 510 FeatureCrypto, 511 FeatureFPARMv8, 512 FeatureFuseAES, 513 FeatureNEON, 514 FeatureFullFP16, 515 FeatureDotProd, 516 FeatureRCPC, 517 FeaturePerfMon 518 ]>; 519 520def ProcA76 : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76", 521 "Cortex-A76 ARM processors", [ 522 HasV8_2aOps, 523 FeatureFPARMv8, 524 FeatureNEON, 525 FeatureRCPC, 526 FeatureCrypto, 527 FeatureFullFP16, 528 FeatureDotProd, 529 FeatureSSBS 530 ]>; 531 532// Note that cyclone does not fuse AES instructions, but newer apple chips do 533// perform the fusion and cyclone is used by default when targetting apple OSes. 534def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone", 535 "Cyclone", [ 536 FeatureAlternateSExtLoadCVTF32Pattern, 537 FeatureArithmeticBccFusion, 538 FeatureArithmeticCbzFusion, 539 FeatureCrypto, 540 FeatureDisableLatencySchedHeuristic, 541 FeatureFPARMv8, 542 FeatureFuseAES, 543 FeatureFuseCryptoEOR, 544 FeatureNEON, 545 FeaturePerfMon, 546 FeatureZCRegMove, 547 FeatureZCZeroing, 548 FeatureZCZeroingFPWorkaround 549 ]>; 550 551def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1", 552 "Samsung Exynos-M1 processors", 553 [FeatureSlowPaired128, 554 FeatureCRC, 555 FeatureCrypto, 556 FeatureExynosCheapAsMoveHandling, 557 FeatureForce32BitJumpTables, 558 FeatureFuseAES, 559 FeaturePerfMon, 560 FeaturePostRAScheduler, 561 FeatureSlowMisaligned128Store, 562 FeatureUseRSqrt, 563 FeatureZCZeroingFP]>; 564 565def ProcExynosM2 : SubtargetFeature<"exynosm2", "ARMProcFamily", "ExynosM1", 566 "Samsung Exynos-M2 processors", 567 [FeatureSlowPaired128, 568 FeatureCRC, 569 FeatureCrypto, 570 FeatureExynosCheapAsMoveHandling, 571 FeatureForce32BitJumpTables, 572 FeatureFuseAES, 573 FeaturePerfMon, 574 FeaturePostRAScheduler, 575 FeatureSlowMisaligned128Store, 576 FeatureZCZeroingFP]>; 577 578def ProcExynosM3 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3", 579 "Samsung Exynos-M3 processors", 580 [FeatureCRC, 581 FeatureCrypto, 582 FeatureExynosCheapAsMoveHandling, 583 FeatureForce32BitJumpTables, 584 FeatureFuseAddress, 585 FeatureFuseAES, 586 FeatureFuseCCSelect, 587 FeatureFuseLiterals, 588 FeatureLSLFast, 589 FeaturePerfMon, 590 FeaturePostRAScheduler, 591 FeaturePredictableSelectIsExpensive, 592 FeatureZCZeroingFP]>; 593 594def ProcExynosM4 : SubtargetFeature<"exynosm4", "ARMProcFamily", "ExynosM3", 595 "Samsung Exynos-M4 processors", 596 [HasV8_2aOps, 597 FeatureArithmeticBccFusion, 598 FeatureArithmeticCbzFusion, 599 FeatureCrypto, 600 FeatureDotProd, 601 FeatureExynosCheapAsMoveHandling, 602 FeatureForce32BitJumpTables, 603 FeatureFullFP16, 604 FeatureFuseAddress, 605 FeatureFuseAES, 606 FeatureFuseArithmeticLogic, 607 FeatureFuseCCSelect, 608 FeatureFuseLiterals, 609 FeatureLSLFast, 610 FeaturePerfMon, 611 FeaturePostRAScheduler, 612 FeatureZCZeroing]>; 613 614def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo", 615 "Qualcomm Kryo processors", [ 616 FeatureCRC, 617 FeatureCrypto, 618 FeatureCustomCheapAsMoveHandling, 619 FeatureFPARMv8, 620 FeatureNEON, 621 FeaturePerfMon, 622 FeaturePostRAScheduler, 623 FeaturePredictableSelectIsExpensive, 624 FeatureZCZeroing, 625 FeatureLSLFast 626 ]>; 627 628def ProcFalkor : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor", 629 "Qualcomm Falkor processors", [ 630 FeatureCRC, 631 FeatureCrypto, 632 FeatureCustomCheapAsMoveHandling, 633 FeatureFPARMv8, 634 FeatureNEON, 635 FeaturePerfMon, 636 FeaturePostRAScheduler, 637 FeaturePredictableSelectIsExpensive, 638 FeatureRDM, 639 FeatureZCZeroing, 640 FeatureLSLFast, 641 FeatureSlowSTRQro 642 ]>; 643 644def ProcSaphira : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira", 645 "Qualcomm Saphira processors", [ 646 FeatureCrypto, 647 FeatureCustomCheapAsMoveHandling, 648 FeatureFPARMv8, 649 FeatureNEON, 650 FeatureSPE, 651 FeaturePerfMon, 652 FeaturePostRAScheduler, 653 FeaturePredictableSelectIsExpensive, 654 FeatureZCZeroing, 655 FeatureLSLFast, 656 HasV8_4aOps]>; 657 658def ProcThunderX2T99 : SubtargetFeature<"thunderx2t99", "ARMProcFamily", 659 "ThunderX2T99", 660 "Cavium ThunderX2 processors", [ 661 FeatureAggressiveFMA, 662 FeatureCRC, 663 FeatureCrypto, 664 FeatureFPARMv8, 665 FeatureArithmeticBccFusion, 666 FeatureNEON, 667 FeaturePostRAScheduler, 668 FeaturePredictableSelectIsExpensive, 669 FeatureLSE, 670 HasV8_1aOps]>; 671 672def ProcThunderX : SubtargetFeature<"thunderx", "ARMProcFamily", "ThunderX", 673 "Cavium ThunderX processors", [ 674 FeatureCRC, 675 FeatureCrypto, 676 FeatureFPARMv8, 677 FeaturePerfMon, 678 FeaturePostRAScheduler, 679 FeaturePredictableSelectIsExpensive, 680 FeatureNEON]>; 681 682def ProcThunderXT88 : SubtargetFeature<"thunderxt88", "ARMProcFamily", 683 "ThunderXT88", 684 "Cavium ThunderX processors", [ 685 FeatureCRC, 686 FeatureCrypto, 687 FeatureFPARMv8, 688 FeaturePerfMon, 689 FeaturePostRAScheduler, 690 FeaturePredictableSelectIsExpensive, 691 FeatureNEON]>; 692 693def ProcThunderXT81 : SubtargetFeature<"thunderxt81", "ARMProcFamily", 694 "ThunderXT81", 695 "Cavium ThunderX processors", [ 696 FeatureCRC, 697 FeatureCrypto, 698 FeatureFPARMv8, 699 FeaturePerfMon, 700 FeaturePostRAScheduler, 701 FeaturePredictableSelectIsExpensive, 702 FeatureNEON]>; 703 704def ProcThunderXT83 : SubtargetFeature<"thunderxt83", "ARMProcFamily", 705 "ThunderXT83", 706 "Cavium ThunderX processors", [ 707 FeatureCRC, 708 FeatureCrypto, 709 FeatureFPARMv8, 710 FeaturePerfMon, 711 FeaturePostRAScheduler, 712 FeaturePredictableSelectIsExpensive, 713 FeatureNEON]>; 714 715def ProcTSV110 : SubtargetFeature<"tsv110", "ARMProcFamily", "TSV110", 716 "HiSilicon TS-V110 processors", [ 717 HasV8_2aOps, 718 FeatureCrypto, 719 FeatureCustomCheapAsMoveHandling, 720 FeatureFPARMv8, 721 FeatureFuseAES, 722 FeatureNEON, 723 FeaturePerfMon, 724 FeaturePostRAScheduler, 725 FeatureSPE, 726 FeatureFullFP16, 727 FeatureFP16FML, 728 FeatureDotProd]>; 729 730def : ProcessorModel<"generic", NoSchedModel, [ 731 FeatureFPARMv8, 732 FeatureFuseAES, 733 FeatureNEON, 734 FeaturePerfMon, 735 FeaturePostRAScheduler 736 ]>; 737 738// FIXME: Cortex-A35 and Cortex-A55 are currently modeled as a Cortex-A53. 739def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>; 740def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>; 741def : ProcessorModel<"cortex-a55", CortexA53Model, [ProcA55]>; 742def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>; 743def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA72]>; 744def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA73]>; 745def : ProcessorModel<"cortex-a75", CortexA57Model, [ProcA75]>; 746def : ProcessorModel<"cortex-a76", CortexA57Model, [ProcA76]>; 747def : ProcessorModel<"cortex-a76ae", CortexA57Model, [ProcA76]>; 748def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>; 749def : ProcessorModel<"exynos-m1", ExynosM1Model, [ProcExynosM1]>; 750def : ProcessorModel<"exynos-m2", ExynosM1Model, [ProcExynosM2]>; 751def : ProcessorModel<"exynos-m3", ExynosM3Model, [ProcExynosM3]>; 752def : ProcessorModel<"exynos-m4", ExynosM4Model, [ProcExynosM4]>; 753def : ProcessorModel<"exynos-m5", ExynosM4Model, [ProcExynosM4]>; 754def : ProcessorModel<"falkor", FalkorModel, [ProcFalkor]>; 755def : ProcessorModel<"saphira", FalkorModel, [ProcSaphira]>; 756def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>; 757// Cavium ThunderX/ThunderX T8X Processors 758def : ProcessorModel<"thunderx", ThunderXT8XModel, [ProcThunderX]>; 759def : ProcessorModel<"thunderxt88", ThunderXT8XModel, [ProcThunderXT88]>; 760def : ProcessorModel<"thunderxt81", ThunderXT8XModel, [ProcThunderXT81]>; 761def : ProcessorModel<"thunderxt83", ThunderXT8XModel, [ProcThunderXT83]>; 762// Cavium ThunderX2T9X Processors. Formerly Broadcom Vulcan. 763def : ProcessorModel<"thunderx2t99", ThunderX2T99Model, [ProcThunderX2T99]>; 764// FIXME: HiSilicon TSV110 is currently modeled as a Cortex-A57. 765def : ProcessorModel<"tsv110", CortexA57Model, [ProcTSV110]>; 766 767// Alias for the latest Apple processor model supported by LLVM. 768def : ProcessorModel<"apple-latest", CycloneModel, [ProcCyclone]>; 769 770//===----------------------------------------------------------------------===// 771// Assembly parser 772//===----------------------------------------------------------------------===// 773 774def GenericAsmParserVariant : AsmParserVariant { 775 int Variant = 0; 776 string Name = "generic"; 777 string BreakCharacters = "."; 778 string TokenizingCharacters = "[]*!/"; 779} 780 781def AppleAsmParserVariant : AsmParserVariant { 782 int Variant = 1; 783 string Name = "apple-neon"; 784 string BreakCharacters = "."; 785 string TokenizingCharacters = "[]*!/"; 786} 787 788//===----------------------------------------------------------------------===// 789// Assembly printer 790//===----------------------------------------------------------------------===// 791// AArch64 Uses the MC printer for asm output, so make sure the TableGen 792// AsmWriter bits get associated with the correct class. 793def GenericAsmWriter : AsmWriter { 794 string AsmWriterClassName = "InstPrinter"; 795 int PassSubtarget = 1; 796 int Variant = 0; 797 bit isMCAsmWriter = 1; 798} 799 800def AppleAsmWriter : AsmWriter { 801 let AsmWriterClassName = "AppleInstPrinter"; 802 int PassSubtarget = 1; 803 int Variant = 1; 804 int isMCAsmWriter = 1; 805} 806 807//===----------------------------------------------------------------------===// 808// Target Declaration 809//===----------------------------------------------------------------------===// 810 811def AArch64 : Target { 812 let InstructionSet = AArch64InstrInfo; 813 let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant]; 814 let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter]; 815 let AllowRegisterRenaming = 1; 816} 817 818//===----------------------------------------------------------------------===// 819// Pfm Counters 820//===----------------------------------------------------------------------===// 821 822include "AArch64PfmCounters.td" 823