1//=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// 10//===----------------------------------------------------------------------===// 11 12//===----------------------------------------------------------------------===// 13// Target-independent interfaces which we are implementing. 14//===----------------------------------------------------------------------===// 15 16include "llvm/Target/Target.td" 17 18//===----------------------------------------------------------------------===// 19// AArch64 Subtarget features. 20// 21 22def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true", 23 "Enable ARMv8 FP">; 24 25def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", 26 "Enable Advanced SIMD instructions", [FeatureFPARMv8]>; 27 28def FeatureSM4 : SubtargetFeature< 29 "sm4", "HasSM4", "true", 30 "Enable SM3 and SM4 support", [FeatureNEON]>; 31 32def FeatureSHA2 : SubtargetFeature< 33 "sha2", "HasSHA2", "true", 34 "Enable SHA1 and SHA256 support", [FeatureNEON]>; 35 36def FeatureSHA3 : SubtargetFeature< 37 "sha3", "HasSHA3", "true", 38 "Enable SHA512 and SHA3 support", [FeatureNEON, FeatureSHA2]>; 39 40def FeatureAES : SubtargetFeature< 41 "aes", "HasAES", "true", 42 "Enable AES support", [FeatureNEON]>; 43 44// Crypto has been split up and any combination is now valid (see the 45// crypto defintions above). Also, crypto is now context sensitive: 46// it has a different meaning for e.g. Armv8.4 than it has for Armv8.2. 47// Therefore, we rely on Clang, the user interacing tool, to pass on the 48// appropriate crypto options. But here in the backend, crypto has very little 49// meaning anymore. We kept the Crypto defintion here for backward 50// compatibility, and now imply features SHA2 and AES, which was the 51// "traditional" meaning of Crypto. 52def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", 53 "Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>; 54 55def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", 56 "Enable ARMv8 CRC-32 checksum instructions">; 57 58def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true", 59 "Enable ARMv8 Reliability, Availability and Serviceability Extensions">; 60 61def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true", 62 "Enable ARMv8.1 Large System Extension (LSE) atomic instructions">; 63 64def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true", 65 "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions">; 66 67def FeaturePAN : SubtargetFeature< 68 "pan", "HasPAN", "true", 69 "Enables ARM v8.1 Privileged Access-Never extension">; 70 71def FeatureLOR : SubtargetFeature< 72 "lor", "HasLOR", "true", 73 "Enables ARM v8.1 Limited Ordering Regions extension">; 74 75def FeatureVH : SubtargetFeature< 76 "vh", "HasVH", "true", 77 "Enables ARM v8.1 Virtual Host extension">; 78 79def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", 80 "Enable ARMv8 PMUv3 Performance Monitors extension">; 81 82def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true", 83 "Full FP16", [FeatureFPARMv8]>; 84 85def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true", 86 "Enable FP16 FML instructions", [FeatureFullFP16]>; 87 88def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true", 89 "Enable Statistical Profiling extension">; 90 91def FeaturePAN_RWV : SubtargetFeature< 92 "pan-rwv", "HasPAN_RWV", "true", 93 "Enable v8.2 PAN s1e1R and s1e1W Variants", 94 [FeaturePAN]>; 95 96// UAO PState 97def FeaturePsUAO : SubtargetFeature< "uaops", "HasPsUAO", "true", 98 "Enable v8.2 UAO PState">; 99 100def FeatureCCPP : SubtargetFeature<"ccpp", "HasCCPP", 101 "true", "Enable v8.2 data Cache Clean to Point of Persistence" >; 102 103def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true", 104 "Enable Scalable Vector Extension (SVE) instructions">; 105 106def FeatureSVE2 : SubtargetFeature<"sve2", "HasSVE2", "true", 107 "Enable Scalable Vector Extension 2 (SVE2) instructions", [FeatureSVE]>; 108 109def FeatureSVE2AES : SubtargetFeature<"sve2-aes", "HasSVE2AES", "true", 110 "Enable AES SVE2 instructions", [FeatureSVE2, FeatureAES]>; 111 112def FeatureSVE2SM4 : SubtargetFeature<"sve2-sm4", "HasSVE2SM4", "true", 113 "Enable SM4 SVE2 instructions", [FeatureSVE2, FeatureSM4]>; 114 115def FeatureSVE2SHA3 : SubtargetFeature<"sve2-sha3", "HasSVE2SHA3", "true", 116 "Enable SHA3 SVE2 instructions", [FeatureSVE2, FeatureSHA3]>; 117 118def FeatureSVE2BitPerm : SubtargetFeature<"sve2-bitperm", "HasSVE2BitPerm", "true", 119 "Enable bit permutation SVE2 instructions", [FeatureSVE2]>; 120 121def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true", 122 "Has zero-cycle register moves">; 123 124def FeatureZCZeroingGP : SubtargetFeature<"zcz-gp", "HasZeroCycleZeroingGP", "true", 125 "Has zero-cycle zeroing instructions for generic registers">; 126 127def FeatureZCZeroingFP : SubtargetFeature<"zcz-fp", "HasZeroCycleZeroingFP", "true", 128 "Has zero-cycle zeroing instructions for FP registers">; 129 130def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true", 131 "Has zero-cycle zeroing instructions", 132 [FeatureZCZeroingGP, FeatureZCZeroingFP]>; 133 134/// ... but the floating-point version doesn't quite work in rare cases on older 135/// CPUs. 136def FeatureZCZeroingFPWorkaround : SubtargetFeature<"zcz-fp-workaround", 137 "HasZeroCycleZeroingFPWorkaround", "true", 138 "The zero-cycle floating-point zeroing instruction has a bug">; 139 140def FeatureStrictAlign : SubtargetFeature<"strict-align", 141 "StrictAlign", "true", 142 "Disallow all unaligned memory " 143 "access">; 144 145foreach i = {1-7,9-15,18,20-28} in 146 def FeatureReserveX#i : SubtargetFeature<"reserve-x"#i, "ReserveXRegister["#i#"]", "true", 147 "Reserve X"#i#", making it unavailable " 148 "as a GPR">; 149 150foreach i = {8-15,18} in 151 def FeatureCallSavedX#i : SubtargetFeature<"call-saved-x"#i, 152 "CustomCallSavedXRegs["#i#"]", "true", "Make X"#i#" callee saved.">; 153 154def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true", 155 "Use alias analysis during codegen">; 156 157def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps", 158 "true", 159 "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">; 160 161def FeaturePredictableSelectIsExpensive : SubtargetFeature< 162 "predictable-select-expensive", "PredictableSelectIsExpensive", "true", 163 "Prefer likely predicted branches over selects">; 164 165def FeatureCustomCheapAsMoveHandling : SubtargetFeature<"custom-cheap-as-move", 166 "CustomAsCheapAsMove", "true", 167 "Use custom handling of cheap instructions">; 168 169def FeatureExynosCheapAsMoveHandling : SubtargetFeature<"exynos-cheap-as-move", 170 "ExynosAsCheapAsMove", "true", 171 "Use Exynos specific handling of cheap instructions", 172 [FeatureCustomCheapAsMoveHandling]>; 173 174def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler", 175 "UsePostRAScheduler", "true", "Schedule again after register allocation">; 176 177def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store", 178 "Misaligned128StoreIsSlow", "true", "Misaligned 128 bit stores are slow">; 179 180def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128", 181 "Paired128IsSlow", "true", "Paired 128 bit loads and stores are slow">; 182 183def FeatureSlowSTRQro : SubtargetFeature<"slow-strqro-store", "STRQroIsSlow", 184 "true", "STR of Q register with register offset is slow">; 185 186def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature< 187 "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern", 188 "true", "Use alternative pattern for sextload convert to f32">; 189 190def FeatureArithmeticBccFusion : SubtargetFeature< 191 "arith-bcc-fusion", "HasArithmeticBccFusion", "true", 192 "CPU fuses arithmetic+bcc operations">; 193 194def FeatureArithmeticCbzFusion : SubtargetFeature< 195 "arith-cbz-fusion", "HasArithmeticCbzFusion", "true", 196 "CPU fuses arithmetic + cbz/cbnz operations">; 197 198def FeatureFuseAddress : SubtargetFeature< 199 "fuse-address", "HasFuseAddress", "true", 200 "CPU fuses address generation and memory operations">; 201 202def FeatureFuseAES : SubtargetFeature< 203 "fuse-aes", "HasFuseAES", "true", 204 "CPU fuses AES crypto operations">; 205 206def FeatureFuseArithmeticLogic : SubtargetFeature< 207 "fuse-arith-logic", "HasFuseArithmeticLogic", "true", 208 "CPU fuses arithmetic and logic operations">; 209 210def FeatureFuseCCSelect : SubtargetFeature< 211 "fuse-csel", "HasFuseCCSelect", "true", 212 "CPU fuses conditional select operations">; 213 214def FeatureFuseCryptoEOR : SubtargetFeature< 215 "fuse-crypto-eor", "HasFuseCryptoEOR", "true", 216 "CPU fuses AES/PMULL and EOR operations">; 217 218def FeatureFuseLiterals : SubtargetFeature< 219 "fuse-literals", "HasFuseLiterals", "true", 220 "CPU fuses literal generation operations">; 221 222def FeatureDisableLatencySchedHeuristic : SubtargetFeature< 223 "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true", 224 "Disable latency scheduling heuristic">; 225 226def FeatureForce32BitJumpTables 227 : SubtargetFeature<"force-32bit-jump-tables", "Force32BitJumpTables", "true", 228 "Force jump table entries to be 32-bits wide except at MinSize">; 229 230def FeatureRCPC : SubtargetFeature<"rcpc", "HasRCPC", "true", 231 "Enable support for RCPC extension">; 232 233def FeatureUseRSqrt : SubtargetFeature< 234 "use-reciprocal-square-root", "UseRSqrt", "true", 235 "Use the reciprocal square root approximation">; 236 237def FeatureDotProd : SubtargetFeature< 238 "dotprod", "HasDotProd", "true", 239 "Enable dot product support">; 240 241def FeaturePA : SubtargetFeature< 242 "pa", "HasPA", "true", 243 "Enable v8.3-A Pointer Authentication enchancement">; 244 245def FeatureJS : SubtargetFeature< 246 "jsconv", "HasJS", "true", 247 "Enable v8.3-A JavaScript FP conversion enchancement", 248 [FeatureFPARMv8]>; 249 250def FeatureCCIDX : SubtargetFeature< 251 "ccidx", "HasCCIDX", "true", 252 "Enable v8.3-A Extend of the CCSIDR number of sets">; 253 254def FeatureComplxNum : SubtargetFeature< 255 "complxnum", "HasComplxNum", "true", 256 "Enable v8.3-A Floating-point complex number support", 257 [FeatureNEON]>; 258 259def FeatureNV : SubtargetFeature< 260 "nv", "HasNV", "true", 261 "Enable v8.4-A Nested Virtualization Enchancement">; 262 263def FeatureRASv8_4 : SubtargetFeature< 264 "rasv8_4", "HasRASv8_4", "true", 265 "Enable v8.4-A Reliability, Availability and Serviceability extension", 266 [FeatureRAS]>; 267 268def FeatureMPAM : SubtargetFeature< 269 "mpam", "HasMPAM", "true", 270 "Enable v8.4-A Memory system Partitioning and Monitoring extension">; 271 272def FeatureDIT : SubtargetFeature< 273 "dit", "HasDIT", "true", 274 "Enable v8.4-A Data Independent Timing instructions">; 275 276def FeatureTRACEV8_4 : SubtargetFeature< 277 "tracev8.4", "HasTRACEV8_4", "true", 278 "Enable v8.4-A Trace extension">; 279 280def FeatureAM : SubtargetFeature< 281 "am", "HasAM", "true", 282 "Enable v8.4-A Activity Monitors extension">; 283 284def FeatureSEL2 : SubtargetFeature< 285 "sel2", "HasSEL2", "true", 286 "Enable v8.4-A Secure Exception Level 2 extension">; 287 288def FeaturePMU : SubtargetFeature< 289 "pmu", "HasPMU", "true", 290 "Enable v8.4-A PMU extension">; 291 292def FeatureTLB_RMI : SubtargetFeature< 293 "tlb-rmi", "HasTLB_RMI", "true", 294 "Enable v8.4-A TLB Range and Maintenance Instructions">; 295 296def FeatureFMI : SubtargetFeature< 297 "fmi", "HasFMI", "true", 298 "Enable v8.4-A Flag Manipulation Instructions">; 299 300// 8.4 RCPC enchancements: LDAPR & STLR instructions with Immediate Offset 301def FeatureRCPC_IMMO : SubtargetFeature<"rcpc-immo", "HasRCPC_IMMO", "true", 302 "Enable v8.4-A RCPC instructions with Immediate Offsets", 303 [FeatureRCPC]>; 304 305def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates", 306 "NegativeImmediates", "false", 307 "Convert immediates and instructions " 308 "to their negated or complemented " 309 "equivalent when the immediate does " 310 "not fit in the encoding.">; 311 312def FeatureLSLFast : SubtargetFeature< 313 "lsl-fast", "HasLSLFast", "true", 314 "CPU has a fastpath logical shift of up to 3 places">; 315 316def FeatureAggressiveFMA : 317 SubtargetFeature<"aggressive-fma", 318 "HasAggressiveFMA", 319 "true", 320 "Enable Aggressive FMA for floating-point.">; 321 322def FeatureAltFPCmp : SubtargetFeature<"altnzcv", "HasAlternativeNZCV", "true", 323 "Enable alternative NZCV format for floating point comparisons">; 324 325def FeatureFRInt3264 : SubtargetFeature<"fptoint", "HasFRInt3264", "true", 326 "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to " 327 "an integer (in FP format) forcing it to fit into a 32- or 64-bit int" >; 328 329def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict", 330 "true", "Enable architectural speculation restriction" >; 331 332def FeatureSB : SubtargetFeature<"sb", "HasSB", 333 "true", "Enable v8.5 Speculation Barrier" >; 334 335def FeatureSSBS : SubtargetFeature<"ssbs", "HasSSBS", 336 "true", "Enable Speculative Store Bypass Safe bit" >; 337 338def FeaturePredRes : SubtargetFeature<"predres", "HasPredRes", "true", 339 "Enable v8.5a execution and data prediction invalidation instructions" >; 340 341def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP", 342 "true", "Enable v8.5 Cache Clean to Point of Deep Persistence" >; 343 344def FeatureBranchTargetId : SubtargetFeature<"bti", "HasBTI", 345 "true", "Enable Branch Target Identification" >; 346 347def FeatureRandGen : SubtargetFeature<"rand", "HasRandGen", 348 "true", "Enable Random Number generation instructions" >; 349 350def FeatureMTE : SubtargetFeature<"mte", "HasMTE", 351 "true", "Enable Memory Tagging Extension" >; 352 353def FeatureTRBE : SubtargetFeature<"trbe", "HasTRBE", 354 "true", "Enable Trace Buffer Extension">; 355 356def FeatureETE : SubtargetFeature<"ete", "HasETE", 357 "true", "Enable Embedded Trace Extension", 358 [FeatureTRBE]>; 359 360def FeatureTME : SubtargetFeature<"tme", "HasTME", 361 "true", "Enable Transactional Memory Extension" >; 362 363def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals", 364 "AllowTaggedGlobals", 365 "true", "Use an instruction sequence for taking the address of a global " 366 "that allows a memory tag in the upper address bits">; 367 368//===----------------------------------------------------------------------===// 369// Architectures. 370// 371 372def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", 373 "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM, 374 FeaturePAN, FeatureLOR, FeatureVH]>; 375 376def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true", 377 "Support ARM v8.2a instructions", [HasV8_1aOps, FeaturePsUAO, 378 FeaturePAN_RWV, FeatureRAS, FeatureCCPP]>; 379 380def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true", 381 "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC, FeaturePA, 382 FeatureJS, FeatureCCIDX, FeatureComplxNum]>; 383 384def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", 385 "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd, 386 FeatureNV, FeatureRASv8_4, FeatureMPAM, FeatureDIT, 387 FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeaturePMU, FeatureTLB_RMI, 388 FeatureFMI, FeatureRCPC_IMMO]>; 389 390def HasV8_5aOps : SubtargetFeature< 391 "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions", 392 [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict, 393 FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist, 394 FeatureBranchTargetId] 395>; 396 397//===----------------------------------------------------------------------===// 398// Register File Description 399//===----------------------------------------------------------------------===// 400 401include "AArch64RegisterInfo.td" 402include "AArch64RegisterBanks.td" 403include "AArch64CallingConvention.td" 404 405//===----------------------------------------------------------------------===// 406// Instruction Descriptions 407//===----------------------------------------------------------------------===// 408 409include "AArch64Schedule.td" 410include "AArch64InstrInfo.td" 411include "AArch64SchedPredicates.td" 412include "AArch64SchedPredExynos.td" 413include "AArch64Combine.td" 414 415def AArch64InstrInfo : InstrInfo; 416 417//===----------------------------------------------------------------------===// 418// Named operands for MRS/MSR/TLBI/... 419//===----------------------------------------------------------------------===// 420 421include "AArch64SystemOperands.td" 422 423//===----------------------------------------------------------------------===// 424// Access to privileged registers 425//===----------------------------------------------------------------------===// 426 427foreach i = 1-3 in 428def FeatureUseEL#i#ForTP : SubtargetFeature<"tpidr-el"#i, "UseEL"#i#"ForTP", 429 "true", "Permit use of TPIDR_EL"#i#" for the TLS base">; 430 431//===----------------------------------------------------------------------===// 432// AArch64 Processors supported. 433// 434 435//===----------------------------------------------------------------------===// 436// Unsupported features to disable for scheduling models 437//===----------------------------------------------------------------------===// 438 439class AArch64Unsupported { list<Predicate> F; } 440 441def SVEUnsupported : AArch64Unsupported { 442 let F = [HasSVE, HasSVE2, HasSVE2AES, HasSVE2SM4, HasSVE2SHA3, 443 HasSVE2BitPerm]; 444} 445 446def PAUnsupported : AArch64Unsupported { 447 let F = [HasPA]; 448} 449 450include "AArch64SchedA53.td" 451include "AArch64SchedA57.td" 452include "AArch64SchedCyclone.td" 453include "AArch64SchedFalkor.td" 454include "AArch64SchedKryo.td" 455include "AArch64SchedExynosM3.td" 456include "AArch64SchedExynosM4.td" 457include "AArch64SchedExynosM5.td" 458include "AArch64SchedThunderX.td" 459include "AArch64SchedThunderX2T99.td" 460include "AArch64SchedThunderX3T110.td" 461 462def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35", 463 "Cortex-A35 ARM processors", [ 464 FeatureCRC, 465 FeatureCrypto, 466 FeatureFPARMv8, 467 FeatureNEON, 468 FeaturePerfMon 469 ]>; 470 471def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", 472 "Cortex-A53 ARM processors", [ 473 FeatureBalanceFPOps, 474 FeatureCRC, 475 FeatureCrypto, 476 FeatureCustomCheapAsMoveHandling, 477 FeatureFPARMv8, 478 FeatureFuseAES, 479 FeatureNEON, 480 FeaturePerfMon, 481 FeaturePostRAScheduler, 482 FeatureUseAA 483 ]>; 484 485def ProcA55 : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55", 486 "Cortex-A55 ARM processors", [ 487 HasV8_2aOps, 488 FeatureCrypto, 489 FeatureFPARMv8, 490 FeatureFuseAES, 491 FeatureNEON, 492 FeatureFullFP16, 493 FeatureDotProd, 494 FeatureRCPC, 495 FeaturePerfMon 496 ]>; 497 498def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", 499 "Cortex-A57 ARM processors", [ 500 FeatureBalanceFPOps, 501 FeatureCRC, 502 FeatureCrypto, 503 FeatureCustomCheapAsMoveHandling, 504 FeatureFPARMv8, 505 FeatureFuseAES, 506 FeatureFuseLiterals, 507 FeatureNEON, 508 FeaturePerfMon, 509 FeaturePostRAScheduler, 510 FeaturePredictableSelectIsExpensive 511 ]>; 512 513def ProcA65 : SubtargetFeature<"a65", "ARMProcFamily", "CortexA65", 514 "Cortex-A65 ARM processors", [ 515 HasV8_2aOps, 516 FeatureCrypto, 517 FeatureDotProd, 518 FeatureFPARMv8, 519 FeatureFullFP16, 520 FeatureNEON, 521 FeatureRAS, 522 FeatureRCPC, 523 FeatureSSBS, 524 ]>; 525 526def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72", 527 "Cortex-A72 ARM processors", [ 528 FeatureCRC, 529 FeatureCrypto, 530 FeatureFPARMv8, 531 FeatureFuseAES, 532 FeatureNEON, 533 FeaturePerfMon 534 ]>; 535 536def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73", 537 "Cortex-A73 ARM processors", [ 538 FeatureCRC, 539 FeatureCrypto, 540 FeatureFPARMv8, 541 FeatureFuseAES, 542 FeatureNEON, 543 FeaturePerfMon 544 ]>; 545 546def ProcA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75", 547 "Cortex-A75 ARM processors", [ 548 HasV8_2aOps, 549 FeatureCrypto, 550 FeatureFPARMv8, 551 FeatureFuseAES, 552 FeatureNEON, 553 FeatureFullFP16, 554 FeatureDotProd, 555 FeatureRCPC, 556 FeaturePerfMon 557 ]>; 558 559def ProcA76 : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76", 560 "Cortex-A76 ARM processors", [ 561 HasV8_2aOps, 562 FeatureFPARMv8, 563 FeatureNEON, 564 FeatureRCPC, 565 FeatureCrypto, 566 FeatureFullFP16, 567 FeatureDotProd, 568 FeatureSSBS 569 ]>; 570 571// Note that cyclone does not fuse AES instructions, but newer apple chips do 572// perform the fusion and cyclone is used by default when targetting apple OSes. 573def ProcAppleA7 : SubtargetFeature<"apple-a7", "ARMProcFamily", "AppleA7", 574 "Apple A7 (the CPU formerly known as Cyclone)", [ 575 FeatureAlternateSExtLoadCVTF32Pattern, 576 FeatureArithmeticBccFusion, 577 FeatureArithmeticCbzFusion, 578 FeatureCrypto, 579 FeatureDisableLatencySchedHeuristic, 580 FeatureFPARMv8, 581 FeatureFuseAES, 582 FeatureFuseCryptoEOR, 583 FeatureNEON, 584 FeaturePerfMon, 585 FeatureZCRegMove, 586 FeatureZCZeroing, 587 FeatureZCZeroingFPWorkaround 588 ]>; 589 590def ProcAppleA10 : SubtargetFeature<"apple-a10", "ARMProcFamily", "AppleA10", 591 "Apple A10", [ 592 FeatureAlternateSExtLoadCVTF32Pattern, 593 FeatureArithmeticBccFusion, 594 FeatureArithmeticCbzFusion, 595 FeatureCrypto, 596 FeatureDisableLatencySchedHeuristic, 597 FeatureFPARMv8, 598 FeatureFuseAES, 599 FeatureFuseCryptoEOR, 600 FeatureNEON, 601 FeaturePerfMon, 602 FeatureZCRegMove, 603 FeatureZCZeroing, 604 FeatureCRC, 605 FeatureRDM, 606 FeaturePAN, 607 FeatureLOR, 608 FeatureVH, 609 ]>; 610 611def ProcAppleA11 : SubtargetFeature<"apple-a11", "ARMProcFamily", "AppleA11", 612 "Apple A11", [ 613 FeatureAlternateSExtLoadCVTF32Pattern, 614 FeatureArithmeticBccFusion, 615 FeatureArithmeticCbzFusion, 616 FeatureCrypto, 617 FeatureDisableLatencySchedHeuristic, 618 FeatureFPARMv8, 619 FeatureFuseAES, 620 FeatureFuseCryptoEOR, 621 FeatureNEON, 622 FeaturePerfMon, 623 FeatureZCRegMove, 624 FeatureZCZeroing, 625 FeatureFullFP16, 626 HasV8_2aOps 627 ]>; 628 629def ProcAppleA12 : SubtargetFeature<"apple-a12", "ARMProcFamily", "AppleA12", 630 "Apple A12", [ 631 FeatureAlternateSExtLoadCVTF32Pattern, 632 FeatureArithmeticBccFusion, 633 FeatureArithmeticCbzFusion, 634 FeatureCrypto, 635 FeatureDisableLatencySchedHeuristic, 636 FeatureFPARMv8, 637 FeatureFuseAES, 638 FeatureFuseCryptoEOR, 639 FeatureNEON, 640 FeaturePerfMon, 641 FeatureZCRegMove, 642 FeatureZCZeroing, 643 FeatureFullFP16, 644 HasV8_3aOps 645 ]>; 646 647def ProcAppleA13 : SubtargetFeature<"apple-a13", "ARMProcFamily", "AppleA13", 648 "Apple A13", [ 649 FeatureAlternateSExtLoadCVTF32Pattern, 650 FeatureArithmeticBccFusion, 651 FeatureArithmeticCbzFusion, 652 FeatureCrypto, 653 FeatureDisableLatencySchedHeuristic, 654 FeatureFPARMv8, 655 FeatureFuseAES, 656 FeatureFuseCryptoEOR, 657 FeatureNEON, 658 FeaturePerfMon, 659 FeatureZCRegMove, 660 FeatureZCZeroing, 661 FeatureFullFP16, 662 FeatureFP16FML, 663 FeatureSHA3, 664 HasV8_4aOps 665 ]>; 666 667def ProcExynosM3 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3", 668 "Samsung Exynos-M3 processors", 669 [FeatureCRC, 670 FeatureCrypto, 671 FeatureExynosCheapAsMoveHandling, 672 FeatureForce32BitJumpTables, 673 FeatureFuseAddress, 674 FeatureFuseAES, 675 FeatureFuseCCSelect, 676 FeatureFuseLiterals, 677 FeatureLSLFast, 678 FeaturePerfMon, 679 FeaturePostRAScheduler, 680 FeaturePredictableSelectIsExpensive, 681 FeatureZCZeroingFP]>; 682 683def ProcExynosM4 : SubtargetFeature<"exynosm4", "ARMProcFamily", "ExynosM3", 684 "Samsung Exynos-M4 processors", 685 [HasV8_2aOps, 686 FeatureArithmeticBccFusion, 687 FeatureArithmeticCbzFusion, 688 FeatureCrypto, 689 FeatureDotProd, 690 FeatureExynosCheapAsMoveHandling, 691 FeatureForce32BitJumpTables, 692 FeatureFullFP16, 693 FeatureFuseAddress, 694 FeatureFuseAES, 695 FeatureFuseArithmeticLogic, 696 FeatureFuseCCSelect, 697 FeatureFuseLiterals, 698 FeatureLSLFast, 699 FeaturePerfMon, 700 FeaturePostRAScheduler, 701 FeatureZCZeroing]>; 702 703def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo", 704 "Qualcomm Kryo processors", [ 705 FeatureCRC, 706 FeatureCrypto, 707 FeatureCustomCheapAsMoveHandling, 708 FeatureFPARMv8, 709 FeatureNEON, 710 FeaturePerfMon, 711 FeaturePostRAScheduler, 712 FeaturePredictableSelectIsExpensive, 713 FeatureZCZeroing, 714 FeatureLSLFast 715 ]>; 716 717def ProcFalkor : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor", 718 "Qualcomm Falkor processors", [ 719 FeatureCRC, 720 FeatureCrypto, 721 FeatureCustomCheapAsMoveHandling, 722 FeatureFPARMv8, 723 FeatureNEON, 724 FeaturePerfMon, 725 FeaturePostRAScheduler, 726 FeaturePredictableSelectIsExpensive, 727 FeatureRDM, 728 FeatureZCZeroing, 729 FeatureLSLFast, 730 FeatureSlowSTRQro 731 ]>; 732 733def ProcNeoverseE1 : SubtargetFeature<"neoversee1", "ARMProcFamily", 734 "NeoverseE1", 735 "Neoverse E1 ARM processors", [ 736 HasV8_2aOps, 737 FeatureCrypto, 738 FeatureDotProd, 739 FeatureFPARMv8, 740 FeatureFullFP16, 741 FeatureNEON, 742 FeatureRCPC, 743 FeatureSSBS, 744 ]>; 745 746def ProcNeoverseN1 : SubtargetFeature<"neoversen1", "ARMProcFamily", 747 "NeoverseN1", 748 "Neoverse N1 ARM processors", [ 749 HasV8_2aOps, 750 FeatureCrypto, 751 FeatureDotProd, 752 FeatureFPARMv8, 753 FeatureFullFP16, 754 FeatureNEON, 755 FeatureRCPC, 756 FeatureSPE, 757 FeatureSSBS, 758 ]>; 759 760def ProcSaphira : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira", 761 "Qualcomm Saphira processors", [ 762 FeatureCrypto, 763 FeatureCustomCheapAsMoveHandling, 764 FeatureFPARMv8, 765 FeatureNEON, 766 FeatureSPE, 767 FeaturePerfMon, 768 FeaturePostRAScheduler, 769 FeaturePredictableSelectIsExpensive, 770 FeatureZCZeroing, 771 FeatureLSLFast, 772 HasV8_4aOps]>; 773 774def ProcThunderX2T99 : SubtargetFeature<"thunderx2t99", "ARMProcFamily", 775 "ThunderX2T99", 776 "Cavium ThunderX2 processors", [ 777 FeatureAggressiveFMA, 778 FeatureCRC, 779 FeatureCrypto, 780 FeatureFPARMv8, 781 FeatureArithmeticBccFusion, 782 FeatureNEON, 783 FeaturePostRAScheduler, 784 FeaturePredictableSelectIsExpensive, 785 FeatureLSE, 786 HasV8_1aOps]>; 787 788def ProcThunderX3T110 : SubtargetFeature<"thunderx3t110", "ARMProcFamily", 789 "ThunderX3T110", 790 "Marvell ThunderX3 processors", [ 791 FeatureAggressiveFMA, 792 FeatureCRC, 793 FeatureCrypto, 794 FeatureFPARMv8, 795 FeatureArithmeticBccFusion, 796 FeatureNEON, 797 FeaturePostRAScheduler, 798 FeaturePredictableSelectIsExpensive, 799 FeatureLSE, 800 FeaturePA, 801 FeatureUseAA, 802 FeatureBalanceFPOps, 803 FeaturePerfMon, 804 FeatureStrictAlign, 805 HasV8_3aOps]>; 806 807def ProcThunderX : SubtargetFeature<"thunderx", "ARMProcFamily", "ThunderX", 808 "Cavium ThunderX processors", [ 809 FeatureCRC, 810 FeatureCrypto, 811 FeatureFPARMv8, 812 FeaturePerfMon, 813 FeaturePostRAScheduler, 814 FeaturePredictableSelectIsExpensive, 815 FeatureNEON]>; 816 817def ProcThunderXT88 : SubtargetFeature<"thunderxt88", "ARMProcFamily", 818 "ThunderXT88", 819 "Cavium ThunderX processors", [ 820 FeatureCRC, 821 FeatureCrypto, 822 FeatureFPARMv8, 823 FeaturePerfMon, 824 FeaturePostRAScheduler, 825 FeaturePredictableSelectIsExpensive, 826 FeatureNEON]>; 827 828def ProcThunderXT81 : SubtargetFeature<"thunderxt81", "ARMProcFamily", 829 "ThunderXT81", 830 "Cavium ThunderX processors", [ 831 FeatureCRC, 832 FeatureCrypto, 833 FeatureFPARMv8, 834 FeaturePerfMon, 835 FeaturePostRAScheduler, 836 FeaturePredictableSelectIsExpensive, 837 FeatureNEON]>; 838 839def ProcThunderXT83 : SubtargetFeature<"thunderxt83", "ARMProcFamily", 840 "ThunderXT83", 841 "Cavium ThunderX processors", [ 842 FeatureCRC, 843 FeatureCrypto, 844 FeatureFPARMv8, 845 FeaturePerfMon, 846 FeaturePostRAScheduler, 847 FeaturePredictableSelectIsExpensive, 848 FeatureNEON]>; 849 850def ProcTSV110 : SubtargetFeature<"tsv110", "ARMProcFamily", "TSV110", 851 "HiSilicon TS-V110 processors", [ 852 HasV8_2aOps, 853 FeatureCrypto, 854 FeatureCustomCheapAsMoveHandling, 855 FeatureFPARMv8, 856 FeatureFuseAES, 857 FeatureNEON, 858 FeaturePerfMon, 859 FeaturePostRAScheduler, 860 FeatureSPE, 861 FeatureFullFP16, 862 FeatureFP16FML, 863 FeatureDotProd]>; 864 865def : ProcessorModel<"generic", NoSchedModel, [ 866 FeatureFPARMv8, 867 FeatureFuseAES, 868 FeatureNEON, 869 FeaturePerfMon, 870 FeaturePostRAScheduler, 871// ETE and TRBE are future architecture extensions. We temporariliy enable them 872// by default for users targeting generic AArch64, until it is decided in which 873// armv8.x-a architecture revision they will end up. The extensions do not 874// affect code generated by the compiler and can be used only by explicitly 875// mentioning the new system register names in assembly. 876 FeatureETE 877 ]>; 878 879def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>; 880def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>; 881def : ProcessorModel<"cortex-a55", CortexA53Model, [ProcA55]>; 882def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>; 883def : ProcessorModel<"cortex-a65", CortexA53Model, [ProcA65]>; 884def : ProcessorModel<"cortex-a65ae", CortexA53Model, [ProcA65]>; 885def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA72]>; 886def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA73]>; 887def : ProcessorModel<"cortex-a75", CortexA57Model, [ProcA75]>; 888def : ProcessorModel<"cortex-a76", CortexA57Model, [ProcA76]>; 889def : ProcessorModel<"cortex-a76ae", CortexA57Model, [ProcA76]>; 890def : ProcessorModel<"neoverse-e1", CortexA53Model, [ProcNeoverseE1]>; 891def : ProcessorModel<"neoverse-n1", CortexA57Model, [ProcNeoverseN1]>; 892def : ProcessorModel<"exynos-m3", ExynosM3Model, [ProcExynosM3]>; 893def : ProcessorModel<"exynos-m4", ExynosM4Model, [ProcExynosM4]>; 894def : ProcessorModel<"exynos-m5", ExynosM5Model, [ProcExynosM4]>; 895def : ProcessorModel<"falkor", FalkorModel, [ProcFalkor]>; 896def : ProcessorModel<"saphira", FalkorModel, [ProcSaphira]>; 897def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>; 898// Cavium ThunderX/ThunderX T8X Processors 899def : ProcessorModel<"thunderx", ThunderXT8XModel, [ProcThunderX]>; 900def : ProcessorModel<"thunderxt88", ThunderXT8XModel, [ProcThunderXT88]>; 901def : ProcessorModel<"thunderxt81", ThunderXT8XModel, [ProcThunderXT81]>; 902def : ProcessorModel<"thunderxt83", ThunderXT8XModel, [ProcThunderXT83]>; 903// Cavium ThunderX2T9X Processors. Formerly Broadcom Vulcan. 904def : ProcessorModel<"thunderx2t99", ThunderX2T99Model, [ProcThunderX2T99]>; 905// Marvell ThunderX3T110 Processors. 906def : ProcessorModel<"thunderx3t110", ThunderX3T110Model, [ProcThunderX3T110]>; 907// FIXME: HiSilicon TSV110 is currently modeled as a Cortex-A57. 908def : ProcessorModel<"tsv110", CortexA57Model, [ProcTSV110]>; 909 910// Support cyclone as an alias for apple-a7 so we can still LTO old bitcode. 911def : ProcessorModel<"cyclone", CycloneModel, [ProcAppleA7]>; 912 913// iPhone and iPad CPUs 914def : ProcessorModel<"apple-a7", CycloneModel, [ProcAppleA7]>; 915def : ProcessorModel<"apple-a8", CycloneModel, [ProcAppleA7]>; 916def : ProcessorModel<"apple-a9", CycloneModel, [ProcAppleA7]>; 917def : ProcessorModel<"apple-a10", CycloneModel, [ProcAppleA10]>; 918def : ProcessorModel<"apple-a11", CycloneModel, [ProcAppleA11]>; 919def : ProcessorModel<"apple-a12", CycloneModel, [ProcAppleA12]>; 920def : ProcessorModel<"apple-a13", CycloneModel, [ProcAppleA13]>; 921 922// watch CPUs. 923def : ProcessorModel<"apple-s4", CycloneModel, [ProcAppleA12]>; 924def : ProcessorModel<"apple-s5", CycloneModel, [ProcAppleA12]>; 925 926// Alias for the latest Apple processor model supported by LLVM. 927def : ProcessorModel<"apple-latest", CycloneModel, [ProcAppleA13]>; 928 929//===----------------------------------------------------------------------===// 930// Assembly parser 931//===----------------------------------------------------------------------===// 932 933def GenericAsmParserVariant : AsmParserVariant { 934 int Variant = 0; 935 string Name = "generic"; 936 string BreakCharacters = "."; 937 string TokenizingCharacters = "[]*!/"; 938} 939 940def AppleAsmParserVariant : AsmParserVariant { 941 int Variant = 1; 942 string Name = "apple-neon"; 943 string BreakCharacters = "."; 944 string TokenizingCharacters = "[]*!/"; 945} 946 947//===----------------------------------------------------------------------===// 948// Assembly printer 949//===----------------------------------------------------------------------===// 950// AArch64 Uses the MC printer for asm output, so make sure the TableGen 951// AsmWriter bits get associated with the correct class. 952def GenericAsmWriter : AsmWriter { 953 string AsmWriterClassName = "InstPrinter"; 954 int PassSubtarget = 1; 955 int Variant = 0; 956 bit isMCAsmWriter = 1; 957} 958 959def AppleAsmWriter : AsmWriter { 960 let AsmWriterClassName = "AppleInstPrinter"; 961 int PassSubtarget = 1; 962 int Variant = 1; 963 int isMCAsmWriter = 1; 964} 965 966//===----------------------------------------------------------------------===// 967// Target Declaration 968//===----------------------------------------------------------------------===// 969 970def AArch64 : Target { 971 let InstructionSet = AArch64InstrInfo; 972 let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant]; 973 let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter]; 974 let AllowRegisterRenaming = 1; 975} 976 977//===----------------------------------------------------------------------===// 978// Pfm Counters 979//===----------------------------------------------------------------------===// 980 981include "AArch64PfmCounters.td" 982