1//=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// 10//===----------------------------------------------------------------------===// 11 12//===----------------------------------------------------------------------===// 13// Target-independent interfaces which we are implementing. 14//===----------------------------------------------------------------------===// 15 16include "llvm/Target/Target.td" 17 18//===----------------------------------------------------------------------===// 19// AArch64 Subtarget features. 20// 21 22def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true", 23 "Enable ARMv8 FP">; 24 25def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", 26 "Enable Advanced SIMD instructions", [FeatureFPARMv8]>; 27 28def FeatureSM4 : SubtargetFeature< 29 "sm4", "HasSM4", "true", 30 "Enable SM3 and SM4 support", [FeatureNEON]>; 31 32def FeatureSHA2 : SubtargetFeature< 33 "sha2", "HasSHA2", "true", 34 "Enable SHA1 and SHA256 support", [FeatureNEON]>; 35 36def FeatureSHA3 : SubtargetFeature< 37 "sha3", "HasSHA3", "true", 38 "Enable SHA512 and SHA3 support", [FeatureNEON, FeatureSHA2]>; 39 40def FeatureAES : SubtargetFeature< 41 "aes", "HasAES", "true", 42 "Enable AES support", [FeatureNEON]>; 43 44// Crypto has been split up and any combination is now valid (see the 45// crypto defintions above). Also, crypto is now context sensitive: 46// it has a different meaning for e.g. Armv8.4 than it has for Armv8.2. 47// Therefore, we rely on Clang, the user interacing tool, to pass on the 48// appropriate crypto options. But here in the backend, crypto has very little 49// meaning anymore. We kept the Crypto defintion here for backward 50// compatibility, and now imply features SHA2 and AES, which was the 51// "traditional" meaning of Crypto. 52def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", 53 "Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>; 54 55def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", 56 "Enable ARMv8 CRC-32 checksum instructions">; 57 58def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true", 59 "Enable ARMv8 Reliability, Availability and Serviceability Extensions">; 60 61def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true", 62 "Enable ARMv8.1 Large System Extension (LSE) atomic instructions">; 63 64def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true", 65 "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions">; 66 67def FeaturePAN : SubtargetFeature< 68 "pan", "HasPAN", "true", 69 "Enables ARM v8.1 Privileged Access-Never extension">; 70 71def FeatureLOR : SubtargetFeature< 72 "lor", "HasLOR", "true", 73 "Enables ARM v8.1 Limited Ordering Regions extension">; 74 75def FeatureVH : SubtargetFeature< 76 "vh", "HasVH", "true", 77 "Enables ARM v8.1 Virtual Host extension">; 78 79def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", 80 "Enable ARMv8 PMUv3 Performance Monitors extension">; 81 82def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true", 83 "Full FP16", [FeatureFPARMv8]>; 84 85def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true", 86 "Enable FP16 FML instructions", [FeatureFullFP16]>; 87 88def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true", 89 "Enable Statistical Profiling extension">; 90 91def FeaturePAN_RWV : SubtargetFeature< 92 "pan-rwv", "HasPAN_RWV", "true", 93 "Enable v8.2 PAN s1e1R and s1e1W Variants", 94 [FeaturePAN]>; 95 96// UAO PState 97def FeaturePsUAO : SubtargetFeature< "uaops", "HasPsUAO", "true", 98 "Enable v8.2 UAO PState">; 99 100def FeatureCCPP : SubtargetFeature<"ccpp", "HasCCPP", 101 "true", "Enable v8.2 data Cache Clean to Point of Persistence" >; 102 103def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true", 104 "Enable Scalable Vector Extension (SVE) instructions">; 105 106def FeatureSVE2 : SubtargetFeature<"sve2", "HasSVE2", "true", 107 "Enable Scalable Vector Extension 2 (SVE2) instructions", [FeatureSVE]>; 108 109def FeatureSVE2AES : SubtargetFeature<"sve2-aes", "HasSVE2AES", "true", 110 "Enable AES SVE2 instructions", [FeatureSVE2, FeatureAES]>; 111 112def FeatureSVE2SM4 : SubtargetFeature<"sve2-sm4", "HasSVE2SM4", "true", 113 "Enable SM4 SVE2 instructions", [FeatureSVE2, FeatureSM4]>; 114 115def FeatureSVE2SHA3 : SubtargetFeature<"sve2-sha3", "HasSVE2SHA3", "true", 116 "Enable SHA3 SVE2 instructions", [FeatureSVE2, FeatureSHA3]>; 117 118def FeatureSVE2BitPerm : SubtargetFeature<"sve2-bitperm", "HasSVE2BitPerm", "true", 119 "Enable bit permutation SVE2 instructions", [FeatureSVE2]>; 120 121def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true", 122 "Has zero-cycle register moves">; 123 124def FeatureZCZeroingGP : SubtargetFeature<"zcz-gp", "HasZeroCycleZeroingGP", "true", 125 "Has zero-cycle zeroing instructions for generic registers">; 126 127def FeatureZCZeroingFP : SubtargetFeature<"zcz-fp", "HasZeroCycleZeroingFP", "true", 128 "Has zero-cycle zeroing instructions for FP registers">; 129 130def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true", 131 "Has zero-cycle zeroing instructions", 132 [FeatureZCZeroingGP, FeatureZCZeroingFP]>; 133 134/// ... but the floating-point version doesn't quite work in rare cases on older 135/// CPUs. 136def FeatureZCZeroingFPWorkaround : SubtargetFeature<"zcz-fp-workaround", 137 "HasZeroCycleZeroingFPWorkaround", "true", 138 "The zero-cycle floating-point zeroing instruction has a bug">; 139 140def FeatureStrictAlign : SubtargetFeature<"strict-align", 141 "StrictAlign", "true", 142 "Disallow all unaligned memory " 143 "access">; 144 145foreach i = {1-7,9-15,18,20-28} in 146 def FeatureReserveX#i : SubtargetFeature<"reserve-x"#i, "ReserveXRegister["#i#"]", "true", 147 "Reserve X"#i#", making it unavailable " 148 "as a GPR">; 149 150foreach i = {8-15,18} in 151 def FeatureCallSavedX#i : SubtargetFeature<"call-saved-x"#i, 152 "CustomCallSavedXRegs["#i#"]", "true", "Make X"#i#" callee saved.">; 153 154def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true", 155 "Use alias analysis during codegen">; 156 157def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps", 158 "true", 159 "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">; 160 161def FeaturePredictableSelectIsExpensive : SubtargetFeature< 162 "predictable-select-expensive", "PredictableSelectIsExpensive", "true", 163 "Prefer likely predicted branches over selects">; 164 165def FeatureCustomCheapAsMoveHandling : SubtargetFeature<"custom-cheap-as-move", 166 "CustomAsCheapAsMove", "true", 167 "Use custom handling of cheap instructions">; 168 169def FeatureExynosCheapAsMoveHandling : SubtargetFeature<"exynos-cheap-as-move", 170 "ExynosAsCheapAsMove", "true", 171 "Use Exynos specific handling of cheap instructions", 172 [FeatureCustomCheapAsMoveHandling]>; 173 174def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler", 175 "UsePostRAScheduler", "true", "Schedule again after register allocation">; 176 177def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store", 178 "Misaligned128StoreIsSlow", "true", "Misaligned 128 bit stores are slow">; 179 180def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128", 181 "Paired128IsSlow", "true", "Paired 128 bit loads and stores are slow">; 182 183def FeatureSlowSTRQro : SubtargetFeature<"slow-strqro-store", "STRQroIsSlow", 184 "true", "STR of Q register with register offset is slow">; 185 186def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature< 187 "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern", 188 "true", "Use alternative pattern for sextload convert to f32">; 189 190def FeatureArithmeticBccFusion : SubtargetFeature< 191 "arith-bcc-fusion", "HasArithmeticBccFusion", "true", 192 "CPU fuses arithmetic+bcc operations">; 193 194def FeatureArithmeticCbzFusion : SubtargetFeature< 195 "arith-cbz-fusion", "HasArithmeticCbzFusion", "true", 196 "CPU fuses arithmetic + cbz/cbnz operations">; 197 198def FeatureFuseAddress : SubtargetFeature< 199 "fuse-address", "HasFuseAddress", "true", 200 "CPU fuses address generation and memory operations">; 201 202def FeatureFuseAES : SubtargetFeature< 203 "fuse-aes", "HasFuseAES", "true", 204 "CPU fuses AES crypto operations">; 205 206def FeatureFuseArithmeticLogic : SubtargetFeature< 207 "fuse-arith-logic", "HasFuseArithmeticLogic", "true", 208 "CPU fuses arithmetic and logic operations">; 209 210def FeatureFuseCCSelect : SubtargetFeature< 211 "fuse-csel", "HasFuseCCSelect", "true", 212 "CPU fuses conditional select operations">; 213 214def FeatureFuseCryptoEOR : SubtargetFeature< 215 "fuse-crypto-eor", "HasFuseCryptoEOR", "true", 216 "CPU fuses AES/PMULL and EOR operations">; 217 218def FeatureFuseLiterals : SubtargetFeature< 219 "fuse-literals", "HasFuseLiterals", "true", 220 "CPU fuses literal generation operations">; 221 222def FeatureDisableLatencySchedHeuristic : SubtargetFeature< 223 "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true", 224 "Disable latency scheduling heuristic">; 225 226def FeatureForce32BitJumpTables 227 : SubtargetFeature<"force-32bit-jump-tables", "Force32BitJumpTables", "true", 228 "Force jump table entries to be 32-bits wide except at MinSize">; 229 230def FeatureRCPC : SubtargetFeature<"rcpc", "HasRCPC", "true", 231 "Enable support for RCPC extension">; 232 233def FeatureUseRSqrt : SubtargetFeature< 234 "use-reciprocal-square-root", "UseRSqrt", "true", 235 "Use the reciprocal square root approximation">; 236 237def FeatureDotProd : SubtargetFeature< 238 "dotprod", "HasDotProd", "true", 239 "Enable dot product support">; 240 241def FeaturePA : SubtargetFeature< 242 "pa", "HasPA", "true", 243 "Enable v8.3-A Pointer Authentication enchancement">; 244 245def FeatureJS : SubtargetFeature< 246 "jsconv", "HasJS", "true", 247 "Enable v8.3-A JavaScript FP conversion enchancement", 248 [FeatureFPARMv8]>; 249 250def FeatureCCIDX : SubtargetFeature< 251 "ccidx", "HasCCIDX", "true", 252 "Enable v8.3-A Extend of the CCSIDR number of sets">; 253 254def FeatureComplxNum : SubtargetFeature< 255 "complxnum", "HasComplxNum", "true", 256 "Enable v8.3-A Floating-point complex number support", 257 [FeatureNEON]>; 258 259def FeatureNV : SubtargetFeature< 260 "nv", "HasNV", "true", 261 "Enable v8.4-A Nested Virtualization Enchancement">; 262 263def FeatureRASv8_4 : SubtargetFeature< 264 "rasv8_4", "HasRASv8_4", "true", 265 "Enable v8.4-A Reliability, Availability and Serviceability extension", 266 [FeatureRAS]>; 267 268def FeatureMPAM : SubtargetFeature< 269 "mpam", "HasMPAM", "true", 270 "Enable v8.4-A Memory system Partitioning and Monitoring extension">; 271 272def FeatureDIT : SubtargetFeature< 273 "dit", "HasDIT", "true", 274 "Enable v8.4-A Data Independent Timing instructions">; 275 276def FeatureTRACEV8_4 : SubtargetFeature< 277 "tracev8.4", "HasTRACEV8_4", "true", 278 "Enable v8.4-A Trace extension">; 279 280def FeatureAM : SubtargetFeature< 281 "am", "HasAM", "true", 282 "Enable v8.4-A Activity Monitors extension">; 283 284def FeatureSEL2 : SubtargetFeature< 285 "sel2", "HasSEL2", "true", 286 "Enable v8.4-A Secure Exception Level 2 extension">; 287 288def FeaturePMU : SubtargetFeature< 289 "pmu", "HasPMU", "true", 290 "Enable v8.4-A PMU extension">; 291 292def FeatureTLB_RMI : SubtargetFeature< 293 "tlb-rmi", "HasTLB_RMI", "true", 294 "Enable v8.4-A TLB Range and Maintenance Instructions">; 295 296def FeatureFMI : SubtargetFeature< 297 "fmi", "HasFMI", "true", 298 "Enable v8.4-A Flag Manipulation Instructions">; 299 300// 8.4 RCPC enchancements: LDAPR & STLR instructions with Immediate Offset 301def FeatureRCPC_IMMO : SubtargetFeature<"rcpc-immo", "HasRCPC_IMMO", "true", 302 "Enable v8.4-A RCPC instructions with Immediate Offsets", 303 [FeatureRCPC]>; 304 305def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates", 306 "NegativeImmediates", "false", 307 "Convert immediates and instructions " 308 "to their negated or complemented " 309 "equivalent when the immediate does " 310 "not fit in the encoding.">; 311 312def FeatureLSLFast : SubtargetFeature< 313 "lsl-fast", "HasLSLFast", "true", 314 "CPU has a fastpath logical shift of up to 3 places">; 315 316def FeatureAggressiveFMA : 317 SubtargetFeature<"aggressive-fma", 318 "HasAggressiveFMA", 319 "true", 320 "Enable Aggressive FMA for floating-point.">; 321 322def FeatureAltFPCmp : SubtargetFeature<"altnzcv", "HasAlternativeNZCV", "true", 323 "Enable alternative NZCV format for floating point comparisons">; 324 325def FeatureFRInt3264 : SubtargetFeature<"fptoint", "HasFRInt3264", "true", 326 "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to " 327 "an integer (in FP format) forcing it to fit into a 32- or 64-bit int" >; 328 329def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict", 330 "true", "Enable architectural speculation restriction" >; 331 332def FeatureSB : SubtargetFeature<"sb", "HasSB", 333 "true", "Enable v8.5 Speculation Barrier" >; 334 335def FeatureSSBS : SubtargetFeature<"ssbs", "HasSSBS", 336 "true", "Enable Speculative Store Bypass Safe bit" >; 337 338def FeaturePredRes : SubtargetFeature<"predres", "HasPredRes", "true", 339 "Enable v8.5a execution and data prediction invalidation instructions" >; 340 341def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP", 342 "true", "Enable v8.5 Cache Clean to Point of Deep Persistence" >; 343 344def FeatureBranchTargetId : SubtargetFeature<"bti", "HasBTI", 345 "true", "Enable Branch Target Identification" >; 346 347def FeatureRandGen : SubtargetFeature<"rand", "HasRandGen", 348 "true", "Enable Random Number generation instructions" >; 349 350def FeatureMTE : SubtargetFeature<"mte", "HasMTE", 351 "true", "Enable Memory Tagging Extension" >; 352 353def FeatureTRBE : SubtargetFeature<"trbe", "HasTRBE", 354 "true", "Enable Trace Buffer Extension">; 355 356def FeatureETE : SubtargetFeature<"ete", "HasETE", 357 "true", "Enable Embedded Trace Extension", 358 [FeatureTRBE]>; 359 360def FeatureTME : SubtargetFeature<"tme", "HasTME", 361 "true", "Enable Transactional Memory Extension" >; 362 363def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals", 364 "AllowTaggedGlobals", 365 "true", "Use an instruction sequence for taking the address of a global " 366 "that allows a memory tag in the upper address bits">; 367 368//===----------------------------------------------------------------------===// 369// Architectures. 370// 371 372def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", 373 "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM, 374 FeaturePAN, FeatureLOR, FeatureVH]>; 375 376def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true", 377 "Support ARM v8.2a instructions", [HasV8_1aOps, FeaturePsUAO, 378 FeaturePAN_RWV, FeatureRAS, FeatureCCPP]>; 379 380def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true", 381 "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC, FeaturePA, 382 FeatureJS, FeatureCCIDX, FeatureComplxNum]>; 383 384def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", 385 "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd, 386 FeatureNV, FeatureRASv8_4, FeatureMPAM, FeatureDIT, 387 FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeaturePMU, FeatureTLB_RMI, 388 FeatureFMI, FeatureRCPC_IMMO]>; 389 390def HasV8_5aOps : SubtargetFeature< 391 "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions", 392 [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict, 393 FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist, 394 FeatureBranchTargetId] 395>; 396 397//===----------------------------------------------------------------------===// 398// Register File Description 399//===----------------------------------------------------------------------===// 400 401include "AArch64RegisterInfo.td" 402include "AArch64RegisterBanks.td" 403include "AArch64CallingConvention.td" 404 405//===----------------------------------------------------------------------===// 406// Instruction Descriptions 407//===----------------------------------------------------------------------===// 408 409include "AArch64Schedule.td" 410include "AArch64InstrInfo.td" 411include "AArch64SchedPredicates.td" 412include "AArch64SchedPredExynos.td" 413include "AArch64Combine.td" 414 415def AArch64InstrInfo : InstrInfo; 416 417//===----------------------------------------------------------------------===// 418// Named operands for MRS/MSR/TLBI/... 419//===----------------------------------------------------------------------===// 420 421include "AArch64SystemOperands.td" 422 423//===----------------------------------------------------------------------===// 424// Access to privileged registers 425//===----------------------------------------------------------------------===// 426 427foreach i = 1-3 in 428def FeatureUseEL#i#ForTP : SubtargetFeature<"tpidr-el"#i, "UseEL"#i#"ForTP", 429 "true", "Permit use of TPIDR_EL"#i#" for the TLS base">; 430 431//===----------------------------------------------------------------------===// 432// AArch64 Processors supported. 433// 434 435//===----------------------------------------------------------------------===// 436// Unsupported features to disable for scheduling models 437//===----------------------------------------------------------------------===// 438 439class AArch64Unsupported { list<Predicate> F; } 440 441def SVEUnsupported : AArch64Unsupported { 442 let F = [HasSVE, HasSVE2, HasSVE2AES, HasSVE2SM4, HasSVE2SHA3, 443 HasSVE2BitPerm]; 444} 445 446include "AArch64SchedA53.td" 447include "AArch64SchedA57.td" 448include "AArch64SchedCyclone.td" 449include "AArch64SchedFalkor.td" 450include "AArch64SchedKryo.td" 451include "AArch64SchedExynosM3.td" 452include "AArch64SchedExynosM4.td" 453include "AArch64SchedExynosM5.td" 454include "AArch64SchedThunderX.td" 455include "AArch64SchedThunderX2T99.td" 456 457def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35", 458 "Cortex-A35 ARM processors", [ 459 FeatureCRC, 460 FeatureCrypto, 461 FeatureFPARMv8, 462 FeatureNEON, 463 FeaturePerfMon 464 ]>; 465 466def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", 467 "Cortex-A53 ARM processors", [ 468 FeatureBalanceFPOps, 469 FeatureCRC, 470 FeatureCrypto, 471 FeatureCustomCheapAsMoveHandling, 472 FeatureFPARMv8, 473 FeatureFuseAES, 474 FeatureNEON, 475 FeaturePerfMon, 476 FeaturePostRAScheduler, 477 FeatureUseAA 478 ]>; 479 480def ProcA55 : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55", 481 "Cortex-A55 ARM processors", [ 482 HasV8_2aOps, 483 FeatureCrypto, 484 FeatureFPARMv8, 485 FeatureFuseAES, 486 FeatureNEON, 487 FeatureFullFP16, 488 FeatureDotProd, 489 FeatureRCPC, 490 FeaturePerfMon 491 ]>; 492 493def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", 494 "Cortex-A57 ARM processors", [ 495 FeatureBalanceFPOps, 496 FeatureCRC, 497 FeatureCrypto, 498 FeatureCustomCheapAsMoveHandling, 499 FeatureFPARMv8, 500 FeatureFuseAES, 501 FeatureFuseLiterals, 502 FeatureNEON, 503 FeaturePerfMon, 504 FeaturePostRAScheduler, 505 FeaturePredictableSelectIsExpensive 506 ]>; 507 508def ProcA65 : SubtargetFeature<"a65", "ARMProcFamily", "CortexA65", 509 "Cortex-A65 ARM processors", [ 510 HasV8_2aOps, 511 FeatureCrypto, 512 FeatureDotProd, 513 FeatureFPARMv8, 514 FeatureFullFP16, 515 FeatureNEON, 516 FeatureRAS, 517 FeatureRCPC, 518 FeatureSSBS, 519 ]>; 520 521def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72", 522 "Cortex-A72 ARM processors", [ 523 FeatureCRC, 524 FeatureCrypto, 525 FeatureFPARMv8, 526 FeatureFuseAES, 527 FeatureNEON, 528 FeaturePerfMon 529 ]>; 530 531def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73", 532 "Cortex-A73 ARM processors", [ 533 FeatureCRC, 534 FeatureCrypto, 535 FeatureFPARMv8, 536 FeatureFuseAES, 537 FeatureNEON, 538 FeaturePerfMon 539 ]>; 540 541def ProcA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75", 542 "Cortex-A75 ARM processors", [ 543 HasV8_2aOps, 544 FeatureCrypto, 545 FeatureFPARMv8, 546 FeatureFuseAES, 547 FeatureNEON, 548 FeatureFullFP16, 549 FeatureDotProd, 550 FeatureRCPC, 551 FeaturePerfMon 552 ]>; 553 554def ProcA76 : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76", 555 "Cortex-A76 ARM processors", [ 556 HasV8_2aOps, 557 FeatureFPARMv8, 558 FeatureNEON, 559 FeatureRCPC, 560 FeatureCrypto, 561 FeatureFullFP16, 562 FeatureDotProd, 563 FeatureSSBS 564 ]>; 565 566// Note that cyclone does not fuse AES instructions, but newer apple chips do 567// perform the fusion and cyclone is used by default when targetting apple OSes. 568def ProcAppleA7 : SubtargetFeature<"apple-a7", "ARMProcFamily", "AppleA7", 569 "Apple A7 (the CPU formerly known as Cyclone)", [ 570 FeatureAlternateSExtLoadCVTF32Pattern, 571 FeatureArithmeticBccFusion, 572 FeatureArithmeticCbzFusion, 573 FeatureCrypto, 574 FeatureDisableLatencySchedHeuristic, 575 FeatureFPARMv8, 576 FeatureFuseAES, 577 FeatureFuseCryptoEOR, 578 FeatureNEON, 579 FeaturePerfMon, 580 FeatureZCRegMove, 581 FeatureZCZeroing, 582 FeatureZCZeroingFPWorkaround 583 ]>; 584 585def ProcAppleA10 : SubtargetFeature<"apple-a10", "ARMProcFamily", "AppleA10", 586 "Apple A10", [ 587 FeatureAlternateSExtLoadCVTF32Pattern, 588 FeatureArithmeticBccFusion, 589 FeatureArithmeticCbzFusion, 590 FeatureCrypto, 591 FeatureDisableLatencySchedHeuristic, 592 FeatureFPARMv8, 593 FeatureFuseAES, 594 FeatureFuseCryptoEOR, 595 FeatureNEON, 596 FeaturePerfMon, 597 FeatureZCRegMove, 598 FeatureZCZeroing, 599 FeatureCRC, 600 FeatureRDM, 601 FeaturePAN, 602 FeatureLOR, 603 FeatureVH, 604 ]>; 605 606def ProcAppleA11 : SubtargetFeature<"apple-a11", "ARMProcFamily", "AppleA11", 607 "Apple A11", [ 608 FeatureAlternateSExtLoadCVTF32Pattern, 609 FeatureArithmeticBccFusion, 610 FeatureArithmeticCbzFusion, 611 FeatureCrypto, 612 FeatureDisableLatencySchedHeuristic, 613 FeatureFPARMv8, 614 FeatureFuseAES, 615 FeatureFuseCryptoEOR, 616 FeatureNEON, 617 FeaturePerfMon, 618 FeatureZCRegMove, 619 FeatureZCZeroing, 620 FeatureFullFP16, 621 HasV8_2aOps 622 ]>; 623 624def ProcAppleA12 : SubtargetFeature<"apple-a12", "ARMProcFamily", "AppleA12", 625 "Apple A12", [ 626 FeatureAlternateSExtLoadCVTF32Pattern, 627 FeatureArithmeticBccFusion, 628 FeatureArithmeticCbzFusion, 629 FeatureCrypto, 630 FeatureDisableLatencySchedHeuristic, 631 FeatureFPARMv8, 632 FeatureFuseAES, 633 FeatureFuseCryptoEOR, 634 FeatureNEON, 635 FeaturePerfMon, 636 FeatureZCRegMove, 637 FeatureZCZeroing, 638 FeatureFullFP16, 639 HasV8_3aOps 640 ]>; 641 642def ProcAppleA13 : SubtargetFeature<"apple-a13", "ARMProcFamily", "AppleA13", 643 "Apple A13", [ 644 FeatureAlternateSExtLoadCVTF32Pattern, 645 FeatureArithmeticBccFusion, 646 FeatureArithmeticCbzFusion, 647 FeatureCrypto, 648 FeatureDisableLatencySchedHeuristic, 649 FeatureFPARMv8, 650 FeatureFuseAES, 651 FeatureFuseCryptoEOR, 652 FeatureNEON, 653 FeaturePerfMon, 654 FeatureZCRegMove, 655 FeatureZCZeroing, 656 FeatureFullFP16, 657 FeatureFP16FML, 658 FeatureSHA3, 659 HasV8_4aOps 660 ]>; 661 662def ProcExynosM3 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3", 663 "Samsung Exynos-M3 processors", 664 [FeatureCRC, 665 FeatureCrypto, 666 FeatureExynosCheapAsMoveHandling, 667 FeatureForce32BitJumpTables, 668 FeatureFuseAddress, 669 FeatureFuseAES, 670 FeatureFuseCCSelect, 671 FeatureFuseLiterals, 672 FeatureLSLFast, 673 FeaturePerfMon, 674 FeaturePostRAScheduler, 675 FeaturePredictableSelectIsExpensive, 676 FeatureZCZeroingFP]>; 677 678def ProcExynosM4 : SubtargetFeature<"exynosm4", "ARMProcFamily", "ExynosM3", 679 "Samsung Exynos-M4 processors", 680 [HasV8_2aOps, 681 FeatureArithmeticBccFusion, 682 FeatureArithmeticCbzFusion, 683 FeatureCrypto, 684 FeatureDotProd, 685 FeatureExynosCheapAsMoveHandling, 686 FeatureForce32BitJumpTables, 687 FeatureFullFP16, 688 FeatureFuseAddress, 689 FeatureFuseAES, 690 FeatureFuseArithmeticLogic, 691 FeatureFuseCCSelect, 692 FeatureFuseLiterals, 693 FeatureLSLFast, 694 FeaturePerfMon, 695 FeaturePostRAScheduler, 696 FeatureZCZeroing]>; 697 698def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo", 699 "Qualcomm Kryo processors", [ 700 FeatureCRC, 701 FeatureCrypto, 702 FeatureCustomCheapAsMoveHandling, 703 FeatureFPARMv8, 704 FeatureNEON, 705 FeaturePerfMon, 706 FeaturePostRAScheduler, 707 FeaturePredictableSelectIsExpensive, 708 FeatureZCZeroing, 709 FeatureLSLFast 710 ]>; 711 712def ProcFalkor : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor", 713 "Qualcomm Falkor processors", [ 714 FeatureCRC, 715 FeatureCrypto, 716 FeatureCustomCheapAsMoveHandling, 717 FeatureFPARMv8, 718 FeatureNEON, 719 FeaturePerfMon, 720 FeaturePostRAScheduler, 721 FeaturePredictableSelectIsExpensive, 722 FeatureRDM, 723 FeatureZCZeroing, 724 FeatureLSLFast, 725 FeatureSlowSTRQro 726 ]>; 727 728def ProcNeoverseE1 : SubtargetFeature<"neoversee1", "ARMProcFamily", 729 "NeoverseE1", 730 "Neoverse E1 ARM processors", [ 731 HasV8_2aOps, 732 FeatureCrypto, 733 FeatureDotProd, 734 FeatureFPARMv8, 735 FeatureFullFP16, 736 FeatureNEON, 737 FeatureRCPC, 738 FeatureSSBS, 739 ]>; 740 741def ProcNeoverseN1 : SubtargetFeature<"neoversen1", "ARMProcFamily", 742 "NeoverseN1", 743 "Neoverse N1 ARM processors", [ 744 HasV8_2aOps, 745 FeatureCrypto, 746 FeatureDotProd, 747 FeatureFPARMv8, 748 FeatureFullFP16, 749 FeatureNEON, 750 FeatureRCPC, 751 FeatureSPE, 752 FeatureSSBS, 753 ]>; 754 755def ProcSaphira : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira", 756 "Qualcomm Saphira processors", [ 757 FeatureCrypto, 758 FeatureCustomCheapAsMoveHandling, 759 FeatureFPARMv8, 760 FeatureNEON, 761 FeatureSPE, 762 FeaturePerfMon, 763 FeaturePostRAScheduler, 764 FeaturePredictableSelectIsExpensive, 765 FeatureZCZeroing, 766 FeatureLSLFast, 767 HasV8_4aOps]>; 768 769def ProcThunderX2T99 : SubtargetFeature<"thunderx2t99", "ARMProcFamily", 770 "ThunderX2T99", 771 "Cavium ThunderX2 processors", [ 772 FeatureAggressiveFMA, 773 FeatureCRC, 774 FeatureCrypto, 775 FeatureFPARMv8, 776 FeatureArithmeticBccFusion, 777 FeatureNEON, 778 FeaturePostRAScheduler, 779 FeaturePredictableSelectIsExpensive, 780 FeatureLSE, 781 HasV8_1aOps]>; 782 783def ProcThunderX : SubtargetFeature<"thunderx", "ARMProcFamily", "ThunderX", 784 "Cavium ThunderX processors", [ 785 FeatureCRC, 786 FeatureCrypto, 787 FeatureFPARMv8, 788 FeaturePerfMon, 789 FeaturePostRAScheduler, 790 FeaturePredictableSelectIsExpensive, 791 FeatureNEON]>; 792 793def ProcThunderXT88 : SubtargetFeature<"thunderxt88", "ARMProcFamily", 794 "ThunderXT88", 795 "Cavium ThunderX processors", [ 796 FeatureCRC, 797 FeatureCrypto, 798 FeatureFPARMv8, 799 FeaturePerfMon, 800 FeaturePostRAScheduler, 801 FeaturePredictableSelectIsExpensive, 802 FeatureNEON]>; 803 804def ProcThunderXT81 : SubtargetFeature<"thunderxt81", "ARMProcFamily", 805 "ThunderXT81", 806 "Cavium ThunderX processors", [ 807 FeatureCRC, 808 FeatureCrypto, 809 FeatureFPARMv8, 810 FeaturePerfMon, 811 FeaturePostRAScheduler, 812 FeaturePredictableSelectIsExpensive, 813 FeatureNEON]>; 814 815def ProcThunderXT83 : SubtargetFeature<"thunderxt83", "ARMProcFamily", 816 "ThunderXT83", 817 "Cavium ThunderX processors", [ 818 FeatureCRC, 819 FeatureCrypto, 820 FeatureFPARMv8, 821 FeaturePerfMon, 822 FeaturePostRAScheduler, 823 FeaturePredictableSelectIsExpensive, 824 FeatureNEON]>; 825 826def ProcTSV110 : SubtargetFeature<"tsv110", "ARMProcFamily", "TSV110", 827 "HiSilicon TS-V110 processors", [ 828 HasV8_2aOps, 829 FeatureCrypto, 830 FeatureCustomCheapAsMoveHandling, 831 FeatureFPARMv8, 832 FeatureFuseAES, 833 FeatureNEON, 834 FeaturePerfMon, 835 FeaturePostRAScheduler, 836 FeatureSPE, 837 FeatureFullFP16, 838 FeatureFP16FML, 839 FeatureDotProd]>; 840 841def : ProcessorModel<"generic", NoSchedModel, [ 842 FeatureFPARMv8, 843 FeatureFuseAES, 844 FeatureNEON, 845 FeaturePerfMon, 846 FeaturePostRAScheduler, 847// ETE and TRBE are future architecture extensions. We temporariliy enable them 848// by default for users targeting generic AArch64, until it is decided in which 849// armv8.x-a architecture revision they will end up. The extensions do not 850// affect code generated by the compiler and can be used only by explicitly 851// mentioning the new system register names in assembly. 852 FeatureETE 853 ]>; 854 855def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>; 856def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>; 857def : ProcessorModel<"cortex-a55", CortexA53Model, [ProcA55]>; 858def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>; 859def : ProcessorModel<"cortex-a65", CortexA53Model, [ProcA65]>; 860def : ProcessorModel<"cortex-a65ae", CortexA53Model, [ProcA65]>; 861def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA72]>; 862def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA73]>; 863def : ProcessorModel<"cortex-a75", CortexA57Model, [ProcA75]>; 864def : ProcessorModel<"cortex-a76", CortexA57Model, [ProcA76]>; 865def : ProcessorModel<"cortex-a76ae", CortexA57Model, [ProcA76]>; 866def : ProcessorModel<"neoverse-e1", CortexA53Model, [ProcNeoverseE1]>; 867def : ProcessorModel<"neoverse-n1", CortexA57Model, [ProcNeoverseN1]>; 868def : ProcessorModel<"exynos-m3", ExynosM3Model, [ProcExynosM3]>; 869def : ProcessorModel<"exynos-m4", ExynosM4Model, [ProcExynosM4]>; 870def : ProcessorModel<"exynos-m5", ExynosM5Model, [ProcExynosM4]>; 871def : ProcessorModel<"falkor", FalkorModel, [ProcFalkor]>; 872def : ProcessorModel<"saphira", FalkorModel, [ProcSaphira]>; 873def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>; 874// Cavium ThunderX/ThunderX T8X Processors 875def : ProcessorModel<"thunderx", ThunderXT8XModel, [ProcThunderX]>; 876def : ProcessorModel<"thunderxt88", ThunderXT8XModel, [ProcThunderXT88]>; 877def : ProcessorModel<"thunderxt81", ThunderXT8XModel, [ProcThunderXT81]>; 878def : ProcessorModel<"thunderxt83", ThunderXT8XModel, [ProcThunderXT83]>; 879// Cavium ThunderX2T9X Processors. Formerly Broadcom Vulcan. 880def : ProcessorModel<"thunderx2t99", ThunderX2T99Model, [ProcThunderX2T99]>; 881// FIXME: HiSilicon TSV110 is currently modeled as a Cortex-A57. 882def : ProcessorModel<"tsv110", CortexA57Model, [ProcTSV110]>; 883 884// Support cyclone as an alias for apple-a7 so we can still LTO old bitcode. 885def : ProcessorModel<"cyclone", CycloneModel, [ProcAppleA7]>; 886 887// iPhone and iPad CPUs 888def : ProcessorModel<"apple-a7", CycloneModel, [ProcAppleA7]>; 889def : ProcessorModel<"apple-a8", CycloneModel, [ProcAppleA7]>; 890def : ProcessorModel<"apple-a9", CycloneModel, [ProcAppleA7]>; 891def : ProcessorModel<"apple-a10", CycloneModel, [ProcAppleA10]>; 892def : ProcessorModel<"apple-a11", CycloneModel, [ProcAppleA11]>; 893def : ProcessorModel<"apple-a12", CycloneModel, [ProcAppleA12]>; 894def : ProcessorModel<"apple-a13", CycloneModel, [ProcAppleA13]>; 895 896// watch CPUs. 897def : ProcessorModel<"apple-s4", CycloneModel, [ProcAppleA12]>; 898def : ProcessorModel<"apple-s5", CycloneModel, [ProcAppleA12]>; 899 900// Alias for the latest Apple processor model supported by LLVM. 901def : ProcessorModel<"apple-latest", CycloneModel, [ProcAppleA13]>; 902 903//===----------------------------------------------------------------------===// 904// Assembly parser 905//===----------------------------------------------------------------------===// 906 907def GenericAsmParserVariant : AsmParserVariant { 908 int Variant = 0; 909 string Name = "generic"; 910 string BreakCharacters = "."; 911 string TokenizingCharacters = "[]*!/"; 912} 913 914def AppleAsmParserVariant : AsmParserVariant { 915 int Variant = 1; 916 string Name = "apple-neon"; 917 string BreakCharacters = "."; 918 string TokenizingCharacters = "[]*!/"; 919} 920 921//===----------------------------------------------------------------------===// 922// Assembly printer 923//===----------------------------------------------------------------------===// 924// AArch64 Uses the MC printer for asm output, so make sure the TableGen 925// AsmWriter bits get associated with the correct class. 926def GenericAsmWriter : AsmWriter { 927 string AsmWriterClassName = "InstPrinter"; 928 int PassSubtarget = 1; 929 int Variant = 0; 930 bit isMCAsmWriter = 1; 931} 932 933def AppleAsmWriter : AsmWriter { 934 let AsmWriterClassName = "AppleInstPrinter"; 935 int PassSubtarget = 1; 936 int Variant = 1; 937 int isMCAsmWriter = 1; 938} 939 940//===----------------------------------------------------------------------===// 941// Target Declaration 942//===----------------------------------------------------------------------===// 943 944def AArch64 : Target { 945 let InstructionSet = AArch64InstrInfo; 946 let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant]; 947 let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter]; 948 let AllowRegisterRenaming = 1; 949} 950 951//===----------------------------------------------------------------------===// 952// Pfm Counters 953//===----------------------------------------------------------------------===// 954 955include "AArch64PfmCounters.td" 956