1//=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// 10//===----------------------------------------------------------------------===// 11 12//===----------------------------------------------------------------------===// 13// Target-independent interfaces which we are implementing. 14//===----------------------------------------------------------------------===// 15 16include "llvm/Target/Target.td" 17 18//===----------------------------------------------------------------------===// 19// AArch64 Subtarget features. 20// 21 22// Each SubtargetFeature which corresponds to an Arm Architecture feature should 23// be annotated with the respective FEAT_ feature name from the Architecture 24// Reference Manual. If a SubtargetFeature enables instructions from multiple 25// Arm Architecture Features, it should list all the relevant features. Not all 26// FEAT_ features have a corresponding SubtargetFeature. 27 28def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true", 29 "Enable ARMv8 FP (FEAT_FP)">; 30 31def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", 32 "Enable Advanced SIMD instructions (FEAT_AdvSIMD)", [FeatureFPARMv8]>; 33 34def FeatureSM4 : SubtargetFeature< 35 "sm4", "HasSM4", "true", 36 "Enable SM3 and SM4 support (FEAT_SM4, FEAT_SM3)", [FeatureNEON]>; 37 38def FeatureSHA2 : SubtargetFeature< 39 "sha2", "HasSHA2", "true", 40 "Enable SHA1 and SHA256 support (FEAT_SHA1, FEAT_SHA256)", [FeatureNEON]>; 41 42def FeatureSHA3 : SubtargetFeature< 43 "sha3", "HasSHA3", "true", 44 "Enable SHA512 and SHA3 support (FEAT_SHA3, FEAT_SHA512)", [FeatureNEON, FeatureSHA2]>; 45 46def FeatureAES : SubtargetFeature< 47 "aes", "HasAES", "true", 48 "Enable AES support (FEAT_AES, FEAT_PMULL)", [FeatureNEON]>; 49 50// Crypto has been split up and any combination is now valid (see the 51// crypto definitions above). Also, crypto is now context sensitive: 52// it has a different meaning for e.g. Armv8.4 than it has for Armv8.2. 53// Therefore, we rely on Clang, the user interacing tool, to pass on the 54// appropriate crypto options. But here in the backend, crypto has very little 55// meaning anymore. We kept the Crypto definition here for backward 56// compatibility, and now imply features SHA2 and AES, which was the 57// "traditional" meaning of Crypto. 58def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", 59 "Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>; 60 61def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", 62 "Enable ARMv8 CRC-32 checksum instructions (FEAT_CRC32)">; 63 64def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true", 65 "Enable ARMv8 Reliability, Availability and Serviceability Extensions (FEAT_RAS, FEAT_RASv1p1)">; 66 67def FeatureRASv2 : SubtargetFeature<"rasv2", "HasRASv2", "true", 68 "Enable ARMv8.9-A Reliability, Availability and Serviceability Extensions (FEAT_RASv2)", 69 [FeatureRAS]>; 70 71def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true", 72 "Enable ARMv8.1 Large System Extension (LSE) atomic instructions (FEAT_LSE)">; 73 74def FeatureLSE2 : SubtargetFeature<"lse2", "HasLSE2", "true", 75 "Enable ARMv8.4 Large System Extension 2 (LSE2) atomicity rules (FEAT_LSE2)">; 76 77def FeatureOutlineAtomics : SubtargetFeature<"outline-atomics", "OutlineAtomics", "true", 78 "Enable out of line atomics to support LSE instructions">; 79 80def FeatureFMV : SubtargetFeature<"fmv", "HasFMV", "true", 81 "Enable Function Multi Versioning support.">; 82 83def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true", 84 "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions (FEAT_RDM)">; 85 86def FeaturePAN : SubtargetFeature< 87 "pan", "HasPAN", "true", 88 "Enables ARM v8.1 Privileged Access-Never extension (FEAT_PAN)">; 89 90def FeatureLOR : SubtargetFeature< 91 "lor", "HasLOR", "true", 92 "Enables ARM v8.1 Limited Ordering Regions extension (FEAT_LOR)">; 93 94def FeatureCONTEXTIDREL2 : SubtargetFeature<"CONTEXTIDREL2", "HasCONTEXTIDREL2", 95 "true", "Enable RW operand CONTEXTIDR_EL2" >; 96 97def FeatureVH : SubtargetFeature<"vh", "HasVH", "true", 98 "Enables ARM v8.1 Virtual Host extension (FEAT_VHE)", [FeatureCONTEXTIDREL2] >; 99 100// This SubtargetFeature is special. It controls only whether codegen will turn 101// `llvm.readcyclecounter()` into an access to a PMUv3 System Register. The 102// `FEAT_PMUv3*` system registers are always available for assembly/disassembly. 103def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", 104 "Enable Code Generation for ARMv8 PMUv3 Performance Monitors extension (FEAT_PMUv3)">; 105 106def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true", 107 "Full FP16 (FEAT_FP16)", [FeatureFPARMv8]>; 108 109def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true", 110 "Enable FP16 FML instructions (FEAT_FHM)", [FeatureFullFP16]>; 111 112def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true", 113 "Enable Statistical Profiling extension (FEAT_SPE)">; 114 115def FeaturePAN_RWV : SubtargetFeature< 116 "pan-rwv", "HasPAN_RWV", "true", 117 "Enable v8.2 PAN s1e1R and s1e1W Variants (FEAT_PAN2)", 118 [FeaturePAN]>; 119 120// UAO PState 121def FeaturePsUAO : SubtargetFeature< "uaops", "HasPsUAO", "true", 122 "Enable v8.2 UAO PState (FEAT_UAO)">; 123 124def FeatureCCPP : SubtargetFeature<"ccpp", "HasCCPP", 125 "true", "Enable v8.2 data Cache Clean to Point of Persistence (FEAT_DPB)" >; 126 127def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true", 128 "Enable Scalable Vector Extension (SVE) instructions (FEAT_SVE)", [FeatureFullFP16]>; 129 130// This flag is currently still labeled as Experimental, but when fully 131// implemented this should tell the compiler to use the zeroing pseudos to 132// benefit from the reverse instructions (e.g. SUB vs SUBR) if the inactive 133// lanes are known to be zero. The pseudos will then be expanded using the 134// MOVPRFX instruction to zero the inactive lanes. This feature should only be 135// enabled if MOVPRFX instructions are known to merge with the destructive 136// operations they prefix. 137// 138// This feature could similarly be extended to support cheap merging of _any_ 139// value into the inactive lanes using the MOVPRFX instruction that uses 140// merging-predication. 141def FeatureExperimentalZeroingPseudos 142 : SubtargetFeature<"use-experimental-zeroing-pseudos", 143 "UseExperimentalZeroingPseudos", "true", 144 "Hint to the compiler that the MOVPRFX instruction is " 145 "merged with destructive operations", 146 []>; 147 148def FeatureUseScalarIncVL : SubtargetFeature<"use-scalar-inc-vl", 149 "UseScalarIncVL", "true", "Prefer inc/dec over add+cnt">; 150 151def FeatureSVE2 : SubtargetFeature<"sve2", "HasSVE2", "true", 152 "Enable Scalable Vector Extension 2 (SVE2) instructions (FEAT_SVE2)", 153 [FeatureSVE, FeatureUseScalarIncVL]>; 154 155def FeatureSVE2AES : SubtargetFeature<"sve2-aes", "HasSVE2AES", "true", 156 "Enable AES SVE2 instructions (FEAT_SVE_AES, FEAT_SVE_PMULL128)", 157 [FeatureSVE2, FeatureAES]>; 158 159def FeatureSVE2SM4 : SubtargetFeature<"sve2-sm4", "HasSVE2SM4", "true", 160 "Enable SM4 SVE2 instructions (FEAT_SVE_SM4)", [FeatureSVE2, FeatureSM4]>; 161 162def FeatureSVE2SHA3 : SubtargetFeature<"sve2-sha3", "HasSVE2SHA3", "true", 163 "Enable SHA3 SVE2 instructions (FEAT_SVE_SHA3)", [FeatureSVE2, FeatureSHA3]>; 164 165def FeatureSVE2BitPerm : SubtargetFeature<"sve2-bitperm", "HasSVE2BitPerm", "true", 166 "Enable bit permutation SVE2 instructions (FEAT_SVE_BitPerm)", [FeatureSVE2]>; 167 168def FeatureSVE2p1: SubtargetFeature<"sve2p1", "HasSVE2p1", "true", 169 "Enable Scalable Vector Extension 2.1 instructions", [FeatureSVE2]>; 170 171def FeatureB16B16 : SubtargetFeature<"b16b16", "HasB16B16", "true", 172 "Enable SVE2.1 or SME2.1 non-widening BFloat16 to BFloat16 instructions (FEAT_B16B16)", []>; 173 174def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true", 175 "Has zero-cycle register moves">; 176 177def FeatureZCZeroingGP : SubtargetFeature<"zcz-gp", "HasZeroCycleZeroingGP", "true", 178 "Has zero-cycle zeroing instructions for generic registers">; 179 180// It is generally beneficial to rewrite "fmov s0, wzr" to "movi d0, #0". 181// as movi is more efficient across all cores. Newer cores can eliminate 182// fmovs early and there is no difference with movi, but this not true for 183// all implementations. 184def FeatureNoZCZeroingFP : SubtargetFeature<"no-zcz-fp", "HasZeroCycleZeroingFP", "false", 185 "Has no zero-cycle zeroing instructions for FP registers">; 186 187def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true", 188 "Has zero-cycle zeroing instructions", 189 [FeatureZCZeroingGP]>; 190 191/// ... but the floating-point version doesn't quite work in rare cases on older 192/// CPUs. 193def FeatureZCZeroingFPWorkaround : SubtargetFeature<"zcz-fp-workaround", 194 "HasZeroCycleZeroingFPWorkaround", "true", 195 "The zero-cycle floating-point zeroing instruction has a bug">; 196 197def FeatureStrictAlign : SubtargetFeature<"strict-align", 198 "RequiresStrictAlign", "true", 199 "Disallow all unaligned memory " 200 "access">; 201 202foreach i = {1-7,9-15,18,20-28,30} in 203 def FeatureReserveX#i : SubtargetFeature<"reserve-x"#i, "ReserveXRegister["#i#"]", "true", 204 "Reserve X"#i#", making it unavailable " 205 "as a GPR">; 206 207foreach i = {8-15,18} in 208 def FeatureCallSavedX#i : SubtargetFeature<"call-saved-x"#i, 209 "CustomCallSavedXRegs["#i#"]", "true", "Make X"#i#" callee saved.">; 210 211def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps", 212 "true", 213 "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">; 214 215def FeaturePredictableSelectIsExpensive : SubtargetFeature< 216 "predictable-select-expensive", "PredictableSelectIsExpensive", "true", 217 "Prefer likely predicted branches over selects">; 218 219def FeatureEnableSelectOptimize : SubtargetFeature< 220 "enable-select-opt", "EnableSelectOptimize", "true", 221 "Enable the select optimize pass for select loop heuristics">; 222 223def FeatureCustomCheapAsMoveHandling : SubtargetFeature<"custom-cheap-as-move", 224 "HasCustomCheapAsMoveHandling", "true", 225 "Use custom handling of cheap instructions">; 226 227def FeatureExynosCheapAsMoveHandling : SubtargetFeature<"exynos-cheap-as-move", 228 "HasExynosCheapAsMoveHandling", "true", 229 "Use Exynos specific handling of cheap instructions", 230 [FeatureCustomCheapAsMoveHandling]>; 231 232def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler", 233 "UsePostRAScheduler", "true", "Schedule again after register allocation">; 234 235def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store", 236 "IsMisaligned128StoreSlow", "true", "Misaligned 128 bit stores are slow">; 237 238def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128", 239 "IsPaired128Slow", "true", "Paired 128 bit loads and stores are slow">; 240 241def FeatureAscendStoreAddress : SubtargetFeature<"ascend-store-address", 242 "IsStoreAddressAscend", "true", 243 "Schedule vector stores by ascending address">; 244 245def FeatureSlowSTRQro : SubtargetFeature<"slow-strqro-store", "IsSTRQroSlow", 246 "true", "STR of Q register with register offset is slow">; 247 248def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature< 249 "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern", 250 "true", "Use alternative pattern for sextload convert to f32">; 251 252def FeatureArithmeticBccFusion : SubtargetFeature< 253 "arith-bcc-fusion", "HasArithmeticBccFusion", "true", 254 "CPU fuses arithmetic+bcc operations">; 255 256def FeatureArithmeticCbzFusion : SubtargetFeature< 257 "arith-cbz-fusion", "HasArithmeticCbzFusion", "true", 258 "CPU fuses arithmetic + cbz/cbnz operations">; 259 260def FeatureCmpBccFusion : SubtargetFeature< 261 "cmp-bcc-fusion", "HasCmpBccFusion", "true", 262 "CPU fuses cmp+bcc operations">; 263 264def FeatureFuseAddress : SubtargetFeature< 265 "fuse-address", "HasFuseAddress", "true", 266 "CPU fuses address generation and memory operations">; 267 268def FeatureFuseAES : SubtargetFeature< 269 "fuse-aes", "HasFuseAES", "true", 270 "CPU fuses AES crypto operations">; 271 272def FeatureFuseArithmeticLogic : SubtargetFeature< 273 "fuse-arith-logic", "HasFuseArithmeticLogic", "true", 274 "CPU fuses arithmetic and logic operations">; 275 276def FeatureFuseCCSelect : SubtargetFeature< 277 "fuse-csel", "HasFuseCCSelect", "true", 278 "CPU fuses conditional select operations">; 279 280def FeatureFuseCryptoEOR : SubtargetFeature< 281 "fuse-crypto-eor", "HasFuseCryptoEOR", "true", 282 "CPU fuses AES/PMULL and EOR operations">; 283 284def FeatureFuseAdrpAdd : SubtargetFeature< 285 "fuse-adrp-add", "HasFuseAdrpAdd", "true", 286 "CPU fuses adrp+add operations">; 287 288def FeatureFuseLiterals : SubtargetFeature< 289 "fuse-literals", "HasFuseLiterals", "true", 290 "CPU fuses literal generation operations">; 291 292def FeatureDisableLatencySchedHeuristic : SubtargetFeature< 293 "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true", 294 "Disable latency scheduling heuristic">; 295 296def FeatureForce32BitJumpTables 297 : SubtargetFeature<"force-32bit-jump-tables", "Force32BitJumpTables", "true", 298 "Force jump table entries to be 32-bits wide except at MinSize">; 299 300def FeatureRCPC : SubtargetFeature<"rcpc", "HasRCPC", "true", 301 "Enable support for RCPC extension (FEAT_LRCPC)">; 302 303def FeatureUseRSqrt : SubtargetFeature< 304 "use-reciprocal-square-root", "UseRSqrt", "true", 305 "Use the reciprocal square root approximation">; 306 307def FeatureDotProd : SubtargetFeature< 308 "dotprod", "HasDotProd", "true", 309 "Enable dot product support (FEAT_DotProd)">; 310 311def FeaturePAuth : SubtargetFeature< 312 "pauth", "HasPAuth", "true", 313 "Enable v8.3-A Pointer Authentication extension (FEAT_PAuth)">; 314 315def FeatureJS : SubtargetFeature< 316 "jsconv", "HasJS", "true", 317 "Enable v8.3-A JavaScript FP conversion instructions (FEAT_JSCVT)", 318 [FeatureFPARMv8]>; 319 320def FeatureCCIDX : SubtargetFeature< 321 "ccidx", "HasCCIDX", "true", 322 "Enable v8.3-A Extend of the CCSIDR number of sets (FEAT_CCIDX)">; 323 324def FeatureComplxNum : SubtargetFeature< 325 "complxnum", "HasComplxNum", "true", 326 "Enable v8.3-A Floating-point complex number support (FEAT_FCMA)", 327 [FeatureNEON]>; 328 329def FeatureNV : SubtargetFeature< 330 "nv", "HasNV", "true", 331 "Enable v8.4-A Nested Virtualization Enchancement (FEAT_NV, FEAT_NV2)">; 332 333def FeatureMPAM : SubtargetFeature< 334 "mpam", "HasMPAM", "true", 335 "Enable v8.4-A Memory system Partitioning and Monitoring extension (FEAT_MPAM)">; 336 337def FeatureDIT : SubtargetFeature< 338 "dit", "HasDIT", "true", 339 "Enable v8.4-A Data Independent Timing instructions (FEAT_DIT)">; 340 341def FeatureTRACEV8_4 : SubtargetFeature< 342 "tracev8.4", "HasTRACEV8_4", "true", 343 "Enable v8.4-A Trace extension (FEAT_TRF)">; 344 345def FeatureAM : SubtargetFeature< 346 "am", "HasAM", "true", 347 "Enable v8.4-A Activity Monitors extension (FEAT_AMUv1)">; 348 349def FeatureAMVS : SubtargetFeature< 350 "amvs", "HasAMVS", "true", 351 "Enable v8.6-A Activity Monitors Virtualization support (FEAT_AMUv1p1)", 352 [FeatureAM]>; 353 354def FeatureSEL2 : SubtargetFeature< 355 "sel2", "HasSEL2", "true", 356 "Enable v8.4-A Secure Exception Level 2 extension (FEAT_SEL2)">; 357 358def FeatureTLB_RMI : SubtargetFeature< 359 "tlb-rmi", "HasTLB_RMI", "true", 360 "Enable v8.4-A TLB Range and Maintenance Instructions (FEAT_TLBIOS, FEAT_TLBIRANGE)">; 361 362def FeatureFlagM : SubtargetFeature< 363 "flagm", "HasFlagM", "true", 364 "Enable v8.4-A Flag Manipulation Instructions (FEAT_FlagM)">; 365 366// 8.4 RCPC enchancements: LDAPR & STLR instructions with Immediate Offset 367def FeatureRCPC_IMMO : SubtargetFeature<"rcpc-immo", "HasRCPC_IMMO", "true", 368 "Enable v8.4-A RCPC instructions with Immediate Offsets (FEAT_LRCPC2)", 369 [FeatureRCPC]>; 370 371def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates", 372 "NegativeImmediates", "false", 373 "Convert immediates and instructions " 374 "to their negated or complemented " 375 "equivalent when the immediate does " 376 "not fit in the encoding.">; 377 378def FeatureLSLFast : SubtargetFeature< 379 "lsl-fast", "HasLSLFast", "true", 380 "CPU has a fastpath logical shift of up to 3 places">; 381 382def FeatureAggressiveFMA : 383 SubtargetFeature<"aggressive-fma", 384 "HasAggressiveFMA", 385 "true", 386 "Enable Aggressive FMA for floating-point.">; 387 388def FeatureAltFPCmp : SubtargetFeature<"altnzcv", "HasAlternativeNZCV", "true", 389 "Enable alternative NZCV format for floating point comparisons (FEAT_FlagM2)">; 390 391def FeatureFRInt3264 : SubtargetFeature<"fptoint", "HasFRInt3264", "true", 392 "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to " 393 "an integer (in FP format) forcing it to fit into a 32- or 64-bit int (FEAT_FRINTTS)" >; 394 395def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict", 396 "true", "Enable architectural speculation restriction (FEAT_CSV2_2)">; 397 398def FeatureSB : SubtargetFeature<"sb", "HasSB", 399 "true", "Enable v8.5 Speculation Barrier (FEAT_SB)" >; 400 401def FeatureSSBS : SubtargetFeature<"ssbs", "HasSSBS", 402 "true", "Enable Speculative Store Bypass Safe bit (FEAT_SSBS, FEAT_SSBS2)" >; 403 404def FeaturePredRes : SubtargetFeature<"predres", "HasPredRes", "true", 405 "Enable v8.5a execution and data prediction invalidation instructions (FEAT_SPECRES)" >; 406 407def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP", 408 "true", "Enable v8.5 Cache Clean to Point of Deep Persistence (FEAT_DPB2)" >; 409 410def FeatureBranchTargetId : SubtargetFeature<"bti", "HasBTI", 411 "true", "Enable Branch Target Identification (FEAT_BTI)" >; 412 413def FeatureRandGen : SubtargetFeature<"rand", "HasRandGen", 414 "true", "Enable Random Number generation instructions (FEAT_RNG)" >; 415 416def FeatureMTE : SubtargetFeature<"mte", "HasMTE", 417 "true", "Enable Memory Tagging Extension (FEAT_MTE, FEAT_MTE2)" >; 418 419def FeatureTRBE : SubtargetFeature<"trbe", "HasTRBE", 420 "true", "Enable Trace Buffer Extension (FEAT_TRBE)">; 421 422def FeatureETE : SubtargetFeature<"ete", "HasETE", 423 "true", "Enable Embedded Trace Extension (FEAT_ETE)", 424 [FeatureTRBE]>; 425 426def FeatureTME : SubtargetFeature<"tme", "HasTME", 427 "true", "Enable Transactional Memory Extension (FEAT_TME)" >; 428 429def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals", 430 "AllowTaggedGlobals", 431 "true", "Use an instruction sequence for taking the address of a global " 432 "that allows a memory tag in the upper address bits">; 433 434def FeatureBF16 : SubtargetFeature<"bf16", "HasBF16", 435 "true", "Enable BFloat16 Extension (FEAT_BF16)" >; 436 437def FeatureMatMulInt8 : SubtargetFeature<"i8mm", "HasMatMulInt8", 438 "true", "Enable Matrix Multiply Int8 Extension (FEAT_I8MM)">; 439 440def FeatureMatMulFP32 : SubtargetFeature<"f32mm", "HasMatMulFP32", 441 "true", "Enable Matrix Multiply FP32 Extension (FEAT_F32MM)", [FeatureSVE]>; 442 443def FeatureMatMulFP64 : SubtargetFeature<"f64mm", "HasMatMulFP64", 444 "true", "Enable Matrix Multiply FP64 Extension (FEAT_F64MM)", [FeatureSVE]>; 445 446def FeatureXS : SubtargetFeature<"xs", "HasXS", 447 "true", "Enable Armv8.7-A limited-TLB-maintenance instruction (FEAT_XS)">; 448 449def FeatureWFxT : SubtargetFeature<"wfxt", "HasWFxT", 450 "true", "Enable Armv8.7-A WFET and WFIT instruction (FEAT_WFxT)">; 451 452def FeatureHCX : SubtargetFeature< 453 "hcx", "HasHCX", "true", "Enable Armv8.7-A HCRX_EL2 system register (FEAT_HCX)">; 454 455def FeatureLS64 : SubtargetFeature<"ls64", "HasLS64", 456 "true", "Enable Armv8.7-A LD64B/ST64B Accelerator Extension (FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA)">; 457 458def FeatureHBC : SubtargetFeature<"hbc", "HasHBC", 459 "true", "Enable Armv8.8-A Hinted Conditional Branches Extension (FEAT_HBC)">; 460 461def FeatureMOPS : SubtargetFeature<"mops", "HasMOPS", 462 "true", "Enable Armv8.8-A memcpy and memset acceleration instructions (FEAT_MOPS)">; 463 464def FeatureNMI : SubtargetFeature<"nmi", "HasNMI", 465 "true", "Enable Armv8.8-A Non-maskable Interrupts (FEAT_NMI, FEAT_GICv3_NMI)">; 466 467def FeatureBRBE : SubtargetFeature<"brbe", "HasBRBE", 468 "true", "Enable Branch Record Buffer Extension (FEAT_BRBE)">; 469 470def FeatureSPE_EEF : SubtargetFeature<"spe-eef", "HasSPE_EEF", 471 "true", "Enable extra register in the Statistical Profiling Extension (FEAT_SPEv1p2)">; 472 473def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps", 474 "true", "Enable fine grained virtualization traps extension (FEAT_FGT)">; 475 476def FeatureEnhancedCounterVirtualization : 477 SubtargetFeature<"ecv", "HasEnhancedCounterVirtualization", 478 "true", "Enable enhanced counter virtualization extension (FEAT_ECV)">; 479 480def FeatureRME : SubtargetFeature<"rme", "HasRME", 481 "true", "Enable Realm Management Extension (FEAT_RME)">; 482 483def FeatureSME : SubtargetFeature<"sme", "HasSME", "true", 484 "Enable Scalable Matrix Extension (SME) (FEAT_SME)", [FeatureBF16, FeatureUseScalarIncVL]>; 485 486def FeatureSMEF64F64 : SubtargetFeature<"sme-f64f64", "HasSMEF64F64", "true", 487 "Enable Scalable Matrix Extension (SME) F64F64 instructions (FEAT_SME_F64F64)", [FeatureSME]>; 488 489def FeatureSMEI16I64 : SubtargetFeature<"sme-i16i64", "HasSMEI16I64", "true", 490 "Enable Scalable Matrix Extension (SME) I16I64 instructions (FEAT_SME_I16I64)", [FeatureSME]>; 491 492def FeatureSMEF16F16 : SubtargetFeature<"sme-f16f16", "HasSMEF16F16", "true", 493 "Enable SME2.1 non-widening Float16 instructions (FEAT_SME_F16F16)", []>; 494 495def FeatureSME2 : SubtargetFeature<"sme2", "HasSME2", "true", 496 "Enable Scalable Matrix Extension 2 (SME2) instructions", [FeatureSME]>; 497 498def FeatureSME2p1 : SubtargetFeature<"sme2p1", "HasSME2p1", "true", 499 "Enable Scalable Matrix Extension 2.1 (FEAT_SME2p1) instructions", [FeatureSME2]>; 500 501def FeatureAppleA7SysReg : SubtargetFeature<"apple-a7-sysreg", "HasAppleA7SysReg", "true", 502 "Apple A7 (the CPU formerly known as Cyclone)">; 503 504def FeatureEL2VMSA : SubtargetFeature<"el2vmsa", "HasEL2VMSA", "true", 505 "Enable Exception Level 2 Virtual Memory System Architecture">; 506 507def FeatureEL3 : SubtargetFeature<"el3", "HasEL3", "true", 508 "Enable Exception Level 3">; 509 510def FeatureCSSC : SubtargetFeature<"cssc", "HasCSSC", "true", 511 "Enable Common Short Sequence Compression (CSSC) instructions (FEAT_CSSC)">; 512 513def FeatureFixCortexA53_835769 : SubtargetFeature<"fix-cortex-a53-835769", 514 "FixCortexA53_835769", "true", "Mitigate Cortex-A53 Erratum 835769">; 515 516def FeatureNoBTIAtReturnTwice : SubtargetFeature<"no-bti-at-return-twice", 517 "NoBTIAtReturnTwice", "true", 518 "Don't place a BTI instruction " 519 "after a return-twice">; 520 521def FeatureCLRBHB : SubtargetFeature<"clrbhb", "HasCLRBHB", 522 "true", "Enable Clear BHB instruction (FEAT_CLRBHB)">; 523 524def FeaturePRFM_SLC : SubtargetFeature<"prfm-slc-target", "HasPRFM_SLC", 525 "true", "Enable SLC target for PRFM instruction">; 526 527def FeatureSPECRES2 : SubtargetFeature<"specres2", "HasSPECRES2", 528 "true", "Enable Speculation Restriction Instruction (FEAT_SPECRES2)", 529 [FeaturePredRes]>; 530 531def FeatureMEC : SubtargetFeature<"mec", "HasMEC", 532 "true", "Enable Memory Encryption Contexts Extension", [FeatureRME]>; 533 534def FeatureITE : SubtargetFeature<"ite", "HasITE", 535 "true", "Enable Armv9.4-A Instrumentation Extension FEAT_ITE", [FeatureETE, 536 FeatureTRBE]>; 537 538def FeatureRCPC3 : SubtargetFeature<"rcpc3", "HasRCPC3", 539 "true", "Enable Armv8.9-A RCPC instructions for A64 and Advanced SIMD and floating-point instruction set (FEAT_LRCPC3)", 540 [FeatureRCPC_IMMO]>; 541 542def FeatureTHE : SubtargetFeature<"the", "HasTHE", 543 "true", "Enable Armv8.9-A Translation Hardening Extension (FEAT_THE)">; 544 545def FeatureLSE128 : SubtargetFeature<"lse128", "HasLSE128", 546 "true", "Enable Armv9.4-A 128-bit Atomic Instructions (FEAT_LSE128)", 547 [FeatureLSE]>; 548 549// FEAT_D128, FEAT_LVA3, FEAT_SYSREG128, and FEAT_SYSINSTR128 are mutually implicit. 550// Therefore group them all under a single feature flag, d128: 551def FeatureD128 : SubtargetFeature<"d128", "HasD128", 552 "true", "Enable Armv9.4-A 128-bit Page Table Descriptors, System Registers " 553 "and Instructions (FEAT_D128, FEAT_LVA3, FEAT_SYSREG128, FEAT_SYSINSTR128)", 554 [FeatureLSE128]>; 555 556//===----------------------------------------------------------------------===// 557// Architectures. 558// 559def HasV8_0aOps : SubtargetFeature<"v8a", "HasV8_0aOps", "true", 560 "Support ARM v8.0a instructions", [FeatureEL2VMSA, FeatureEL3]>; 561 562def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", 563 "Support ARM v8.1a instructions", [HasV8_0aOps, FeatureCRC, FeatureLSE, 564 FeatureRDM, FeaturePAN, FeatureLOR, FeatureVH]>; 565 566def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true", 567 "Support ARM v8.2a instructions", [HasV8_1aOps, FeaturePsUAO, 568 FeaturePAN_RWV, FeatureRAS, FeatureCCPP]>; 569 570def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true", 571 "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC, FeaturePAuth, 572 FeatureJS, FeatureCCIDX, FeatureComplxNum]>; 573 574def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", 575 "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd, 576 FeatureNV, FeatureMPAM, FeatureDIT, 577 FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeatureTLB_RMI, 578 FeatureFlagM, FeatureRCPC_IMMO, FeatureLSE2]>; 579 580def HasV8_5aOps : SubtargetFeature< 581 "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions", 582 [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict, 583 FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist, 584 FeatureBranchTargetId]>; 585 586def HasV8_6aOps : SubtargetFeature< 587 "v8.6a", "HasV8_6aOps", "true", "Support ARM v8.6a instructions", 588 [HasV8_5aOps, FeatureAMVS, FeatureBF16, FeatureFineGrainedTraps, 589 FeatureEnhancedCounterVirtualization, FeatureMatMulInt8]>; 590 591def HasV8_7aOps : SubtargetFeature< 592 "v8.7a", "HasV8_7aOps", "true", "Support ARM v8.7a instructions", 593 [HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX]>; 594 595def HasV8_8aOps : SubtargetFeature< 596 "v8.8a", "HasV8_8aOps", "true", "Support ARM v8.8a instructions", 597 [HasV8_7aOps, FeatureHBC, FeatureMOPS, FeatureNMI]>; 598 599def HasV8_9aOps : SubtargetFeature< 600 "v8.9a", "HasV8_9aOps", "true", "Support ARM v8.9a instructions", 601 [HasV8_8aOps, FeatureCLRBHB, FeaturePRFM_SLC, FeatureSPECRES2, 602 FeatureCSSC, FeatureRASv2]>; 603 604def HasV9_0aOps : SubtargetFeature< 605 "v9a", "HasV9_0aOps", "true", "Support ARM v9a instructions", 606 [HasV8_5aOps, FeatureMEC, FeatureSVE2]>; 607 608def HasV9_1aOps : SubtargetFeature< 609 "v9.1a", "HasV9_1aOps", "true", "Support ARM v9.1a instructions", 610 [HasV8_6aOps, HasV9_0aOps]>; 611 612def HasV9_2aOps : SubtargetFeature< 613 "v9.2a", "HasV9_2aOps", "true", "Support ARM v9.2a instructions", 614 [HasV8_7aOps, HasV9_1aOps]>; 615 616def HasV9_3aOps : SubtargetFeature< 617 "v9.3a", "HasV9_3aOps", "true", "Support ARM v9.3a instructions", 618 [HasV8_8aOps, HasV9_2aOps]>; 619 620def HasV9_4aOps : SubtargetFeature< 621 "v9.4a", "HasV9_4aOps", "true", "Support ARM v9.4a instructions", 622 [HasV8_9aOps, HasV9_3aOps]>; 623 624def HasV8_0rOps : SubtargetFeature< 625 "v8r", "HasV8_0rOps", "true", "Support ARM v8r instructions", 626 [//v8.1 627 FeatureCRC, FeaturePAN, FeatureRDM, FeatureLSE, FeatureCONTEXTIDREL2, 628 //v8.2 629 FeatureRAS, FeaturePsUAO, FeatureCCPP, FeaturePAN_RWV, 630 //v8.3 631 FeatureComplxNum, FeatureCCIDX, FeatureJS, 632 FeaturePAuth, FeatureRCPC, 633 //v8.4 634 FeatureDotProd, FeatureTRACEV8_4, FeatureTLB_RMI, 635 FeatureFlagM, FeatureDIT, FeatureSEL2, FeatureRCPC_IMMO, 636 // Not mandatory in v8.0-R, but included here on the grounds that it 637 // only enables names of system registers 638 FeatureSpecRestrict 639 ]>; 640 641// Only intended to be used by disassemblers. 642def FeatureAll 643 : SubtargetFeature<"all", "IsAll", "true", "Enable all instructions", []>; 644 645class AssemblerPredicateWithAll<dag cond, string name=""> 646 : AssemblerPredicate<(any_of FeatureAll, cond), name>; 647 648//===----------------------------------------------------------------------===// 649// Register File Description 650//===----------------------------------------------------------------------===// 651 652include "AArch64RegisterInfo.td" 653include "AArch64RegisterBanks.td" 654include "AArch64CallingConvention.td" 655 656//===----------------------------------------------------------------------===// 657// Instruction Descriptions 658//===----------------------------------------------------------------------===// 659 660include "AArch64Schedule.td" 661include "AArch64InstrInfo.td" 662include "AArch64SchedPredicates.td" 663include "AArch64SchedPredExynos.td" 664include "AArch64SchedPredAmpere.td" 665include "AArch64Combine.td" 666 667def AArch64InstrInfo : InstrInfo; 668 669//===----------------------------------------------------------------------===// 670// Named operands for MRS/MSR/TLBI/... 671//===----------------------------------------------------------------------===// 672 673include "AArch64SystemOperands.td" 674 675//===----------------------------------------------------------------------===// 676// Access to privileged registers 677//===----------------------------------------------------------------------===// 678 679foreach i = 1-3 in 680def FeatureUseEL#i#ForTP : SubtargetFeature<"tpidr-el"#i, "UseEL"#i#"ForTP", 681 "true", "Permit use of TPIDR_EL"#i#" for the TLS base">; 682 683//===----------------------------------------------------------------------===// 684// Control codegen mitigation against Straight Line Speculation vulnerability. 685//===----------------------------------------------------------------------===// 686 687def FeatureHardenSlsRetBr : SubtargetFeature<"harden-sls-retbr", 688 "HardenSlsRetBr", "true", 689 "Harden against straight line speculation across RET and BR instructions">; 690def FeatureHardenSlsBlr : SubtargetFeature<"harden-sls-blr", 691 "HardenSlsBlr", "true", 692 "Harden against straight line speculation across BLR instructions">; 693def FeatureHardenSlsNoComdat : SubtargetFeature<"harden-sls-nocomdat", 694 "HardenSlsNoComdat", "true", 695 "Generate thunk code for SLS mitigation in the normal text section">; 696 697//===----------------------------------------------------------------------===// 698// AArch64 Processors supported. 699// 700 701//===----------------------------------------------------------------------===// 702// Unsupported features to disable for scheduling models 703//===----------------------------------------------------------------------===// 704 705class AArch64Unsupported { list<Predicate> F; } 706 707def SVEUnsupported : AArch64Unsupported { 708 let F = [HasSVE, HasSVE2, HasSVE2AES, HasSVE2SM4, HasSVE2SHA3, 709 HasSVE2BitPerm, HasSVEorSME, HasSVE2p1, HasSVE2orSME, HasSVE2p1_or_HasSME2p1]; 710} 711 712def PAUnsupported : AArch64Unsupported { 713 let F = [HasPAuth]; 714} 715 716def SMEUnsupported : AArch64Unsupported { 717 let F = [HasSME, HasSMEF64F64, HasSMEI16I64, HasSME2, HasSVE2p1_or_HasSME2, 718 HasSVE2p1_or_HasSME2p1, HasSME2p1, HasSMEF16F16]; 719} 720 721include "AArch64SchedA53.td" 722include "AArch64SchedA55.td" 723include "AArch64SchedA57.td" 724include "AArch64SchedCyclone.td" 725include "AArch64SchedFalkor.td" 726include "AArch64SchedKryo.td" 727include "AArch64SchedExynosM3.td" 728include "AArch64SchedExynosM4.td" 729include "AArch64SchedExynosM5.td" 730include "AArch64SchedThunderX.td" 731include "AArch64SchedThunderX2T99.td" 732include "AArch64SchedA64FX.td" 733include "AArch64SchedThunderX3T110.td" 734include "AArch64SchedTSV110.td" 735include "AArch64SchedAmpere1.td" 736include "AArch64SchedNeoverseN2.td" 737 738def TuneA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35", 739 "Cortex-A35 ARM processors">; 740 741def TuneA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", 742 "Cortex-A53 ARM processors", [ 743 FeatureFuseAES, 744 FeatureFuseAdrpAdd, 745 FeatureBalanceFPOps, 746 FeatureCustomCheapAsMoveHandling, 747 FeaturePostRAScheduler]>; 748 749def TuneA55 : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55", 750 "Cortex-A55 ARM processors", [ 751 FeatureFuseAES, 752 FeatureFuseAdrpAdd, 753 FeaturePostRAScheduler, 754 FeatureFuseAddress]>; 755 756def TuneA510 : SubtargetFeature<"a510", "ARMProcFamily", "CortexA510", 757 "Cortex-A510 ARM processors", [ 758 FeatureFuseAES, 759 FeatureFuseAdrpAdd, 760 FeaturePostRAScheduler 761 ]>; 762 763def TuneA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", 764 "Cortex-A57 ARM processors", [ 765 FeatureFuseAES, 766 FeatureBalanceFPOps, 767 FeatureCustomCheapAsMoveHandling, 768 FeatureFuseAdrpAdd, 769 FeatureFuseLiterals, 770 FeaturePostRAScheduler, 771 FeatureEnableSelectOptimize, 772 FeaturePredictableSelectIsExpensive]>; 773 774def TuneA65 : SubtargetFeature<"a65", "ARMProcFamily", "CortexA65", 775 "Cortex-A65 ARM processors", [ 776 FeatureFuseAES, 777 FeatureFuseAddress, 778 FeatureFuseAdrpAdd, 779 FeatureFuseLiterals, 780 FeatureEnableSelectOptimize]>; 781 782def TuneA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72", 783 "Cortex-A72 ARM processors", [ 784 FeatureFuseAES, 785 FeatureFuseAdrpAdd, 786 FeatureFuseLiterals, 787 FeatureEnableSelectOptimize]>; 788 789def TuneA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73", 790 "Cortex-A73 ARM processors", [ 791 FeatureFuseAES, 792 FeatureFuseAdrpAdd, 793 FeatureEnableSelectOptimize]>; 794 795def TuneA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75", 796 "Cortex-A75 ARM processors", [ 797 FeatureFuseAES, 798 FeatureFuseAdrpAdd, 799 FeatureEnableSelectOptimize]>; 800 801def TuneA76 : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76", 802 "Cortex-A76 ARM processors", [ 803 FeatureFuseAES, 804 FeatureFuseAdrpAdd, 805 FeatureLSLFast, 806 FeatureEnableSelectOptimize]>; 807 808def TuneA77 : SubtargetFeature<"a77", "ARMProcFamily", "CortexA77", 809 "Cortex-A77 ARM processors", [ 810 FeatureCmpBccFusion, 811 FeatureFuseAES, 812 FeatureFuseAdrpAdd, 813 FeatureLSLFast, 814 FeatureEnableSelectOptimize]>; 815 816def TuneA78 : SubtargetFeature<"a78", "ARMProcFamily", "CortexA78", 817 "Cortex-A78 ARM processors", [ 818 FeatureCmpBccFusion, 819 FeatureFuseAES, 820 FeatureFuseAdrpAdd, 821 FeatureLSLFast, 822 FeaturePostRAScheduler, 823 FeatureEnableSelectOptimize]>; 824 825def TuneA78C : SubtargetFeature<"a78c", "ARMProcFamily", 826 "CortexA78C", 827 "Cortex-A78C ARM processors", [ 828 FeatureCmpBccFusion, 829 FeatureFuseAES, 830 FeatureFuseAdrpAdd, 831 FeatureLSLFast, 832 FeaturePostRAScheduler, 833 FeatureEnableSelectOptimize]>; 834 835def TuneA710 : SubtargetFeature<"a710", "ARMProcFamily", "CortexA710", 836 "Cortex-A710 ARM processors", [ 837 FeatureCmpBccFusion, 838 FeatureFuseAES, 839 FeatureFuseAdrpAdd, 840 FeatureLSLFast, 841 FeaturePostRAScheduler, 842 FeatureEnableSelectOptimize]>; 843 844def TuneA715 : SubtargetFeature<"a715", "ARMProcFamily", "CortexA715", 845 "Cortex-A715 ARM processors", [ 846 FeatureFuseAES, 847 FeaturePostRAScheduler, 848 FeatureCmpBccFusion, 849 FeatureLSLFast, 850 FeatureFuseAdrpAdd, 851 FeatureEnableSelectOptimize]>; 852 853def TuneR82 : SubtargetFeature<"cortex-r82", "ARMProcFamily", 854 "CortexR82", 855 "Cortex-R82 ARM processors", [ 856 FeaturePostRAScheduler]>; 857 858def TuneX1 : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1", 859 "Cortex-X1 ARM processors", [ 860 FeatureCmpBccFusion, 861 FeatureFuseAES, 862 FeatureFuseAdrpAdd, 863 FeatureLSLFast, 864 FeaturePostRAScheduler, 865 FeatureEnableSelectOptimize]>; 866 867def TuneX2 : SubtargetFeature<"cortex-x2", "ARMProcFamily", "CortexX2", 868 "Cortex-X2 ARM processors", [ 869 FeatureCmpBccFusion, 870 FeatureFuseAES, 871 FeatureFuseAdrpAdd, 872 FeatureLSLFast, 873 FeaturePostRAScheduler, 874 FeatureEnableSelectOptimize]>; 875 876def TuneX3 : SubtargetFeature<"cortex-x3", "ARMProcFamily", "CortexX3", 877 "Cortex-X3 ARM processors", [ 878 FeatureLSLFast, 879 FeatureFuseAdrpAdd, 880 FeatureFuseAES, 881 FeaturePostRAScheduler, 882 FeatureEnableSelectOptimize]>; 883 884def TuneA64FX : SubtargetFeature<"a64fx", "ARMProcFamily", "A64FX", 885 "Fujitsu A64FX processors", [ 886 FeaturePostRAScheduler, 887 FeatureAggressiveFMA, 888 FeatureArithmeticBccFusion, 889 FeaturePredictableSelectIsExpensive 890 ]>; 891 892def TuneCarmel : SubtargetFeature<"carmel", "ARMProcFamily", "Carmel", 893 "Nvidia Carmel processors">; 894 895// Note that cyclone does not fuse AES instructions, but newer apple chips do 896// perform the fusion and cyclone is used by default when targetting apple OSes. 897def TuneAppleA7 : SubtargetFeature<"apple-a7", "ARMProcFamily", "AppleA7", 898 "Apple A7 (the CPU formerly known as Cyclone)", [ 899 FeatureAlternateSExtLoadCVTF32Pattern, 900 FeatureArithmeticBccFusion, 901 FeatureArithmeticCbzFusion, 902 FeatureDisableLatencySchedHeuristic, 903 FeatureFuseAES, FeatureFuseCryptoEOR, 904 FeatureZCRegMove, 905 FeatureZCZeroing, 906 FeatureZCZeroingFPWorkaround] 907 >; 908 909def TuneAppleA10 : SubtargetFeature<"apple-a10", "ARMProcFamily", "AppleA10", 910 "Apple A10", [ 911 FeatureAlternateSExtLoadCVTF32Pattern, 912 FeatureArithmeticBccFusion, 913 FeatureArithmeticCbzFusion, 914 FeatureDisableLatencySchedHeuristic, 915 FeatureFuseAES, 916 FeatureFuseCryptoEOR, 917 FeatureZCRegMove, 918 FeatureZCZeroing] 919 >; 920 921def TuneAppleA11 : SubtargetFeature<"apple-a11", "ARMProcFamily", "AppleA11", 922 "Apple A11", [ 923 FeatureAlternateSExtLoadCVTF32Pattern, 924 FeatureArithmeticBccFusion, 925 FeatureArithmeticCbzFusion, 926 FeatureDisableLatencySchedHeuristic, 927 FeatureFuseAES, 928 FeatureFuseCryptoEOR, 929 FeatureZCRegMove, 930 FeatureZCZeroing] 931 >; 932 933def TuneAppleA12 : SubtargetFeature<"apple-a12", "ARMProcFamily", "AppleA12", 934 "Apple A12", [ 935 FeatureAlternateSExtLoadCVTF32Pattern, 936 FeatureArithmeticBccFusion, 937 FeatureArithmeticCbzFusion, 938 FeatureDisableLatencySchedHeuristic, 939 FeatureFuseAES, 940 FeatureFuseCryptoEOR, 941 FeatureZCRegMove, 942 FeatureZCZeroing] 943 >; 944 945def TuneAppleA13 : SubtargetFeature<"apple-a13", "ARMProcFamily", "AppleA13", 946 "Apple A13", [ 947 FeatureAlternateSExtLoadCVTF32Pattern, 948 FeatureArithmeticBccFusion, 949 FeatureArithmeticCbzFusion, 950 FeatureDisableLatencySchedHeuristic, 951 FeatureFuseAES, 952 FeatureFuseCryptoEOR, 953 FeatureZCRegMove, 954 FeatureZCZeroing] 955 >; 956 957def TuneAppleA14 : SubtargetFeature<"apple-a14", "ARMProcFamily", "AppleA14", 958 "Apple A14", [ 959 FeatureAggressiveFMA, 960 FeatureAlternateSExtLoadCVTF32Pattern, 961 FeatureArithmeticBccFusion, 962 FeatureArithmeticCbzFusion, 963 FeatureDisableLatencySchedHeuristic, 964 FeatureFuseAddress, 965 FeatureFuseAES, 966 FeatureFuseArithmeticLogic, 967 FeatureFuseCCSelect, 968 FeatureFuseCryptoEOR, 969 FeatureFuseAdrpAdd, 970 FeatureFuseLiterals, 971 FeatureZCRegMove, 972 FeatureZCZeroing]>; 973 974def TuneAppleA15 : SubtargetFeature<"apple-a15", "ARMProcFamily", "AppleA15", 975 "Apple A15", [ 976 FeatureAlternateSExtLoadCVTF32Pattern, 977 FeatureArithmeticBccFusion, 978 FeatureArithmeticCbzFusion, 979 FeatureDisableLatencySchedHeuristic, 980 FeatureFuseAddress, 981 FeatureFuseAES, 982 FeatureFuseArithmeticLogic, 983 FeatureFuseCCSelect, 984 FeatureFuseCryptoEOR, 985 FeatureFuseLiterals, 986 FeatureZCRegMove, 987 FeatureZCZeroing 988 ]>; 989 990def TuneAppleA16 : SubtargetFeature<"apple-a16", "ARMProcFamily", "AppleA16", 991 "Apple A16", [ 992 FeatureAlternateSExtLoadCVTF32Pattern, 993 FeatureArithmeticBccFusion, 994 FeatureArithmeticCbzFusion, 995 FeatureDisableLatencySchedHeuristic, 996 FeatureFuseAddress, 997 FeatureFuseAES, 998 FeatureFuseArithmeticLogic, 999 FeatureFuseCCSelect, 1000 FeatureFuseCryptoEOR, 1001 FeatureFuseLiterals, 1002 FeatureZCRegMove, 1003 FeatureZCZeroing 1004 ]>; 1005 1006def TuneExynosM3 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3", 1007 "Samsung Exynos-M3 processors", 1008 [FeatureExynosCheapAsMoveHandling, 1009 FeatureForce32BitJumpTables, 1010 FeatureFuseAddress, 1011 FeatureFuseAES, 1012 FeatureFuseCCSelect, 1013 FeatureFuseAdrpAdd, 1014 FeatureFuseLiterals, 1015 FeatureLSLFast, 1016 FeaturePostRAScheduler, 1017 FeaturePredictableSelectIsExpensive]>; 1018 1019// Re-uses some scheduling and tunings from the ExynosM3 proc family. 1020def TuneExynosM4 : SubtargetFeature<"exynosm4", "ARMProcFamily", "ExynosM3", 1021 "Samsung Exynos-M4 processors", 1022 [FeatureArithmeticBccFusion, 1023 FeatureArithmeticCbzFusion, 1024 FeatureExynosCheapAsMoveHandling, 1025 FeatureForce32BitJumpTables, 1026 FeatureFuseAddress, 1027 FeatureFuseAES, 1028 FeatureFuseArithmeticLogic, 1029 FeatureFuseCCSelect, 1030 FeatureFuseAdrpAdd, 1031 FeatureFuseLiterals, 1032 FeatureLSLFast, 1033 FeaturePostRAScheduler, 1034 FeatureZCZeroing]>; 1035 1036def TuneKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo", 1037 "Qualcomm Kryo processors", [ 1038 FeatureCustomCheapAsMoveHandling, 1039 FeaturePostRAScheduler, 1040 FeaturePredictableSelectIsExpensive, 1041 FeatureZCZeroing, 1042 FeatureLSLFast] 1043 >; 1044 1045def TuneFalkor : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor", 1046 "Qualcomm Falkor processors", [ 1047 FeatureCustomCheapAsMoveHandling, 1048 FeaturePostRAScheduler, 1049 FeaturePredictableSelectIsExpensive, 1050 FeatureZCZeroing, 1051 FeatureLSLFast, 1052 FeatureSlowSTRQro 1053 ]>; 1054 1055def TuneNeoverseE1 : SubtargetFeature<"neoversee1", "ARMProcFamily", "NeoverseE1", 1056 "Neoverse E1 ARM processors", [ 1057 FeatureFuseAES, 1058 FeatureFuseAdrpAdd, 1059 FeaturePostRAScheduler]>; 1060 1061def TuneNeoverseN1 : SubtargetFeature<"neoversen1", "ARMProcFamily", "NeoverseN1", 1062 "Neoverse N1 ARM processors", [ 1063 FeatureFuseAES, 1064 FeatureFuseAdrpAdd, 1065 FeatureLSLFast, 1066 FeaturePostRAScheduler, 1067 FeatureEnableSelectOptimize]>; 1068 1069def TuneNeoverseN2 : SubtargetFeature<"neoversen2", "ARMProcFamily", "NeoverseN2", 1070 "Neoverse N2 ARM processors", [ 1071 FeatureFuseAES, 1072 FeatureFuseAdrpAdd, 1073 FeatureLSLFast, 1074 FeaturePostRAScheduler, 1075 FeatureEnableSelectOptimize]>; 1076 1077def TuneNeoverse512TVB : SubtargetFeature<"neoverse512tvb", "ARMProcFamily", "Neoverse512TVB", 1078 "Neoverse 512-TVB ARM processors", [ 1079 FeatureFuseAES, 1080 FeatureFuseAdrpAdd, 1081 FeatureLSLFast, 1082 FeaturePostRAScheduler, 1083 FeatureEnableSelectOptimize]>; 1084 1085def TuneNeoverseV1 : SubtargetFeature<"neoversev1", "ARMProcFamily", "NeoverseV1", 1086 "Neoverse V1 ARM processors", [ 1087 FeatureFuseAES, 1088 FeatureFuseAdrpAdd, 1089 FeatureLSLFast, 1090 FeaturePostRAScheduler, 1091 FeatureEnableSelectOptimize]>; 1092 1093def TuneNeoverseV2 : SubtargetFeature<"neoversev2", "ARMProcFamily", "NeoverseV2", 1094 "Neoverse V2 ARM processors", [ 1095 FeatureFuseAES, 1096 FeatureLSLFast, 1097 FeaturePostRAScheduler, 1098 FeatureEnableSelectOptimize]>; 1099 1100def TuneSaphira : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira", 1101 "Qualcomm Saphira processors", [ 1102 FeatureCustomCheapAsMoveHandling, 1103 FeaturePostRAScheduler, 1104 FeaturePredictableSelectIsExpensive, 1105 FeatureZCZeroing, 1106 FeatureLSLFast]>; 1107 1108def TuneThunderX2T99 : SubtargetFeature<"thunderx2t99", "ARMProcFamily", "ThunderX2T99", 1109 "Cavium ThunderX2 processors", [ 1110 FeatureAggressiveFMA, 1111 FeatureArithmeticBccFusion, 1112 FeaturePostRAScheduler, 1113 FeaturePredictableSelectIsExpensive]>; 1114 1115def TuneThunderX3T110 : SubtargetFeature<"thunderx3t110", "ARMProcFamily", 1116 "ThunderX3T110", 1117 "Marvell ThunderX3 processors", [ 1118 FeatureAggressiveFMA, 1119 FeatureArithmeticBccFusion, 1120 FeaturePostRAScheduler, 1121 FeaturePredictableSelectIsExpensive, 1122 FeatureBalanceFPOps, 1123 FeatureStrictAlign]>; 1124 1125def TuneThunderX : SubtargetFeature<"thunderx", "ARMProcFamily", "ThunderX", 1126 "Cavium ThunderX processors", [ 1127 FeaturePostRAScheduler, 1128 FeaturePredictableSelectIsExpensive]>; 1129 1130def TuneThunderXT88 : SubtargetFeature<"thunderxt88", "ARMProcFamily", 1131 "ThunderXT88", 1132 "Cavium ThunderX processors", [ 1133 FeaturePostRAScheduler, 1134 FeaturePredictableSelectIsExpensive]>; 1135 1136def TuneThunderXT81 : SubtargetFeature<"thunderxt81", "ARMProcFamily", 1137 "ThunderXT81", 1138 "Cavium ThunderX processors", [ 1139 FeaturePostRAScheduler, 1140 FeaturePredictableSelectIsExpensive]>; 1141 1142def TuneThunderXT83 : SubtargetFeature<"thunderxt83", "ARMProcFamily", 1143 "ThunderXT83", 1144 "Cavium ThunderX processors", [ 1145 FeaturePostRAScheduler, 1146 FeaturePredictableSelectIsExpensive]>; 1147 1148def TuneTSV110 : SubtargetFeature<"tsv110", "ARMProcFamily", "TSV110", 1149 "HiSilicon TS-V110 processors", [ 1150 FeatureCustomCheapAsMoveHandling, 1151 FeatureFuseAES, 1152 FeaturePostRAScheduler]>; 1153 1154def TuneAmpere1 : SubtargetFeature<"ampere1", "ARMProcFamily", "Ampere1", 1155 "Ampere Computing Ampere-1 processors", [ 1156 FeaturePostRAScheduler, 1157 FeatureFuseAES, 1158 FeatureLSLFast, 1159 FeatureAggressiveFMA, 1160 FeatureArithmeticBccFusion, 1161 FeatureCmpBccFusion, 1162 FeatureFuseAddress, 1163 FeatureFuseLiterals]>; 1164 1165def TuneAmpere1A : SubtargetFeature<"ampere1a", "ARMProcFamily", "Ampere1A", 1166 "Ampere Computing Ampere-1A processors", [ 1167 FeaturePostRAScheduler, 1168 FeatureFuseAES, 1169 FeatureLSLFast, 1170 FeatureAggressiveFMA, 1171 FeatureArithmeticBccFusion, 1172 FeatureCmpBccFusion, 1173 FeatureFuseAddress, 1174 FeatureFuseLiterals, 1175 FeatureFuseLiterals]>; 1176 1177def ProcessorFeatures { 1178 list<SubtargetFeature> A53 = [HasV8_0aOps, FeatureCRC, FeatureCrypto, 1179 FeatureFPARMv8, FeatureNEON, FeaturePerfMon]; 1180 list<SubtargetFeature> A55 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1181 FeatureNEON, FeatureFullFP16, FeatureDotProd, 1182 FeatureRCPC, FeaturePerfMon]; 1183 list<SubtargetFeature> A510 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon, 1184 FeatureMatMulInt8, FeatureBF16, FeatureAM, 1185 FeatureMTE, FeatureETE, FeatureSVE2BitPerm, 1186 FeatureFP16FML]; 1187 list<SubtargetFeature> A65 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1188 FeatureNEON, FeatureFullFP16, FeatureDotProd, 1189 FeatureRCPC, FeatureSSBS, FeatureRAS, 1190 FeaturePerfMon]; 1191 list<SubtargetFeature> A76 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1192 FeatureNEON, FeatureFullFP16, FeatureDotProd, 1193 FeatureRCPC, FeatureSSBS, FeaturePerfMon]; 1194 list<SubtargetFeature> A77 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1195 FeatureNEON, FeatureFullFP16, FeatureDotProd, 1196 FeatureRCPC, FeaturePerfMon, FeatureSSBS]; 1197 list<SubtargetFeature> A78 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1198 FeatureNEON, FeatureFullFP16, FeatureDotProd, 1199 FeatureRCPC, FeaturePerfMon, FeatureSPE, 1200 FeatureSSBS]; 1201 list<SubtargetFeature> A78C = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1202 FeatureNEON, FeatureFullFP16, FeatureDotProd, 1203 FeatureFlagM, FeatureFP16FML, FeaturePAuth, 1204 FeaturePerfMon, FeatureRCPC, FeatureSPE, 1205 FeatureSSBS]; 1206 list<SubtargetFeature> A710 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon, 1207 FeatureETE, FeatureMTE, FeatureFP16FML, 1208 FeatureSVE2BitPerm, FeatureBF16, FeatureMatMulInt8]; 1209 list<SubtargetFeature> A715 = [HasV9_0aOps, FeatureNEON, FeatureMTE, 1210 FeatureFP16FML, FeatureSVE, FeatureTRBE, 1211 FeatureSVE2BitPerm, FeatureBF16, FeatureETE, 1212 FeaturePerfMon, FeatureMatMulInt8, FeatureSPE]; 1213 list<SubtargetFeature> R82 = [HasV8_0rOps, FeaturePerfMon, FeatureFullFP16, 1214 FeatureFP16FML, FeatureSSBS, FeaturePredRes, 1215 FeatureSB]; 1216 list<SubtargetFeature> X1 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1217 FeatureNEON, FeatureRCPC, FeaturePerfMon, 1218 FeatureSPE, FeatureFullFP16, FeatureDotProd, 1219 FeatureSSBS]; 1220 list<SubtargetFeature> X1C = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1221 FeatureNEON, FeatureRCPC_IMMO, FeaturePerfMon, 1222 FeatureSPE, FeatureFullFP16, FeatureDotProd, 1223 FeaturePAuth, FeatureSSBS, FeatureFlagM, 1224 FeatureLSE2]; 1225 list<SubtargetFeature> X2 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon, 1226 FeatureMatMulInt8, FeatureBF16, FeatureAM, 1227 FeatureMTE, FeatureETE, FeatureSVE2BitPerm, 1228 FeatureFP16FML]; 1229 list<SubtargetFeature> X3 = [HasV9_0aOps, FeatureSVE, FeatureNEON, 1230 FeaturePerfMon, FeatureETE, FeatureTRBE, 1231 FeatureSPE, FeatureBF16, FeatureMatMulInt8, 1232 FeatureMTE, FeatureSVE2BitPerm, FeatureFullFP16, 1233 FeatureFP16FML]; 1234 list<SubtargetFeature> A64FX = [HasV8_2aOps, FeatureFPARMv8, FeatureNEON, 1235 FeatureSHA2, FeaturePerfMon, FeatureFullFP16, 1236 FeatureSVE, FeatureComplxNum]; 1237 list<SubtargetFeature> Carmel = [HasV8_2aOps, FeatureNEON, FeatureCrypto, 1238 FeatureFullFP16]; 1239 list<SubtargetFeature> AppleA7 = [HasV8_0aOps, FeatureCrypto, FeatureFPARMv8, 1240 FeatureNEON,FeaturePerfMon, FeatureAppleA7SysReg]; 1241 list<SubtargetFeature> AppleA10 = [HasV8_0aOps, FeatureCrypto, FeatureFPARMv8, 1242 FeatureNEON, FeaturePerfMon, FeatureCRC, 1243 FeatureRDM, FeaturePAN, FeatureLOR, FeatureVH]; 1244 list<SubtargetFeature> AppleA11 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1245 FeatureNEON, FeaturePerfMon, FeatureFullFP16]; 1246 list<SubtargetFeature> AppleA12 = [HasV8_3aOps, FeatureCrypto, FeatureFPARMv8, 1247 FeatureNEON, FeaturePerfMon, FeatureFullFP16]; 1248 list<SubtargetFeature> AppleA13 = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8, 1249 FeatureNEON, FeaturePerfMon, FeatureFullFP16, 1250 FeatureFP16FML, FeatureSHA3]; 1251 list<SubtargetFeature> AppleA14 = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8, 1252 FeatureNEON, FeaturePerfMon, FeatureFRInt3264, 1253 FeatureSpecRestrict, FeatureSSBS, FeatureSB, 1254 FeaturePredRes, FeatureCacheDeepPersist, 1255 FeatureFullFP16, FeatureFP16FML, FeatureSHA3, 1256 FeatureAltFPCmp]; 1257 list<SubtargetFeature> AppleA15 = [HasV8_6aOps, FeatureCrypto, FeatureFPARMv8, 1258 FeatureNEON, FeaturePerfMon, FeatureSHA3, 1259 FeatureFullFP16, FeatureFP16FML]; 1260 list<SubtargetFeature> AppleA16 = [HasV8_6aOps, FeatureCrypto, FeatureFPARMv8, 1261 FeatureNEON, FeaturePerfMon, FeatureSHA3, 1262 FeatureFullFP16, FeatureFP16FML, 1263 FeatureHCX]; 1264 list<SubtargetFeature> ExynosM3 = [HasV8_0aOps, FeatureCRC, FeatureCrypto, 1265 FeaturePerfMon]; 1266 list<SubtargetFeature> ExynosM4 = [HasV8_2aOps, FeatureCrypto, FeatureDotProd, 1267 FeatureFullFP16, FeaturePerfMon]; 1268 list<SubtargetFeature> Falkor = [HasV8_0aOps, FeatureCRC, FeatureCrypto, 1269 FeatureFPARMv8, FeatureNEON, FeaturePerfMon, 1270 FeatureRDM]; 1271 list<SubtargetFeature> NeoverseE1 = [HasV8_2aOps, FeatureCrypto, FeatureDotProd, 1272 FeatureFPARMv8, FeatureFullFP16, FeatureNEON, 1273 FeatureRCPC, FeatureSSBS, FeaturePerfMon]; 1274 list<SubtargetFeature> NeoverseN1 = [HasV8_2aOps, FeatureCrypto, FeatureDotProd, 1275 FeatureFPARMv8, FeatureFullFP16, FeatureNEON, 1276 FeatureRCPC, FeatureSPE, FeatureSSBS, 1277 FeaturePerfMon]; 1278 list<SubtargetFeature> NeoverseN2 = [HasV8_5aOps, FeatureBF16, FeatureETE, 1279 FeatureMatMulInt8, FeatureMTE, FeatureSVE2, 1280 FeatureSVE2BitPerm, FeatureTRBE, FeatureCrypto, 1281 FeaturePerfMon]; 1282 list<SubtargetFeature> Neoverse512TVB = [HasV8_4aOps, FeatureBF16, FeatureCacheDeepPersist, 1283 FeatureCrypto, FeatureFPARMv8, FeatureFP16FML, 1284 FeatureFullFP16, FeatureMatMulInt8, FeatureNEON, 1285 FeaturePerfMon, FeatureRandGen, FeatureSPE, 1286 FeatureSSBS, FeatureSVE]; 1287 list<SubtargetFeature> NeoverseV1 = [HasV8_4aOps, FeatureBF16, FeatureCacheDeepPersist, 1288 FeatureCrypto, FeatureFPARMv8, FeatureFP16FML, 1289 FeatureFullFP16, FeatureMatMulInt8, FeatureNEON, 1290 FeaturePerfMon, FeatureRandGen, FeatureSPE, 1291 FeatureSSBS, FeatureSVE]; 1292 list<SubtargetFeature> NeoverseV2 = [HasV9_0aOps, FeatureBF16, FeatureSPE, 1293 FeaturePerfMon, FeatureETE, FeatureMatMulInt8, 1294 FeatureNEON, FeatureSVE2BitPerm, FeatureFP16FML, 1295 FeatureMTE, FeatureRandGen]; 1296 list<SubtargetFeature> Saphira = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8, 1297 FeatureNEON, FeatureSPE, FeaturePerfMon]; 1298 list<SubtargetFeature> ThunderX = [HasV8_0aOps, FeatureCRC, FeatureCrypto, 1299 FeatureFPARMv8, FeaturePerfMon, FeatureNEON]; 1300 list<SubtargetFeature> ThunderX2T99 = [HasV8_1aOps, FeatureCRC, FeatureCrypto, 1301 FeatureFPARMv8, FeatureNEON, FeatureLSE]; 1302 list<SubtargetFeature> ThunderX3T110 = [HasV8_3aOps, FeatureCRC, FeatureCrypto, 1303 FeatureFPARMv8, FeatureNEON, FeatureLSE, 1304 FeaturePAuth, FeaturePerfMon]; 1305 list<SubtargetFeature> TSV110 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1306 FeatureNEON, FeaturePerfMon, FeatureSPE, 1307 FeatureFullFP16, FeatureFP16FML, FeatureDotProd]; 1308 list<SubtargetFeature> Ampere1 = [HasV8_6aOps, FeatureNEON, FeaturePerfMon, 1309 FeatureSSBS, FeatureRandGen, FeatureSB, 1310 FeatureSHA2, FeatureSHA3, FeatureAES]; 1311 list<SubtargetFeature> Ampere1A = [HasV8_6aOps, FeatureNEON, FeaturePerfMon, 1312 FeatureMTE, FeatureSSBS, FeatureRandGen, 1313 FeatureSB, FeatureSM4, FeatureSHA2, 1314 FeatureSHA3, FeatureAES]; 1315 1316 // ETE and TRBE are future architecture extensions. We temporarily enable them 1317 // by default for users targeting generic AArch64. The extensions do not 1318 // affect code generated by the compiler and can be used only by explicitly 1319 // mentioning the new system register names in assembly. 1320 list<SubtargetFeature> Generic = [FeatureFPARMv8, FeatureNEON, FeatureETE]; 1321} 1322 1323// FeatureFuseAdrpAdd is enabled under Generic to allow linker merging 1324// optimizations. 1325def : ProcessorModel<"generic", CortexA55Model, ProcessorFeatures.Generic, 1326 [FeatureFuseAES, FeatureFuseAdrpAdd, FeaturePostRAScheduler, 1327 FeatureEnableSelectOptimize]>; 1328def : ProcessorModel<"cortex-a35", CortexA53Model, ProcessorFeatures.A53, 1329 [TuneA35]>; 1330def : ProcessorModel<"cortex-a34", CortexA53Model, ProcessorFeatures.A53, 1331 [TuneA35]>; 1332def : ProcessorModel<"cortex-a53", CortexA53Model, ProcessorFeatures.A53, 1333 [TuneA53]>; 1334def : ProcessorModel<"cortex-a55", CortexA55Model, ProcessorFeatures.A55, 1335 [TuneA55]>; 1336def : ProcessorModel<"cortex-a510", CortexA55Model, ProcessorFeatures.A510, 1337 [TuneA510]>; 1338def : ProcessorModel<"cortex-a57", CortexA57Model, ProcessorFeatures.A53, 1339 [TuneA57]>; 1340def : ProcessorModel<"cortex-a65", CortexA53Model, ProcessorFeatures.A65, 1341 [TuneA65]>; 1342def : ProcessorModel<"cortex-a65ae", CortexA53Model, ProcessorFeatures.A65, 1343 [TuneA65]>; 1344def : ProcessorModel<"cortex-a72", CortexA57Model, ProcessorFeatures.A53, 1345 [TuneA72]>; 1346def : ProcessorModel<"cortex-a73", CortexA57Model, ProcessorFeatures.A53, 1347 [TuneA73]>; 1348def : ProcessorModel<"cortex-a75", CortexA57Model, ProcessorFeatures.A55, 1349 [TuneA75]>; 1350def : ProcessorModel<"cortex-a76", CortexA57Model, ProcessorFeatures.A76, 1351 [TuneA76]>; 1352def : ProcessorModel<"cortex-a76ae", CortexA57Model, ProcessorFeatures.A76, 1353 [TuneA76]>; 1354def : ProcessorModel<"cortex-a77", CortexA57Model, ProcessorFeatures.A77, 1355 [TuneA77]>; 1356def : ProcessorModel<"cortex-a78", CortexA57Model, ProcessorFeatures.A78, 1357 [TuneA78]>; 1358def : ProcessorModel<"cortex-a78c", CortexA57Model, ProcessorFeatures.A78C, 1359 [TuneA78C]>; 1360def : ProcessorModel<"cortex-a710", NeoverseN2Model, ProcessorFeatures.A710, 1361 [TuneA710]>; 1362def : ProcessorModel<"cortex-a715", NeoverseN2Model, ProcessorFeatures.A715, 1363 [TuneA715]>; 1364def : ProcessorModel<"cortex-r82", CortexA55Model, ProcessorFeatures.R82, 1365 [TuneR82]>; 1366def : ProcessorModel<"cortex-x1", CortexA57Model, ProcessorFeatures.X1, 1367 [TuneX1]>; 1368def : ProcessorModel<"cortex-x1c", CortexA57Model, ProcessorFeatures.X1C, 1369 [TuneX1]>; 1370def : ProcessorModel<"cortex-x2", NeoverseN2Model, ProcessorFeatures.X2, 1371 [TuneX2]>; 1372def : ProcessorModel<"cortex-x3", NeoverseN2Model, ProcessorFeatures.X3, 1373 [TuneX3]>; 1374def : ProcessorModel<"neoverse-e1", CortexA53Model, 1375 ProcessorFeatures.NeoverseE1, [TuneNeoverseE1]>; 1376def : ProcessorModel<"neoverse-n1", CortexA57Model, 1377 ProcessorFeatures.NeoverseN1, [TuneNeoverseN1]>; 1378def : ProcessorModel<"neoverse-n2", NeoverseN2Model, 1379 ProcessorFeatures.NeoverseN2, [TuneNeoverseN2]>; 1380def : ProcessorModel<"neoverse-512tvb", NeoverseN2Model, 1381 ProcessorFeatures.Neoverse512TVB, [TuneNeoverse512TVB]>; 1382def : ProcessorModel<"neoverse-v1", NeoverseN2Model, 1383 ProcessorFeatures.NeoverseV1, [TuneNeoverseV1]>; 1384def : ProcessorModel<"neoverse-v2", NeoverseN2Model, 1385 ProcessorFeatures.NeoverseV2, [TuneNeoverseV2]>; 1386def : ProcessorModel<"exynos-m3", ExynosM3Model, ProcessorFeatures.ExynosM3, 1387 [TuneExynosM3]>; 1388def : ProcessorModel<"exynos-m4", ExynosM4Model, ProcessorFeatures.ExynosM4, 1389 [TuneExynosM4]>; 1390def : ProcessorModel<"exynos-m5", ExynosM5Model, ProcessorFeatures.ExynosM4, 1391 [TuneExynosM4]>; 1392def : ProcessorModel<"falkor", FalkorModel, ProcessorFeatures.Falkor, 1393 [TuneFalkor]>; 1394def : ProcessorModel<"saphira", FalkorModel, ProcessorFeatures.Saphira, 1395 [TuneSaphira]>; 1396def : ProcessorModel<"kryo", KryoModel, ProcessorFeatures.A53, [TuneKryo]>; 1397 1398// Cavium ThunderX/ThunderX T8X Processors 1399def : ProcessorModel<"thunderx", ThunderXT8XModel, ProcessorFeatures.ThunderX, 1400 [TuneThunderX]>; 1401def : ProcessorModel<"thunderxt88", ThunderXT8XModel, 1402 ProcessorFeatures.ThunderX, [TuneThunderXT88]>; 1403def : ProcessorModel<"thunderxt81", ThunderXT8XModel, 1404 ProcessorFeatures.ThunderX, [TuneThunderXT81]>; 1405def : ProcessorModel<"thunderxt83", ThunderXT8XModel, 1406 ProcessorFeatures.ThunderX, [TuneThunderXT83]>; 1407// Cavium ThunderX2T9X Processors. Formerly Broadcom Vulcan. 1408def : ProcessorModel<"thunderx2t99", ThunderX2T99Model, 1409 ProcessorFeatures.ThunderX2T99, [TuneThunderX2T99]>; 1410// Marvell ThunderX3T110 Processors. 1411def : ProcessorModel<"thunderx3t110", ThunderX3T110Model, 1412 ProcessorFeatures.ThunderX3T110, [TuneThunderX3T110]>; 1413def : ProcessorModel<"tsv110", TSV110Model, ProcessorFeatures.TSV110, 1414 [TuneTSV110]>; 1415 1416// Support cyclone as an alias for apple-a7 so we can still LTO old bitcode. 1417def : ProcessorModel<"cyclone", CycloneModel, ProcessorFeatures.AppleA7, 1418 [TuneAppleA7]>; 1419 1420// iPhone and iPad CPUs 1421def : ProcessorModel<"apple-a7", CycloneModel, ProcessorFeatures.AppleA7, 1422 [TuneAppleA7]>; 1423def : ProcessorModel<"apple-a8", CycloneModel, ProcessorFeatures.AppleA7, 1424 [TuneAppleA7]>; 1425def : ProcessorModel<"apple-a9", CycloneModel, ProcessorFeatures.AppleA7, 1426 [TuneAppleA7]>; 1427def : ProcessorModel<"apple-a10", CycloneModel, ProcessorFeatures.AppleA10, 1428 [TuneAppleA10]>; 1429def : ProcessorModel<"apple-a11", CycloneModel, ProcessorFeatures.AppleA11, 1430 [TuneAppleA11]>; 1431def : ProcessorModel<"apple-a12", CycloneModel, ProcessorFeatures.AppleA12, 1432 [TuneAppleA12]>; 1433def : ProcessorModel<"apple-a13", CycloneModel, ProcessorFeatures.AppleA13, 1434 [TuneAppleA13]>; 1435def : ProcessorModel<"apple-a14", CycloneModel, ProcessorFeatures.AppleA14, 1436 [TuneAppleA14]>; 1437def : ProcessorModel<"apple-a15", CycloneModel, ProcessorFeatures.AppleA15, 1438 [TuneAppleA15]>; 1439def : ProcessorModel<"apple-a16", CycloneModel, ProcessorFeatures.AppleA16, 1440 [TuneAppleA16]>; 1441 1442// Mac CPUs 1443def : ProcessorModel<"apple-m1", CycloneModel, ProcessorFeatures.AppleA14, 1444 [TuneAppleA14]>; 1445def : ProcessorModel<"apple-m2", CycloneModel, ProcessorFeatures.AppleA15, 1446 [TuneAppleA15]>; 1447 1448// watch CPUs. 1449def : ProcessorModel<"apple-s4", CycloneModel, ProcessorFeatures.AppleA12, 1450 [TuneAppleA12]>; 1451def : ProcessorModel<"apple-s5", CycloneModel, ProcessorFeatures.AppleA12, 1452 [TuneAppleA12]>; 1453 1454// Alias for the latest Apple processor model supported by LLVM. 1455def : ProcessorModel<"apple-latest", CycloneModel, ProcessorFeatures.AppleA16, 1456 [TuneAppleA16]>; 1457 1458// Fujitsu A64FX 1459def : ProcessorModel<"a64fx", A64FXModel, ProcessorFeatures.A64FX, 1460 [TuneA64FX]>; 1461 1462// Nvidia Carmel 1463def : ProcessorModel<"carmel", NoSchedModel, ProcessorFeatures.Carmel, 1464 [TuneCarmel]>; 1465 1466// Ampere Computing 1467def : ProcessorModel<"ampere1", Ampere1Model, ProcessorFeatures.Ampere1, 1468 [TuneAmpere1]>; 1469 1470def : ProcessorModel<"ampere1a", Ampere1Model, ProcessorFeatures.Ampere1A, 1471 [TuneAmpere1A]>; 1472 1473//===----------------------------------------------------------------------===// 1474// Assembly parser 1475//===----------------------------------------------------------------------===// 1476 1477def GenericAsmParserVariant : AsmParserVariant { 1478 int Variant = 0; 1479 string Name = "generic"; 1480 string BreakCharacters = "."; 1481 string TokenizingCharacters = "[]*!/"; 1482} 1483 1484def AppleAsmParserVariant : AsmParserVariant { 1485 int Variant = 1; 1486 string Name = "apple-neon"; 1487 string BreakCharacters = "."; 1488 string TokenizingCharacters = "[]*!/"; 1489} 1490 1491//===----------------------------------------------------------------------===// 1492// Assembly printer 1493//===----------------------------------------------------------------------===// 1494// AArch64 Uses the MC printer for asm output, so make sure the TableGen 1495// AsmWriter bits get associated with the correct class. 1496def GenericAsmWriter : AsmWriter { 1497 string AsmWriterClassName = "InstPrinter"; 1498 int PassSubtarget = 1; 1499 int Variant = 0; 1500 bit isMCAsmWriter = 1; 1501} 1502 1503def AppleAsmWriter : AsmWriter { 1504 let AsmWriterClassName = "AppleInstPrinter"; 1505 int PassSubtarget = 1; 1506 int Variant = 1; 1507 int isMCAsmWriter = 1; 1508} 1509 1510//===----------------------------------------------------------------------===// 1511// Target Declaration 1512//===----------------------------------------------------------------------===// 1513 1514def AArch64 : Target { 1515 let InstructionSet = AArch64InstrInfo; 1516 let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant]; 1517 let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter]; 1518 let AllowRegisterRenaming = 1; 1519} 1520 1521//===----------------------------------------------------------------------===// 1522// Pfm Counters 1523//===----------------------------------------------------------------------===// 1524 1525include "AArch64PfmCounters.td" 1526