1//=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// 10//===----------------------------------------------------------------------===// 11 12//===----------------------------------------------------------------------===// 13// Target-independent interfaces which we are implementing. 14//===----------------------------------------------------------------------===// 15 16include "llvm/Target/Target.td" 17 18//===----------------------------------------------------------------------===// 19// AArch64 Subtarget features. 20// 21 22// Each SubtargetFeature which corresponds to an Arm Architecture feature should 23// be annotated with the respective FEAT_ feature name from the Architecture 24// Reference Manual. If a SubtargetFeature enables instructions from multiple 25// Arm Architecture Features, it should list all the relevant features. Not all 26// FEAT_ features have a corresponding SubtargetFeature. 27 28def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true", 29 "Enable ARMv8 FP (FEAT_FP)">; 30 31def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", 32 "Enable Advanced SIMD instructions (FEAT_AdvSIMD)", [FeatureFPARMv8]>; 33 34def FeatureSM4 : SubtargetFeature< 35 "sm4", "HasSM4", "true", 36 "Enable SM3 and SM4 support (FEAT_SM4, FEAT_SM3)", [FeatureNEON]>; 37 38def FeatureSHA2 : SubtargetFeature< 39 "sha2", "HasSHA2", "true", 40 "Enable SHA1 and SHA256 support (FEAT_SHA1, FEAT_SHA256)", [FeatureNEON]>; 41 42def FeatureSHA3 : SubtargetFeature< 43 "sha3", "HasSHA3", "true", 44 "Enable SHA512 and SHA3 support (FEAT_SHA3, FEAT_SHA512)", [FeatureNEON, FeatureSHA2]>; 45 46def FeatureAES : SubtargetFeature< 47 "aes", "HasAES", "true", 48 "Enable AES support (FEAT_AES, FEAT_PMULL)", [FeatureNEON]>; 49 50// Crypto has been split up and any combination is now valid (see the 51// crypto definitions above). Also, crypto is now context sensitive: 52// it has a different meaning for e.g. Armv8.4 than it has for Armv8.2. 53// Therefore, we rely on Clang, the user interfacing tool, to pass on the 54// appropriate crypto options. But here in the backend, crypto has very little 55// meaning anymore. We kept the Crypto definition here for backward 56// compatibility, and now imply features SHA2 and AES, which was the 57// "traditional" meaning of Crypto. 58def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", 59 "Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>; 60 61def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", 62 "Enable ARMv8 CRC-32 checksum instructions (FEAT_CRC32)">; 63 64def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true", 65 "Enable ARMv8 Reliability, Availability and Serviceability Extensions (FEAT_RAS, FEAT_RASv1p1)">; 66 67def FeatureRASv2 : SubtargetFeature<"rasv2", "HasRASv2", "true", 68 "Enable ARMv8.9-A Reliability, Availability and Serviceability Extensions (FEAT_RASv2)", 69 [FeatureRAS]>; 70 71def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true", 72 "Enable ARMv8.1 Large System Extension (LSE) atomic instructions (FEAT_LSE)">; 73 74def FeatureLSE2 : SubtargetFeature<"lse2", "HasLSE2", "true", 75 "Enable ARMv8.4 Large System Extension 2 (LSE2) atomicity rules (FEAT_LSE2)">; 76 77def FeatureOutlineAtomics : SubtargetFeature<"outline-atomics", "OutlineAtomics", "true", 78 "Enable out of line atomics to support LSE instructions">; 79 80def FeatureFMV : SubtargetFeature<"fmv", "HasFMV", "true", 81 "Enable Function Multi Versioning support.">; 82 83def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true", 84 "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions (FEAT_RDM)">; 85 86def FeaturePAN : SubtargetFeature< 87 "pan", "HasPAN", "true", 88 "Enables ARM v8.1 Privileged Access-Never extension (FEAT_PAN)">; 89 90def FeatureLOR : SubtargetFeature< 91 "lor", "HasLOR", "true", 92 "Enables ARM v8.1 Limited Ordering Regions extension (FEAT_LOR)">; 93 94def FeatureCONTEXTIDREL2 : SubtargetFeature<"CONTEXTIDREL2", "HasCONTEXTIDREL2", 95 "true", "Enable RW operand CONTEXTIDR_EL2" >; 96 97def FeatureVH : SubtargetFeature<"vh", "HasVH", "true", 98 "Enables ARM v8.1 Virtual Host extension (FEAT_VHE)", [FeatureCONTEXTIDREL2] >; 99 100// This SubtargetFeature is special. It controls only whether codegen will turn 101// `llvm.readcyclecounter()` into an access to a PMUv3 System Register. The 102// `FEAT_PMUv3*` system registers are always available for assembly/disassembly. 103def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", 104 "Enable Code Generation for ARMv8 PMUv3 Performance Monitors extension (FEAT_PMUv3)">; 105 106def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true", 107 "Full FP16 (FEAT_FP16)", [FeatureFPARMv8]>; 108 109def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true", 110 "Enable FP16 FML instructions (FEAT_FHM)", [FeatureFullFP16]>; 111 112def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true", 113 "Enable Statistical Profiling extension (FEAT_SPE)">; 114 115def FeaturePAN_RWV : SubtargetFeature< 116 "pan-rwv", "HasPAN_RWV", "true", 117 "Enable v8.2 PAN s1e1R and s1e1W Variants (FEAT_PAN2)", 118 [FeaturePAN]>; 119 120// UAO PState 121def FeaturePsUAO : SubtargetFeature< "uaops", "HasPsUAO", "true", 122 "Enable v8.2 UAO PState (FEAT_UAO)">; 123 124def FeatureCCPP : SubtargetFeature<"ccpp", "HasCCPP", 125 "true", "Enable v8.2 data Cache Clean to Point of Persistence (FEAT_DPB)" >; 126 127def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true", 128 "Enable Scalable Vector Extension (SVE) instructions (FEAT_SVE)", [FeatureFullFP16]>; 129 130def FeatureFPMR : SubtargetFeature<"fpmr", "HasFPMR", "true", 131 "Enable FPMR Register (FEAT_FPMR)">; 132 133def FeatureFP8 : SubtargetFeature<"fp8", "HasFP8", "true", 134 "Enable FP8 instructions (FEAT_FP8)">; 135 136// This flag is currently still labeled as Experimental, but when fully 137// implemented this should tell the compiler to use the zeroing pseudos to 138// benefit from the reverse instructions (e.g. SUB vs SUBR) if the inactive 139// lanes are known to be zero. The pseudos will then be expanded using the 140// MOVPRFX instruction to zero the inactive lanes. This feature should only be 141// enabled if MOVPRFX instructions are known to merge with the destructive 142// operations they prefix. 143// 144// This feature could similarly be extended to support cheap merging of _any_ 145// value into the inactive lanes using the MOVPRFX instruction that uses 146// merging-predication. 147def FeatureExperimentalZeroingPseudos 148 : SubtargetFeature<"use-experimental-zeroing-pseudos", 149 "UseExperimentalZeroingPseudos", "true", 150 "Hint to the compiler that the MOVPRFX instruction is " 151 "merged with destructive operations", 152 []>; 153 154def FeatureUseScalarIncVL : SubtargetFeature<"use-scalar-inc-vl", 155 "UseScalarIncVL", "true", "Prefer inc/dec over add+cnt">; 156 157def FeatureBF16 : SubtargetFeature<"bf16", "HasBF16", 158 "true", "Enable BFloat16 Extension (FEAT_BF16)" >; 159 160def FeatureNoSVEFPLD1R : SubtargetFeature<"no-sve-fp-ld1r", 161 "NoSVEFPLD1R", "true", "Avoid using LD1RX instructions for FP">; 162 163def FeatureSVE2 : SubtargetFeature<"sve2", "HasSVE2", "true", 164 "Enable Scalable Vector Extension 2 (SVE2) instructions (FEAT_SVE2)", 165 [FeatureSVE, FeatureUseScalarIncVL]>; 166 167def FeatureSVE2AES : SubtargetFeature<"sve2-aes", "HasSVE2AES", "true", 168 "Enable AES SVE2 instructions (FEAT_SVE_AES, FEAT_SVE_PMULL128)", 169 [FeatureSVE2, FeatureAES]>; 170 171def FeatureSVE2SM4 : SubtargetFeature<"sve2-sm4", "HasSVE2SM4", "true", 172 "Enable SM4 SVE2 instructions (FEAT_SVE_SM4)", [FeatureSVE2, FeatureSM4]>; 173 174def FeatureSVE2SHA3 : SubtargetFeature<"sve2-sha3", "HasSVE2SHA3", "true", 175 "Enable SHA3 SVE2 instructions (FEAT_SVE_SHA3)", [FeatureSVE2, FeatureSHA3]>; 176 177def FeatureSVE2BitPerm : SubtargetFeature<"sve2-bitperm", "HasSVE2BitPerm", "true", 178 "Enable bit permutation SVE2 instructions (FEAT_SVE_BitPerm)", [FeatureSVE2]>; 179 180def FeatureSVE2p1: SubtargetFeature<"sve2p1", "HasSVE2p1", "true", 181 "Enable Scalable Vector Extension 2.1 instructions", [FeatureSVE2]>; 182 183def FeatureB16B16 : SubtargetFeature<"b16b16", "HasB16B16", "true", 184 "Enable SVE2.1 or SME2.1 non-widening BFloat16 to BFloat16 instructions (FEAT_B16B16)", [FeatureBF16]>; 185 186def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true", 187 "Has zero-cycle register moves">; 188 189def FeatureZCZeroingGP : SubtargetFeature<"zcz-gp", "HasZeroCycleZeroingGP", "true", 190 "Has zero-cycle zeroing instructions for generic registers">; 191 192// It is generally beneficial to rewrite "fmov s0, wzr" to "movi d0, #0". 193// as movi is more efficient across all cores. Newer cores can eliminate 194// fmovs early and there is no difference with movi, but this not true for 195// all implementations. 196def FeatureNoZCZeroingFP : SubtargetFeature<"no-zcz-fp", "HasZeroCycleZeroingFP", "false", 197 "Has no zero-cycle zeroing instructions for FP registers">; 198 199def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true", 200 "Has zero-cycle zeroing instructions", 201 [FeatureZCZeroingGP]>; 202 203/// ... but the floating-point version doesn't quite work in rare cases on older 204/// CPUs. 205def FeatureZCZeroingFPWorkaround : SubtargetFeature<"zcz-fp-workaround", 206 "HasZeroCycleZeroingFPWorkaround", "true", 207 "The zero-cycle floating-point zeroing instruction has a bug">; 208 209def FeatureStrictAlign : SubtargetFeature<"strict-align", 210 "RequiresStrictAlign", "true", 211 "Disallow all unaligned memory " 212 "access">; 213 214foreach i = {1-7,9-15,18,20-28,30} in 215 def FeatureReserveX#i : SubtargetFeature<"reserve-x"#i, "ReserveXRegister["#i#"]", "true", 216 "Reserve X"#i#", making it unavailable " 217 "as a GPR">; 218 219foreach i = {8-15,18} in 220 def FeatureCallSavedX#i : SubtargetFeature<"call-saved-x"#i, 221 "CustomCallSavedXRegs["#i#"]", "true", "Make X"#i#" callee saved.">; 222 223def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps", 224 "true", 225 "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">; 226 227def FeaturePredictableSelectIsExpensive : SubtargetFeature< 228 "predictable-select-expensive", "PredictableSelectIsExpensive", "true", 229 "Prefer likely predicted branches over selects">; 230 231def FeatureEnableSelectOptimize : SubtargetFeature< 232 "enable-select-opt", "EnableSelectOptimize", "true", 233 "Enable the select optimize pass for select loop heuristics">; 234 235def FeatureExynosCheapAsMoveHandling : SubtargetFeature<"exynos-cheap-as-move", 236 "HasExynosCheapAsMoveHandling", "true", 237 "Use Exynos specific handling of cheap instructions">; 238 239def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler", 240 "UsePostRAScheduler", "true", "Schedule again after register allocation">; 241 242def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store", 243 "IsMisaligned128StoreSlow", "true", "Misaligned 128 bit stores are slow">; 244 245def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128", 246 "IsPaired128Slow", "true", "Paired 128 bit loads and stores are slow">; 247 248def FeatureAscendStoreAddress : SubtargetFeature<"ascend-store-address", 249 "IsStoreAddressAscend", "true", 250 "Schedule vector stores by ascending address">; 251 252def FeatureSlowSTRQro : SubtargetFeature<"slow-strqro-store", "IsSTRQroSlow", 253 "true", "STR of Q register with register offset is slow">; 254 255def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature< 256 "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern", 257 "true", "Use alternative pattern for sextload convert to f32">; 258 259def FeatureArithmeticBccFusion : SubtargetFeature< 260 "arith-bcc-fusion", "HasArithmeticBccFusion", "true", 261 "CPU fuses arithmetic+bcc operations">; 262 263def FeatureArithmeticCbzFusion : SubtargetFeature< 264 "arith-cbz-fusion", "HasArithmeticCbzFusion", "true", 265 "CPU fuses arithmetic + cbz/cbnz operations">; 266 267def FeatureCmpBccFusion : SubtargetFeature< 268 "cmp-bcc-fusion", "HasCmpBccFusion", "true", 269 "CPU fuses cmp+bcc operations">; 270 271def FeatureFuseAddress : SubtargetFeature< 272 "fuse-address", "HasFuseAddress", "true", 273 "CPU fuses address generation and memory operations">; 274 275def FeatureFuseAES : SubtargetFeature< 276 "fuse-aes", "HasFuseAES", "true", 277 "CPU fuses AES crypto operations">; 278 279def FeatureFuseArithmeticLogic : SubtargetFeature< 280 "fuse-arith-logic", "HasFuseArithmeticLogic", "true", 281 "CPU fuses arithmetic and logic operations">; 282 283def FeatureFuseCCSelect : SubtargetFeature< 284 "fuse-csel", "HasFuseCCSelect", "true", 285 "CPU fuses conditional select operations">; 286 287def FeatureFuseCryptoEOR : SubtargetFeature< 288 "fuse-crypto-eor", "HasFuseCryptoEOR", "true", 289 "CPU fuses AES/PMULL and EOR operations">; 290 291def FeatureFuseAdrpAdd : SubtargetFeature< 292 "fuse-adrp-add", "HasFuseAdrpAdd", "true", 293 "CPU fuses adrp+add operations">; 294 295def FeatureFuseLiterals : SubtargetFeature< 296 "fuse-literals", "HasFuseLiterals", "true", 297 "CPU fuses literal generation operations">; 298 299def FeatureFuseAddSub2RegAndConstOne : SubtargetFeature< 300 "fuse-addsub-2reg-const1", "HasFuseAddSub2RegAndConstOne", "true", 301 "CPU fuses (a + b + 1) and (a - b - 1)">; 302 303def FeatureDisableLatencySchedHeuristic : SubtargetFeature< 304 "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true", 305 "Disable latency scheduling heuristic">; 306 307def FeatureStorePairSuppress : SubtargetFeature< 308 "store-pair-suppress", "EnableStorePairSuppress", "true", 309 "Enable Store Pair Suppression heuristics">; 310 311def FeatureForce32BitJumpTables 312 : SubtargetFeature<"force-32bit-jump-tables", "Force32BitJumpTables", "true", 313 "Force jump table entries to be 32-bits wide except at MinSize">; 314 315def FeatureRCPC : SubtargetFeature<"rcpc", "HasRCPC", "true", 316 "Enable support for RCPC extension (FEAT_LRCPC)">; 317 318def FeatureUseRSqrt : SubtargetFeature< 319 "use-reciprocal-square-root", "UseRSqrt", "true", 320 "Use the reciprocal square root approximation">; 321 322def FeatureDotProd : SubtargetFeature< 323 "dotprod", "HasDotProd", "true", 324 "Enable dot product support (FEAT_DotProd)">; 325 326def FeaturePAuth : SubtargetFeature< 327 "pauth", "HasPAuth", "true", 328 "Enable v8.3-A Pointer Authentication extension (FEAT_PAuth)">; 329 330def FeatureJS : SubtargetFeature< 331 "jsconv", "HasJS", "true", 332 "Enable v8.3-A JavaScript FP conversion instructions (FEAT_JSCVT)", 333 [FeatureFPARMv8]>; 334 335def FeatureCCIDX : SubtargetFeature< 336 "ccidx", "HasCCIDX", "true", 337 "Enable v8.3-A Extend of the CCSIDR number of sets (FEAT_CCIDX)">; 338 339def FeatureComplxNum : SubtargetFeature< 340 "complxnum", "HasComplxNum", "true", 341 "Enable v8.3-A Floating-point complex number support (FEAT_FCMA)", 342 [FeatureNEON]>; 343 344def FeatureNV : SubtargetFeature< 345 "nv", "HasNV", "true", 346 "Enable v8.4-A Nested Virtualization Enchancement (FEAT_NV, FEAT_NV2)">; 347 348def FeatureMPAM : SubtargetFeature< 349 "mpam", "HasMPAM", "true", 350 "Enable v8.4-A Memory system Partitioning and Monitoring extension (FEAT_MPAM)">; 351 352def FeatureDIT : SubtargetFeature< 353 "dit", "HasDIT", "true", 354 "Enable v8.4-A Data Independent Timing instructions (FEAT_DIT)">; 355 356def FeatureTRACEV8_4 : SubtargetFeature< 357 "tracev8.4", "HasTRACEV8_4", "true", 358 "Enable v8.4-A Trace extension (FEAT_TRF)">; 359 360def FeatureAM : SubtargetFeature< 361 "am", "HasAM", "true", 362 "Enable v8.4-A Activity Monitors extension (FEAT_AMUv1)">; 363 364def FeatureAMVS : SubtargetFeature< 365 "amvs", "HasAMVS", "true", 366 "Enable v8.6-A Activity Monitors Virtualization support (FEAT_AMUv1p1)", 367 [FeatureAM]>; 368 369def FeatureSEL2 : SubtargetFeature< 370 "sel2", "HasSEL2", "true", 371 "Enable v8.4-A Secure Exception Level 2 extension (FEAT_SEL2)">; 372 373def FeatureTLB_RMI : SubtargetFeature< 374 "tlb-rmi", "HasTLB_RMI", "true", 375 "Enable v8.4-A TLB Range and Maintenance Instructions (FEAT_TLBIOS, FEAT_TLBIRANGE)">; 376 377def FeatureFlagM : SubtargetFeature< 378 "flagm", "HasFlagM", "true", 379 "Enable v8.4-A Flag Manipulation Instructions (FEAT_FlagM)">; 380 381// 8.4 RCPC enchancements: LDAPR & STLR instructions with Immediate Offset 382def FeatureRCPC_IMMO : SubtargetFeature<"rcpc-immo", "HasRCPC_IMMO", "true", 383 "Enable v8.4-A RCPC instructions with Immediate Offsets (FEAT_LRCPC2)", 384 [FeatureRCPC]>; 385 386def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates", 387 "NegativeImmediates", "false", 388 "Convert immediates and instructions " 389 "to their negated or complemented " 390 "equivalent when the immediate does " 391 "not fit in the encoding.">; 392 393def FeatureAddrLSLFast : SubtargetFeature< 394 "addr-lsl-fast", "HasAddrLSLFast", "true", 395 "Address operands with logical shift of up to 3 places are cheap">; 396 397def FeatureALULSLFast : SubtargetFeature< 398 "alu-lsl-fast", "HasALULSLFast", "true", 399 "Add/Sub operations with lsl shift <= 4 are cheap">; 400 401def FeatureAggressiveFMA : 402 SubtargetFeature<"aggressive-fma", 403 "HasAggressiveFMA", 404 "true", 405 "Enable Aggressive FMA for floating-point.">; 406 407def FeatureAltFPCmp : SubtargetFeature<"altnzcv", "HasAlternativeNZCV", "true", 408 "Enable alternative NZCV format for floating point comparisons (FEAT_FlagM2)">; 409 410def FeatureFRInt3264 : SubtargetFeature<"fptoint", "HasFRInt3264", "true", 411 "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to " 412 "an integer (in FP format) forcing it to fit into a 32- or 64-bit int (FEAT_FRINTTS)" >; 413 414def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict", 415 "true", "Enable architectural speculation restriction (FEAT_CSV2_2)">; 416 417def FeatureSB : SubtargetFeature<"sb", "HasSB", 418 "true", "Enable v8.5 Speculation Barrier (FEAT_SB)" >; 419 420def FeatureSSBS : SubtargetFeature<"ssbs", "HasSSBS", 421 "true", "Enable Speculative Store Bypass Safe bit (FEAT_SSBS, FEAT_SSBS2)" >; 422 423def FeaturePredRes : SubtargetFeature<"predres", "HasPredRes", "true", 424 "Enable v8.5a execution and data prediction invalidation instructions (FEAT_SPECRES)" >; 425 426def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP", 427 "true", "Enable v8.5 Cache Clean to Point of Deep Persistence (FEAT_DPB2)" >; 428 429def FeatureBranchTargetId : SubtargetFeature<"bti", "HasBTI", 430 "true", "Enable Branch Target Identification (FEAT_BTI)" >; 431 432def FeatureRandGen : SubtargetFeature<"rand", "HasRandGen", 433 "true", "Enable Random Number generation instructions (FEAT_RNG)" >; 434 435def FeatureMTE : SubtargetFeature<"mte", "HasMTE", 436 "true", "Enable Memory Tagging Extension (FEAT_MTE, FEAT_MTE2)" >; 437 438def FeatureTRBE : SubtargetFeature<"trbe", "HasTRBE", 439 "true", "Enable Trace Buffer Extension (FEAT_TRBE)">; 440 441def FeatureETE : SubtargetFeature<"ete", "HasETE", 442 "true", "Enable Embedded Trace Extension (FEAT_ETE)", 443 [FeatureTRBE]>; 444 445def FeatureTME : SubtargetFeature<"tme", "HasTME", 446 "true", "Enable Transactional Memory Extension (FEAT_TME)" >; 447 448def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals", 449 "AllowTaggedGlobals", 450 "true", "Use an instruction sequence for taking the address of a global " 451 "that allows a memory tag in the upper address bits">; 452 453def FeatureMatMulInt8 : SubtargetFeature<"i8mm", "HasMatMulInt8", 454 "true", "Enable Matrix Multiply Int8 Extension (FEAT_I8MM)">; 455 456def FeatureMatMulFP32 : SubtargetFeature<"f32mm", "HasMatMulFP32", 457 "true", "Enable Matrix Multiply FP32 Extension (FEAT_F32MM)", [FeatureSVE]>; 458 459def FeatureMatMulFP64 : SubtargetFeature<"f64mm", "HasMatMulFP64", 460 "true", "Enable Matrix Multiply FP64 Extension (FEAT_F64MM)", [FeatureSVE]>; 461 462def FeatureXS : SubtargetFeature<"xs", "HasXS", 463 "true", "Enable Armv8.7-A limited-TLB-maintenance instruction (FEAT_XS)">; 464 465def FeatureWFxT : SubtargetFeature<"wfxt", "HasWFxT", 466 "true", "Enable Armv8.7-A WFET and WFIT instruction (FEAT_WFxT)">; 467 468def FeatureHCX : SubtargetFeature< 469 "hcx", "HasHCX", "true", "Enable Armv8.7-A HCRX_EL2 system register (FEAT_HCX)">; 470 471def FeatureLS64 : SubtargetFeature<"ls64", "HasLS64", 472 "true", "Enable Armv8.7-A LD64B/ST64B Accelerator Extension (FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA)">; 473 474def FeatureHBC : SubtargetFeature<"hbc", "HasHBC", 475 "true", "Enable Armv8.8-A Hinted Conditional Branches Extension (FEAT_HBC)">; 476 477def FeatureMOPS : SubtargetFeature<"mops", "HasMOPS", 478 "true", "Enable Armv8.8-A memcpy and memset acceleration instructions (FEAT_MOPS)">; 479 480def FeatureNMI : SubtargetFeature<"nmi", "HasNMI", 481 "true", "Enable Armv8.8-A Non-maskable Interrupts (FEAT_NMI, FEAT_GICv3_NMI)">; 482 483def FeatureBRBE : SubtargetFeature<"brbe", "HasBRBE", 484 "true", "Enable Branch Record Buffer Extension (FEAT_BRBE)">; 485 486def FeatureSPE_EEF : SubtargetFeature<"spe-eef", "HasSPE_EEF", 487 "true", "Enable extra register in the Statistical Profiling Extension (FEAT_SPEv1p2)">; 488 489def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps", 490 "true", "Enable fine grained virtualization traps extension (FEAT_FGT)">; 491 492def FeatureEnhancedCounterVirtualization : 493 SubtargetFeature<"ecv", "HasEnhancedCounterVirtualization", 494 "true", "Enable enhanced counter virtualization extension (FEAT_ECV)">; 495 496def FeatureRME : SubtargetFeature<"rme", "HasRME", 497 "true", "Enable Realm Management Extension (FEAT_RME)">; 498 499def FeatureSME : SubtargetFeature<"sme", "HasSME", "true", 500 "Enable Scalable Matrix Extension (SME) (FEAT_SME)", [FeatureBF16, FeatureUseScalarIncVL]>; 501 502def FeatureSMEF64F64 : SubtargetFeature<"sme-f64f64", "HasSMEF64F64", "true", 503 "Enable Scalable Matrix Extension (SME) F64F64 instructions (FEAT_SME_F64F64)", [FeatureSME]>; 504 505def FeatureSMEI16I64 : SubtargetFeature<"sme-i16i64", "HasSMEI16I64", "true", 506 "Enable Scalable Matrix Extension (SME) I16I64 instructions (FEAT_SME_I16I64)", [FeatureSME]>; 507 508def FeatureSMEF16F16 : SubtargetFeature<"sme-f16f16", "HasSMEF16F16", "true", 509 "Enable SME2.1 non-widening Float16 instructions (FEAT_SME_F16F16)", []>; 510 511def FeatureSMEFA64 : SubtargetFeature<"sme-fa64", "HasSMEFA64", "true", 512 "Enable the full A64 instruction set in streaming SVE mode (FEAT_SME_FA64)", [FeatureSME, FeatureSVE2]>; 513 514def FeatureSME2 : SubtargetFeature<"sme2", "HasSME2", "true", 515 "Enable Scalable Matrix Extension 2 (SME2) instructions", [FeatureSME]>; 516 517def FeatureSME2p1 : SubtargetFeature<"sme2p1", "HasSME2p1", "true", 518 "Enable Scalable Matrix Extension 2.1 (FEAT_SME2p1) instructions", [FeatureSME2]>; 519 520def FeatureFAMINMAX: SubtargetFeature<"faminmax", "HasFAMINMAX", "true", 521 "Enable FAMIN and FAMAX instructions (FEAT_FAMINMAX)">; 522 523def FeatureFP8FMA : SubtargetFeature<"fp8fma", "HasFP8FMA", "true", 524 "Enable fp8 multiply-add instructions (FEAT_FP8FMA)">; 525 526def FeatureSSVE_FP8FMA : SubtargetFeature<"ssve-fp8fma", "HasSSVE_FP8FMA", "true", 527 "Enable SVE2 fp8 multiply-add instructions (FEAT_SSVE_FP8FMA)", [FeatureSME2]>; 528 529def FeatureFP8DOT2: SubtargetFeature<"fp8dot2", "HasFP8DOT2", "true", 530 "Enable fp8 2-way dot instructions (FEAT_FP8DOT2)">; 531 532def FeatureSSVE_FP8DOT2 : SubtargetFeature<"ssve-fp8dot2", "HasSSVE_FP8DOT2", "true", 533 "Enable SVE2 fp8 2-way dot product instructions (FEAT_SSVE_FP8DOT2)", [FeatureSME2]>; 534 535def FeatureFP8DOT4: SubtargetFeature<"fp8dot4", "HasFP8DOT4", "true", 536 "Enable fp8 4-way dot instructions (FEAT_FP8DOT4)">; 537 538def FeatureSSVE_FP8DOT4 : SubtargetFeature<"ssve-fp8dot4", "HasSSVE_FP8DOT4", "true", 539 "Enable SVE2 fp8 4-way dot product instructions (FEAT_SSVE_FP8DOT4)", [FeatureSME2]>; 540def FeatureLUT: SubtargetFeature<"lut", "HasLUT", "true", 541 "Enable Lookup Table instructions (FEAT_LUT)">; 542 543def FeatureSME_LUTv2 : SubtargetFeature<"sme-lutv2", "HasSME_LUTv2", "true", 544 "Enable Scalable Matrix Extension (SME) LUTv2 instructions (FEAT_SME_LUTv2)">; 545 546def FeatureSMEF8F16 : SubtargetFeature<"sme-f8f16", "HasSMEF8F16", "true", 547 "Enable Scalable Matrix Extension (SME) F8F16 instructions(FEAT_SME_F8F16)", [FeatureSME2, FeatureFP8]>; 548 549def FeatureSMEF8F32 : SubtargetFeature<"sme-f8f32", "HasSMEF8F32", "true", 550 "Enable Scalable Matrix Extension (SME) F8F32 instructions (FEAT_SME_F8F32)", [FeatureSME2, FeatureFP8]>; 551 552def FeatureAppleA7SysReg : SubtargetFeature<"apple-a7-sysreg", "HasAppleA7SysReg", "true", 553 "Apple A7 (the CPU formerly known as Cyclone)">; 554 555def FeatureEL2VMSA : SubtargetFeature<"el2vmsa", "HasEL2VMSA", "true", 556 "Enable Exception Level 2 Virtual Memory System Architecture">; 557 558def FeatureEL3 : SubtargetFeature<"el3", "HasEL3", "true", 559 "Enable Exception Level 3">; 560 561def FeatureCSSC : SubtargetFeature<"cssc", "HasCSSC", "true", 562 "Enable Common Short Sequence Compression (CSSC) instructions (FEAT_CSSC)">; 563 564def FeatureFixCortexA53_835769 : SubtargetFeature<"fix-cortex-a53-835769", 565 "FixCortexA53_835769", "true", "Mitigate Cortex-A53 Erratum 835769">; 566 567def FeatureNoBTIAtReturnTwice : SubtargetFeature<"no-bti-at-return-twice", 568 "NoBTIAtReturnTwice", "true", 569 "Don't place a BTI instruction " 570 "after a return-twice">; 571 572def FeatureCHK : SubtargetFeature<"chk", "HasCHK", 573 "true", "Enable Armv8.0-A Check Feature Status Extension (FEAT_CHK)">; 574 575def FeatureGCS : SubtargetFeature<"gcs", "HasGCS", 576 "true", "Enable Armv9.4-A Guarded Call Stack Extension", [FeatureCHK]>; 577 578def FeatureCLRBHB : SubtargetFeature<"clrbhb", "HasCLRBHB", 579 "true", "Enable Clear BHB instruction (FEAT_CLRBHB)">; 580 581def FeaturePRFM_SLC : SubtargetFeature<"prfm-slc-target", "HasPRFM_SLC", 582 "true", "Enable SLC target for PRFM instruction">; 583 584def FeatureSPECRES2 : SubtargetFeature<"specres2", "HasSPECRES2", 585 "true", "Enable Speculation Restriction Instruction (FEAT_SPECRES2)", 586 [FeaturePredRes]>; 587 588def FeatureMEC : SubtargetFeature<"mec", "HasMEC", 589 "true", "Enable Memory Encryption Contexts Extension", [FeatureRME]>; 590 591def FeatureITE : SubtargetFeature<"ite", "HasITE", 592 "true", "Enable Armv9.4-A Instrumentation Extension FEAT_ITE", [FeatureETE, 593 FeatureTRBE]>; 594 595def FeatureRCPC3 : SubtargetFeature<"rcpc3", "HasRCPC3", 596 "true", "Enable Armv8.9-A RCPC instructions for A64 and Advanced SIMD and floating-point instruction set (FEAT_LRCPC3)", 597 [FeatureRCPC_IMMO]>; 598 599def FeatureTHE : SubtargetFeature<"the", "HasTHE", 600 "true", "Enable Armv8.9-A Translation Hardening Extension (FEAT_THE)">; 601 602def FeatureLSE128 : SubtargetFeature<"lse128", "HasLSE128", 603 "true", "Enable Armv9.4-A 128-bit Atomic Instructions (FEAT_LSE128)", 604 [FeatureLSE]>; 605 606// FEAT_D128, FEAT_LVA3, FEAT_SYSREG128, and FEAT_SYSINSTR128 are mutually implicit. 607// Therefore group them all under a single feature flag, d128: 608def FeatureD128 : SubtargetFeature<"d128", "HasD128", 609 "true", "Enable Armv9.4-A 128-bit Page Table Descriptors, System Registers " 610 "and Instructions (FEAT_D128, FEAT_LVA3, FEAT_SYSREG128, FEAT_SYSINSTR128)", 611 [FeatureLSE128]>; 612 613def FeatureDisableLdp : SubtargetFeature<"disable-ldp", "HasDisableLdp", 614 "true", "Do not emit ldp">; 615 616def FeatureDisableStp : SubtargetFeature<"disable-stp", "HasDisableStp", 617 "true", "Do not emit stp">; 618 619def FeatureLdpAlignedOnly : SubtargetFeature<"ldp-aligned-only", "HasLdpAlignedOnly", 620 "true", "In order to emit ldp, first check if the load will be aligned to 2 * element_size">; 621 622def FeatureStpAlignedOnly : SubtargetFeature<"stp-aligned-only", "HasStpAlignedOnly", 623 "true", "In order to emit stp, first check if the store will be aligned to 2 * element_size">; 624 625// AArch64 2023 Architecture Extensions (v9.5-A) 626 627def FeatureCPA : SubtargetFeature<"cpa", "HasCPA", "true", 628 "Enable Armv9.5-A Checked Pointer Arithmetic (FEAT_CPA)">; 629 630def FeaturePAuthLR : SubtargetFeature<"pauth-lr", "HasPAuthLR", 631 "true", "Enable Armv9.5-A PAC enhancements (FEAT_PAuth_LR)">; 632 633def FeatureTLBIW : SubtargetFeature<"tlbiw", "HasTLBIW", "true", 634 "Enable ARMv9.5-A TLBI VMALL for Dirty State (FEAT_TLBIW)">; 635 636//===----------------------------------------------------------------------===// 637// Architectures. 638// 639def HasV8_0aOps : SubtargetFeature<"v8a", "HasV8_0aOps", "true", 640 "Support ARM v8.0a instructions", [FeatureEL2VMSA, FeatureEL3]>; 641 642def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", 643 "Support ARM v8.1a instructions", [HasV8_0aOps, FeatureCRC, FeatureLSE, 644 FeatureRDM, FeaturePAN, FeatureLOR, FeatureVH]>; 645 646def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true", 647 "Support ARM v8.2a instructions", [HasV8_1aOps, FeaturePsUAO, 648 FeaturePAN_RWV, FeatureRAS, FeatureCCPP]>; 649 650def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true", 651 "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC, FeaturePAuth, 652 FeatureJS, FeatureCCIDX, FeatureComplxNum]>; 653 654def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", 655 "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd, 656 FeatureNV, FeatureMPAM, FeatureDIT, 657 FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeatureTLB_RMI, 658 FeatureFlagM, FeatureRCPC_IMMO, FeatureLSE2]>; 659 660def HasV8_5aOps : SubtargetFeature< 661 "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions", 662 [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict, 663 FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist, 664 FeatureBranchTargetId]>; 665 666def HasV8_6aOps : SubtargetFeature< 667 "v8.6a", "HasV8_6aOps", "true", "Support ARM v8.6a instructions", 668 [HasV8_5aOps, FeatureAMVS, FeatureBF16, FeatureFineGrainedTraps, 669 FeatureEnhancedCounterVirtualization, FeatureMatMulInt8]>; 670 671def HasV8_7aOps : SubtargetFeature< 672 "v8.7a", "HasV8_7aOps", "true", "Support ARM v8.7a instructions", 673 [HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX]>; 674 675def HasV8_8aOps : SubtargetFeature< 676 "v8.8a", "HasV8_8aOps", "true", "Support ARM v8.8a instructions", 677 [HasV8_7aOps, FeatureHBC, FeatureMOPS, FeatureNMI]>; 678 679def HasV8_9aOps : SubtargetFeature< 680 "v8.9a", "HasV8_9aOps", "true", "Support ARM v8.9a instructions", 681 [HasV8_8aOps, FeatureCLRBHB, FeaturePRFM_SLC, FeatureSPECRES2, 682 FeatureCSSC, FeatureRASv2, FeatureCHK]>; 683 684def HasV9_0aOps : SubtargetFeature< 685 "v9a", "HasV9_0aOps", "true", "Support ARM v9a instructions", 686 [HasV8_5aOps, FeatureMEC, FeatureSVE2]>; 687 688def HasV9_1aOps : SubtargetFeature< 689 "v9.1a", "HasV9_1aOps", "true", "Support ARM v9.1a instructions", 690 [HasV8_6aOps, HasV9_0aOps]>; 691 692def HasV9_2aOps : SubtargetFeature< 693 "v9.2a", "HasV9_2aOps", "true", "Support ARM v9.2a instructions", 694 [HasV8_7aOps, HasV9_1aOps]>; 695 696def HasV9_3aOps : SubtargetFeature< 697 "v9.3a", "HasV9_3aOps", "true", "Support ARM v9.3a instructions", 698 [HasV8_8aOps, HasV9_2aOps]>; 699 700def HasV9_4aOps : SubtargetFeature< 701 "v9.4a", "HasV9_4aOps", "true", "Support ARM v9.4a instructions", 702 [HasV8_9aOps, HasV9_3aOps]>; 703 704def HasV9_5aOps : SubtargetFeature< 705 "v9.5a", "HasV9_5aOps", "true", "Support ARM v9.5a instructions", 706 [HasV9_4aOps, FeatureCPA]>; 707 708def HasV8_0rOps : SubtargetFeature< 709 "v8r", "HasV8_0rOps", "true", "Support ARM v8r instructions", 710 [//v8.1 711 FeatureCRC, FeaturePAN, FeatureRDM, FeatureLSE, FeatureCONTEXTIDREL2, 712 //v8.2 713 FeatureRAS, FeaturePsUAO, FeatureCCPP, FeaturePAN_RWV, 714 //v8.3 715 FeatureComplxNum, FeatureCCIDX, FeatureJS, 716 FeaturePAuth, FeatureRCPC, 717 //v8.4 718 FeatureDotProd, FeatureTRACEV8_4, FeatureTLB_RMI, 719 FeatureFlagM, FeatureDIT, FeatureSEL2, FeatureRCPC_IMMO, 720 // Not mandatory in v8.0-R, but included here on the grounds that it 721 // only enables names of system registers 722 FeatureSpecRestrict 723 ]>; 724 725// Only intended to be used by disassemblers. 726def FeatureAll 727 : SubtargetFeature<"all", "IsAll", "true", "Enable all instructions", []>; 728 729class AssemblerPredicateWithAll<dag cond, string name=""> 730 : AssemblerPredicate<(any_of FeatureAll, cond), name>; 731 732//===----------------------------------------------------------------------===// 733// Register File Description 734//===----------------------------------------------------------------------===// 735 736include "AArch64RegisterInfo.td" 737include "AArch64RegisterBanks.td" 738include "AArch64CallingConvention.td" 739 740//===----------------------------------------------------------------------===// 741// Instruction Descriptions 742//===----------------------------------------------------------------------===// 743 744include "AArch64Schedule.td" 745include "AArch64InstrInfo.td" 746include "AArch64SchedPredicates.td" 747include "AArch64SchedPredExynos.td" 748include "AArch64SchedPredNeoverse.td" 749include "AArch64Combine.td" 750 751def AArch64InstrInfo : InstrInfo; 752 753//===----------------------------------------------------------------------===// 754// Named operands for MRS/MSR/TLBI/... 755//===----------------------------------------------------------------------===// 756 757include "AArch64SystemOperands.td" 758 759//===----------------------------------------------------------------------===// 760// Access to privileged registers 761//===----------------------------------------------------------------------===// 762 763foreach i = 1-3 in 764def FeatureUseEL#i#ForTP : SubtargetFeature<"tpidr-el"#i, "UseEL"#i#"ForTP", 765 "true", "Permit use of TPIDR_EL"#i#" for the TLS base">; 766def FeatureUseROEL0ForTP : SubtargetFeature<"tpidrro-el0", "UseROEL0ForTP", 767 "true", "Permit use of TPIDRRO_EL0 for the TLS base">; 768 769//===----------------------------------------------------------------------===// 770// Control codegen mitigation against Straight Line Speculation vulnerability. 771//===----------------------------------------------------------------------===// 772 773def FeatureHardenSlsRetBr : SubtargetFeature<"harden-sls-retbr", 774 "HardenSlsRetBr", "true", 775 "Harden against straight line speculation across RET and BR instructions">; 776def FeatureHardenSlsBlr : SubtargetFeature<"harden-sls-blr", 777 "HardenSlsBlr", "true", 778 "Harden against straight line speculation across BLR instructions">; 779def FeatureHardenSlsNoComdat : SubtargetFeature<"harden-sls-nocomdat", 780 "HardenSlsNoComdat", "true", 781 "Generate thunk code for SLS mitigation in the normal text section">; 782 783//===----------------------------------------------------------------------===// 784// AArch64 Processors supported. 785// 786 787//===----------------------------------------------------------------------===// 788// Unsupported features to disable for scheduling models 789//===----------------------------------------------------------------------===// 790 791class AArch64Unsupported { list<Predicate> F; } 792 793let F = [HasSVE2p1, HasSVE2p1_or_HasSME2, HasSVE2p1_or_HasSME2p1] in 794def SVE2p1Unsupported : AArch64Unsupported; 795 796def SVE2Unsupported : AArch64Unsupported { 797 let F = !listconcat([HasSVE2, HasSVE2orSME, HasSVE2orSME2, HasSSVE_FP8FMA, HasSMEF8F16, 798 HasSMEF8F32, HasSVE2AES, HasSVE2SHA3, HasSVE2SM4, HasSVE2BitPerm], 799 SVE2p1Unsupported.F); 800} 801 802def SVEUnsupported : AArch64Unsupported { 803 let F = !listconcat([HasSVE, HasSVEorSME], 804 SVE2Unsupported.F); 805} 806 807let F = [HasSME2p1, HasSVE2p1_or_HasSME2p1] in 808def SME2p1Unsupported : AArch64Unsupported; 809 810def SME2Unsupported : AArch64Unsupported { 811 let F = !listconcat([HasSME2, HasSVE2orSME2, HasSVE2p1_or_HasSME2, HasSSVE_FP8FMA, 812 HasSMEF8F16, HasSMEF8F32], 813 SME2p1Unsupported.F); 814} 815 816def SMEUnsupported : AArch64Unsupported { 817 let F = !listconcat([HasSME, HasSMEI16I64, HasSMEF16F16, HasSMEF64F64, HasSMEFA64], 818 SME2Unsupported.F); 819} 820 821let F = [HasPAuth, HasPAuthLR] in 822def PAUnsupported : AArch64Unsupported; 823 824include "AArch64SchedA53.td" 825include "AArch64SchedA55.td" 826include "AArch64SchedA510.td" 827include "AArch64SchedA57.td" 828include "AArch64SchedCyclone.td" 829include "AArch64SchedFalkor.td" 830include "AArch64SchedKryo.td" 831include "AArch64SchedExynosM3.td" 832include "AArch64SchedExynosM4.td" 833include "AArch64SchedExynosM5.td" 834include "AArch64SchedThunderX.td" 835include "AArch64SchedThunderX2T99.td" 836include "AArch64SchedA64FX.td" 837include "AArch64SchedThunderX3T110.td" 838include "AArch64SchedTSV110.td" 839include "AArch64SchedAmpere1.td" 840include "AArch64SchedAmpere1B.td" 841include "AArch64SchedNeoverseN1.td" 842include "AArch64SchedNeoverseN2.td" 843include "AArch64SchedNeoverseV1.td" 844include "AArch64SchedNeoverseV2.td" 845 846def TuneA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35", 847 "Cortex-A35 ARM processors">; 848 849def TuneA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", 850 "Cortex-A53 ARM processors", [ 851 FeatureFuseAES, 852 FeatureFuseAdrpAdd, 853 FeatureBalanceFPOps, 854 FeaturePostRAScheduler]>; 855 856def TuneA55 : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55", 857 "Cortex-A55 ARM processors", [ 858 FeatureFuseAES, 859 FeatureFuseAdrpAdd, 860 FeaturePostRAScheduler, 861 FeatureFuseAddress]>; 862 863def TuneA510 : SubtargetFeature<"a510", "ARMProcFamily", "CortexA510", 864 "Cortex-A510 ARM processors", [ 865 FeatureFuseAES, 866 FeatureFuseAdrpAdd, 867 FeaturePostRAScheduler 868 ]>; 869 870def TuneA520 : SubtargetFeature<"a520", "ARMProcFamily", "CortexA520", 871 "Cortex-A520 ARM processors", [ 872 FeatureFuseAES, 873 FeatureFuseAdrpAdd, 874 FeaturePostRAScheduler]>; 875 876def TuneA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", 877 "Cortex-A57 ARM processors", [ 878 FeatureFuseAES, 879 FeatureBalanceFPOps, 880 FeatureFuseAdrpAdd, 881 FeatureFuseLiterals, 882 FeaturePostRAScheduler, 883 FeatureEnableSelectOptimize, 884 FeaturePredictableSelectIsExpensive]>; 885 886def TuneA65 : SubtargetFeature<"a65", "ARMProcFamily", "CortexA65", 887 "Cortex-A65 ARM processors", [ 888 FeatureFuseAES, 889 FeatureFuseAddress, 890 FeatureFuseAdrpAdd, 891 FeatureFuseLiterals, 892 FeatureEnableSelectOptimize, 893 FeaturePredictableSelectIsExpensive]>; 894 895def TuneA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72", 896 "Cortex-A72 ARM processors", [ 897 FeatureFuseAES, 898 FeatureFuseAdrpAdd, 899 FeatureFuseLiterals, 900 FeatureEnableSelectOptimize, 901 FeaturePredictableSelectIsExpensive]>; 902 903def TuneA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73", 904 "Cortex-A73 ARM processors", [ 905 FeatureFuseAES, 906 FeatureFuseAdrpAdd, 907 FeatureEnableSelectOptimize, 908 FeaturePredictableSelectIsExpensive]>; 909 910def TuneA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75", 911 "Cortex-A75 ARM processors", [ 912 FeatureFuseAES, 913 FeatureFuseAdrpAdd, 914 FeatureEnableSelectOptimize, 915 FeaturePredictableSelectIsExpensive]>; 916 917def TuneA76 : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76", 918 "Cortex-A76 ARM processors", [ 919 FeatureFuseAES, 920 FeatureFuseAdrpAdd, 921 FeatureAddrLSLFast, 922 FeatureALULSLFast, 923 FeatureEnableSelectOptimize, 924 FeaturePredictableSelectIsExpensive]>; 925 926def TuneA77 : SubtargetFeature<"a77", "ARMProcFamily", "CortexA77", 927 "Cortex-A77 ARM processors", [ 928 FeatureCmpBccFusion, 929 FeatureFuseAES, 930 FeatureFuseAdrpAdd, 931 FeatureAddrLSLFast, 932 FeatureALULSLFast, 933 FeatureEnableSelectOptimize, 934 FeaturePredictableSelectIsExpensive]>; 935 936def TuneA78 : SubtargetFeature<"a78", "ARMProcFamily", "CortexA78", 937 "Cortex-A78 ARM processors", [ 938 FeatureCmpBccFusion, 939 FeatureFuseAES, 940 FeatureFuseAdrpAdd, 941 FeatureAddrLSLFast, 942 FeatureALULSLFast, 943 FeaturePostRAScheduler, 944 FeatureEnableSelectOptimize, 945 FeaturePredictableSelectIsExpensive]>; 946 947def TuneA78C : SubtargetFeature<"a78c", "ARMProcFamily", 948 "CortexA78C", 949 "Cortex-A78C ARM processors", [ 950 FeatureCmpBccFusion, 951 FeatureFuseAES, 952 FeatureFuseAdrpAdd, 953 FeatureAddrLSLFast, 954 FeatureALULSLFast, 955 FeaturePostRAScheduler, 956 FeatureEnableSelectOptimize, 957 FeaturePredictableSelectIsExpensive]>; 958 959def TuneA710 : SubtargetFeature<"a710", "ARMProcFamily", "CortexA710", 960 "Cortex-A710 ARM processors", [ 961 FeatureCmpBccFusion, 962 FeatureFuseAES, 963 FeatureFuseAdrpAdd, 964 FeatureAddrLSLFast, 965 FeatureALULSLFast, 966 FeaturePostRAScheduler, 967 FeatureEnableSelectOptimize, 968 FeaturePredictableSelectIsExpensive]>; 969 970def TuneA715 : SubtargetFeature<"a715", "ARMProcFamily", "CortexA715", 971 "Cortex-A715 ARM processors", [ 972 FeatureFuseAES, 973 FeaturePostRAScheduler, 974 FeatureCmpBccFusion, 975 FeatureAddrLSLFast, 976 FeatureALULSLFast, 977 FeatureFuseAdrpAdd, 978 FeatureEnableSelectOptimize, 979 FeaturePredictableSelectIsExpensive]>; 980 981def TuneA720 : SubtargetFeature<"a720", "ARMProcFamily", "CortexA720", 982 "Cortex-A720 ARM processors", [ 983 FeatureFuseAES, 984 FeaturePostRAScheduler, 985 FeatureCmpBccFusion, 986 FeatureAddrLSLFast, 987 FeatureALULSLFast, 988 FeatureFuseAdrpAdd, 989 FeatureEnableSelectOptimize, 990 FeaturePredictableSelectIsExpensive]>; 991 992def TuneR82 : SubtargetFeature<"cortex-r82", "ARMProcFamily", 993 "CortexR82", 994 "Cortex-R82 ARM processors", [ 995 FeaturePostRAScheduler]>; 996 997def TuneX1 : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1", 998 "Cortex-X1 ARM processors", [ 999 FeatureCmpBccFusion, 1000 FeatureFuseAES, 1001 FeatureFuseAdrpAdd, 1002 FeatureAddrLSLFast, 1003 FeatureALULSLFast, 1004 FeaturePostRAScheduler, 1005 FeatureEnableSelectOptimize, 1006 FeaturePredictableSelectIsExpensive]>; 1007 1008def TuneX2 : SubtargetFeature<"cortex-x2", "ARMProcFamily", "CortexX2", 1009 "Cortex-X2 ARM processors", [ 1010 FeatureCmpBccFusion, 1011 FeatureFuseAES, 1012 FeatureFuseAdrpAdd, 1013 FeatureAddrLSLFast, 1014 FeatureALULSLFast, 1015 FeaturePostRAScheduler, 1016 FeatureEnableSelectOptimize, 1017 FeaturePredictableSelectIsExpensive]>; 1018 1019def TuneX3 : SubtargetFeature<"cortex-x3", "ARMProcFamily", "CortexX3", 1020 "Cortex-X3 ARM processors", [ 1021 FeatureAddrLSLFast, 1022 FeatureALULSLFast, 1023 FeatureFuseAdrpAdd, 1024 FeatureFuseAES, 1025 FeaturePostRAScheduler, 1026 FeatureEnableSelectOptimize, 1027 FeaturePredictableSelectIsExpensive]>; 1028 1029def TuneX4 : SubtargetFeature<"cortex-x4", "ARMProcFamily", "CortexX4", 1030 "Cortex-X4 ARM processors", [ 1031 FeatureAddrLSLFast, 1032 FeatureALULSLFast, 1033 FeatureFuseAdrpAdd, 1034 FeatureFuseAES, 1035 FeaturePostRAScheduler, 1036 FeatureEnableSelectOptimize, 1037 FeaturePredictableSelectIsExpensive]>; 1038 1039def TuneA64FX : SubtargetFeature<"a64fx", "ARMProcFamily", "A64FX", 1040 "Fujitsu A64FX processors", [ 1041 FeaturePostRAScheduler, 1042 FeatureAggressiveFMA, 1043 FeatureArithmeticBccFusion, 1044 FeatureStorePairSuppress, 1045 FeaturePredictableSelectIsExpensive]>; 1046 1047def TuneCarmel : SubtargetFeature<"carmel", "ARMProcFamily", "Carmel", 1048 "Nvidia Carmel processors">; 1049 1050// Note that cyclone does not fuse AES instructions, but newer apple chips do 1051// perform the fusion and cyclone is used by default when targetting apple OSes. 1052def TuneAppleA7 : SubtargetFeature<"apple-a7", "ARMProcFamily", "AppleA7", 1053 "Apple A7 (the CPU formerly known as Cyclone)", [ 1054 FeatureAlternateSExtLoadCVTF32Pattern, 1055 FeatureArithmeticBccFusion, 1056 FeatureArithmeticCbzFusion, 1057 FeatureDisableLatencySchedHeuristic, 1058 FeatureFuseAES, FeatureFuseCryptoEOR, 1059 FeatureStorePairSuppress, 1060 FeatureZCRegMove, 1061 FeatureZCZeroing, 1062 FeatureZCZeroingFPWorkaround]>; 1063 1064def TuneAppleA10 : SubtargetFeature<"apple-a10", "ARMProcFamily", "AppleA10", 1065 "Apple A10", [ 1066 FeatureAlternateSExtLoadCVTF32Pattern, 1067 FeatureArithmeticBccFusion, 1068 FeatureArithmeticCbzFusion, 1069 FeatureDisableLatencySchedHeuristic, 1070 FeatureFuseAES, 1071 FeatureFuseCryptoEOR, 1072 FeatureStorePairSuppress, 1073 FeatureZCRegMove, 1074 FeatureZCZeroing]>; 1075 1076def TuneAppleA11 : SubtargetFeature<"apple-a11", "ARMProcFamily", "AppleA11", 1077 "Apple A11", [ 1078 FeatureAlternateSExtLoadCVTF32Pattern, 1079 FeatureArithmeticBccFusion, 1080 FeatureArithmeticCbzFusion, 1081 FeatureDisableLatencySchedHeuristic, 1082 FeatureFuseAES, 1083 FeatureFuseCryptoEOR, 1084 FeatureStorePairSuppress, 1085 FeatureZCRegMove, 1086 FeatureZCZeroing]>; 1087 1088def TuneAppleA12 : SubtargetFeature<"apple-a12", "ARMProcFamily", "AppleA12", 1089 "Apple A12", [ 1090 FeatureAlternateSExtLoadCVTF32Pattern, 1091 FeatureArithmeticBccFusion, 1092 FeatureArithmeticCbzFusion, 1093 FeatureDisableLatencySchedHeuristic, 1094 FeatureFuseAES, 1095 FeatureFuseCryptoEOR, 1096 FeatureStorePairSuppress, 1097 FeatureZCRegMove, 1098 FeatureZCZeroing]>; 1099 1100def TuneAppleA13 : SubtargetFeature<"apple-a13", "ARMProcFamily", "AppleA13", 1101 "Apple A13", [ 1102 FeatureAlternateSExtLoadCVTF32Pattern, 1103 FeatureArithmeticBccFusion, 1104 FeatureArithmeticCbzFusion, 1105 FeatureDisableLatencySchedHeuristic, 1106 FeatureFuseAES, 1107 FeatureFuseCryptoEOR, 1108 FeatureStorePairSuppress, 1109 FeatureZCRegMove, 1110 FeatureZCZeroing]>; 1111 1112def TuneAppleA14 : SubtargetFeature<"apple-a14", "ARMProcFamily", "AppleA14", 1113 "Apple A14", [ 1114 FeatureAggressiveFMA, 1115 FeatureAlternateSExtLoadCVTF32Pattern, 1116 FeatureArithmeticBccFusion, 1117 FeatureArithmeticCbzFusion, 1118 FeatureDisableLatencySchedHeuristic, 1119 FeatureFuseAddress, 1120 FeatureFuseAES, 1121 FeatureFuseArithmeticLogic, 1122 FeatureFuseCCSelect, 1123 FeatureFuseCryptoEOR, 1124 FeatureFuseAdrpAdd, 1125 FeatureFuseLiterals, 1126 FeatureStorePairSuppress, 1127 FeatureZCRegMove, 1128 FeatureZCZeroing]>; 1129 1130def TuneAppleA15 : SubtargetFeature<"apple-a15", "ARMProcFamily", "AppleA15", 1131 "Apple A15", [ 1132 FeatureAlternateSExtLoadCVTF32Pattern, 1133 FeatureArithmeticBccFusion, 1134 FeatureArithmeticCbzFusion, 1135 FeatureDisableLatencySchedHeuristic, 1136 FeatureFuseAddress, 1137 FeatureFuseAES, 1138 FeatureFuseArithmeticLogic, 1139 FeatureFuseCCSelect, 1140 FeatureFuseCryptoEOR, 1141 FeatureFuseLiterals, 1142 FeatureStorePairSuppress, 1143 FeatureZCRegMove, 1144 FeatureZCZeroing]>; 1145 1146def TuneAppleA16 : SubtargetFeature<"apple-a16", "ARMProcFamily", "AppleA16", 1147 "Apple A16", [ 1148 FeatureAlternateSExtLoadCVTF32Pattern, 1149 FeatureArithmeticBccFusion, 1150 FeatureArithmeticCbzFusion, 1151 FeatureDisableLatencySchedHeuristic, 1152 FeatureFuseAddress, 1153 FeatureFuseAES, 1154 FeatureFuseArithmeticLogic, 1155 FeatureFuseCCSelect, 1156 FeatureFuseCryptoEOR, 1157 FeatureFuseLiterals, 1158 FeatureStorePairSuppress, 1159 FeatureZCRegMove, 1160 FeatureZCZeroing]>; 1161 1162def TuneAppleA17 : SubtargetFeature<"apple-a17", "ARMProcFamily", "AppleA17", 1163 "Apple A17", [ 1164 FeatureAlternateSExtLoadCVTF32Pattern, 1165 FeatureArithmeticBccFusion, 1166 FeatureArithmeticCbzFusion, 1167 FeatureDisableLatencySchedHeuristic, 1168 FeatureFuseAddress, 1169 FeatureFuseAES, 1170 FeatureFuseArithmeticLogic, 1171 FeatureFuseCCSelect, 1172 FeatureFuseCryptoEOR, 1173 FeatureFuseLiterals, 1174 FeatureStorePairSuppress, 1175 FeatureZCRegMove, 1176 FeatureZCZeroing]>; 1177 1178def TuneExynosM3 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3", 1179 "Samsung Exynos-M3 processors", 1180 [FeatureExynosCheapAsMoveHandling, 1181 FeatureForce32BitJumpTables, 1182 FeatureFuseAddress, 1183 FeatureFuseAES, 1184 FeatureFuseCCSelect, 1185 FeatureFuseAdrpAdd, 1186 FeatureFuseLiterals, 1187 FeatureStorePairSuppress, 1188 FeatureAddrLSLFast, 1189 FeatureALULSLFast, 1190 FeaturePostRAScheduler, 1191 FeaturePredictableSelectIsExpensive]>; 1192 1193// Re-uses some scheduling and tunings from the ExynosM3 proc family. 1194def TuneExynosM4 : SubtargetFeature<"exynosm4", "ARMProcFamily", "ExynosM3", 1195 "Samsung Exynos-M4 processors", 1196 [FeatureArithmeticBccFusion, 1197 FeatureArithmeticCbzFusion, 1198 FeatureExynosCheapAsMoveHandling, 1199 FeatureForce32BitJumpTables, 1200 FeatureFuseAddress, 1201 FeatureFuseAES, 1202 FeatureFuseArithmeticLogic, 1203 FeatureFuseCCSelect, 1204 FeatureFuseAdrpAdd, 1205 FeatureFuseLiterals, 1206 FeatureStorePairSuppress, 1207 FeatureAddrLSLFast, 1208 FeatureALULSLFast, 1209 FeaturePostRAScheduler, 1210 FeatureZCZeroing]>; 1211 1212def TuneKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo", 1213 "Qualcomm Kryo processors", [ 1214 FeaturePostRAScheduler, 1215 FeaturePredictableSelectIsExpensive, 1216 FeatureZCZeroing, 1217 FeatureAddrLSLFast, 1218 FeatureALULSLFast, 1219 FeatureStorePairSuppress]>; 1220 1221def TuneFalkor : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor", 1222 "Qualcomm Falkor processors", [ 1223 FeaturePostRAScheduler, 1224 FeaturePredictableSelectIsExpensive, 1225 FeatureZCZeroing, 1226 FeatureStorePairSuppress, 1227 FeatureAddrLSLFast, 1228 FeatureALULSLFast, 1229 FeatureSlowSTRQro]>; 1230 1231def TuneNeoverseE1 : SubtargetFeature<"neoversee1", "ARMProcFamily", "NeoverseE1", 1232 "Neoverse E1 ARM processors", [ 1233 FeatureFuseAES, 1234 FeatureFuseAdrpAdd, 1235 FeaturePostRAScheduler]>; 1236 1237def TuneNeoverseN1 : SubtargetFeature<"neoversen1", "ARMProcFamily", "NeoverseN1", 1238 "Neoverse N1 ARM processors", [ 1239 FeatureFuseAES, 1240 FeatureFuseAdrpAdd, 1241 FeatureAddrLSLFast, 1242 FeatureALULSLFast, 1243 FeaturePostRAScheduler, 1244 FeatureEnableSelectOptimize, 1245 FeaturePredictableSelectIsExpensive]>; 1246 1247def TuneNeoverseN2 : SubtargetFeature<"neoversen2", "ARMProcFamily", "NeoverseN2", 1248 "Neoverse N2 ARM processors", [ 1249 FeatureFuseAES, 1250 FeatureFuseAdrpAdd, 1251 FeatureAddrLSLFast, 1252 FeatureALULSLFast, 1253 FeaturePostRAScheduler, 1254 FeatureEnableSelectOptimize, 1255 FeaturePredictableSelectIsExpensive]>; 1256 1257def TuneNeoverse512TVB : SubtargetFeature<"neoverse512tvb", "ARMProcFamily", "Neoverse512TVB", 1258 "Neoverse 512-TVB ARM processors", [ 1259 FeatureFuseAES, 1260 FeatureFuseAdrpAdd, 1261 FeatureAddrLSLFast, 1262 FeatureALULSLFast, 1263 FeaturePostRAScheduler, 1264 FeatureEnableSelectOptimize, 1265 FeaturePredictableSelectIsExpensive]>; 1266 1267def TuneNeoverseV1 : SubtargetFeature<"neoversev1", "ARMProcFamily", "NeoverseV1", 1268 "Neoverse V1 ARM processors", [ 1269 FeatureFuseAES, 1270 FeatureFuseAdrpAdd, 1271 FeatureAddrLSLFast, 1272 FeatureALULSLFast, 1273 FeaturePostRAScheduler, 1274 FeatureEnableSelectOptimize, 1275 FeaturePredictableSelectIsExpensive, 1276 FeatureNoSVEFPLD1R]>; 1277 1278def TuneNeoverseV2 : SubtargetFeature<"neoversev2", "ARMProcFamily", "NeoverseV2", 1279 "Neoverse V2 ARM processors", [ 1280 FeatureFuseAES, 1281 FeatureFuseAdrpAdd, 1282 FeatureAddrLSLFast, 1283 FeatureALULSLFast, 1284 FeaturePostRAScheduler, 1285 FeatureEnableSelectOptimize, 1286 FeaturePredictableSelectIsExpensive]>; 1287 1288def TuneSaphira : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira", 1289 "Qualcomm Saphira processors", [ 1290 FeaturePostRAScheduler, 1291 FeaturePredictableSelectIsExpensive, 1292 FeatureZCZeroing, 1293 FeatureStorePairSuppress, 1294 FeatureAddrLSLFast, 1295 FeatureALULSLFast]>; 1296 1297def TuneThunderX2T99 : SubtargetFeature<"thunderx2t99", "ARMProcFamily", "ThunderX2T99", 1298 "Cavium ThunderX2 processors", [ 1299 FeatureAggressiveFMA, 1300 FeatureArithmeticBccFusion, 1301 FeaturePostRAScheduler, 1302 FeatureStorePairSuppress, 1303 FeaturePredictableSelectIsExpensive]>; 1304 1305def TuneThunderX3T110 : SubtargetFeature<"thunderx3t110", "ARMProcFamily", 1306 "ThunderX3T110", 1307 "Marvell ThunderX3 processors", [ 1308 FeatureAggressiveFMA, 1309 FeatureArithmeticBccFusion, 1310 FeaturePostRAScheduler, 1311 FeaturePredictableSelectIsExpensive, 1312 FeatureBalanceFPOps, 1313 FeatureStorePairSuppress, 1314 FeatureStrictAlign]>; 1315 1316def TuneThunderX : SubtargetFeature<"thunderx", "ARMProcFamily", "ThunderX", 1317 "Cavium ThunderX processors", [ 1318 FeaturePostRAScheduler, 1319 FeatureStorePairSuppress, 1320 FeaturePredictableSelectIsExpensive]>; 1321 1322def TuneThunderXT88 : SubtargetFeature<"thunderxt88", "ARMProcFamily", 1323 "ThunderXT88", 1324 "Cavium ThunderX processors", [ 1325 FeaturePostRAScheduler, 1326 FeatureStorePairSuppress, 1327 FeaturePredictableSelectIsExpensive]>; 1328 1329def TuneThunderXT81 : SubtargetFeature<"thunderxt81", "ARMProcFamily", 1330 "ThunderXT81", 1331 "Cavium ThunderX processors", [ 1332 FeaturePostRAScheduler, 1333 FeatureStorePairSuppress, 1334 FeaturePredictableSelectIsExpensive]>; 1335 1336def TuneThunderXT83 : SubtargetFeature<"thunderxt83", "ARMProcFamily", 1337 "ThunderXT83", 1338 "Cavium ThunderX processors", [ 1339 FeaturePostRAScheduler, 1340 FeatureStorePairSuppress, 1341 FeaturePredictableSelectIsExpensive]>; 1342 1343def TuneTSV110 : SubtargetFeature<"tsv110", "ARMProcFamily", "TSV110", 1344 "HiSilicon TS-V110 processors", [ 1345 FeatureFuseAES, 1346 FeatureStorePairSuppress, 1347 FeaturePostRAScheduler]>; 1348 1349def TuneAmpere1 : SubtargetFeature<"ampere1", "ARMProcFamily", "Ampere1", 1350 "Ampere Computing Ampere-1 processors", [ 1351 FeaturePostRAScheduler, 1352 FeatureFuseAES, 1353 FeatureAddrLSLFast, 1354 FeatureALULSLFast, 1355 FeatureAggressiveFMA, 1356 FeatureArithmeticBccFusion, 1357 FeatureCmpBccFusion, 1358 FeatureFuseAddress, 1359 FeatureFuseLiterals, 1360 FeatureStorePairSuppress, 1361 FeatureLdpAlignedOnly, 1362 FeatureStpAlignedOnly]>; 1363 1364def TuneAmpere1A : SubtargetFeature<"ampere1a", "ARMProcFamily", "Ampere1A", 1365 "Ampere Computing Ampere-1A processors", [ 1366 FeaturePostRAScheduler, 1367 FeatureFuseAES, 1368 FeatureAddrLSLFast, 1369 FeatureALULSLFast, 1370 FeatureAggressiveFMA, 1371 FeatureArithmeticBccFusion, 1372 FeatureCmpBccFusion, 1373 FeatureFuseAddress, 1374 FeatureFuseLiterals, 1375 FeatureFuseLiterals, 1376 FeatureStorePairSuppress, 1377 FeatureLdpAlignedOnly, 1378 FeatureStpAlignedOnly]>; 1379 1380def TuneAmpere1B : SubtargetFeature<"ampere1b", "ARMProcFamily", "Ampere1B", 1381 "Ampere Computing Ampere-1B processors", [ 1382 FeaturePostRAScheduler, 1383 FeatureFuseAES, 1384 FeatureFuseAdrpAdd, 1385 FeatureAddrLSLFast, 1386 FeatureALULSLFast, 1387 FeatureAggressiveFMA, 1388 FeatureArithmeticBccFusion, 1389 FeatureCmpBccFusion, 1390 FeatureFuseAddress, 1391 FeatureFuseLiterals, 1392 FeatureStorePairSuppress, 1393 FeatureEnableSelectOptimize, 1394 FeaturePredictableSelectIsExpensive, 1395 FeatureLdpAlignedOnly, 1396 FeatureStpAlignedOnly]>; 1397 1398def ProcessorFeatures { 1399 list<SubtargetFeature> A53 = [HasV8_0aOps, FeatureCRC, FeatureCrypto, 1400 FeatureFPARMv8, FeatureNEON, FeaturePerfMon]; 1401 list<SubtargetFeature> A55 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1402 FeatureNEON, FeatureFullFP16, FeatureDotProd, 1403 FeatureRCPC, FeaturePerfMon]; 1404 list<SubtargetFeature> A510 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon, 1405 FeatureMatMulInt8, FeatureBF16, FeatureAM, 1406 FeatureMTE, FeatureETE, FeatureSVE2BitPerm, 1407 FeatureFP16FML]; 1408 list<SubtargetFeature> A520 = [HasV9_2aOps, FeaturePerfMon, FeatureAM, 1409 FeatureMTE, FeatureETE, FeatureSVE2BitPerm, 1410 FeatureFP16FML]; 1411 list<SubtargetFeature> A65 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1412 FeatureNEON, FeatureFullFP16, FeatureDotProd, 1413 FeatureRCPC, FeatureSSBS, FeatureRAS, 1414 FeaturePerfMon]; 1415 list<SubtargetFeature> A76 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1416 FeatureNEON, FeatureFullFP16, FeatureDotProd, 1417 FeatureRCPC, FeatureSSBS, FeaturePerfMon]; 1418 list<SubtargetFeature> A77 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1419 FeatureNEON, FeatureFullFP16, FeatureDotProd, 1420 FeatureRCPC, FeaturePerfMon, FeatureSSBS]; 1421 list<SubtargetFeature> A78 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1422 FeatureNEON, FeatureFullFP16, FeatureDotProd, 1423 FeatureRCPC, FeaturePerfMon, FeatureSPE, 1424 FeatureSSBS]; 1425 list<SubtargetFeature> A78C = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1426 FeatureNEON, FeatureFullFP16, FeatureDotProd, 1427 FeatureFlagM, FeaturePAuth, 1428 FeaturePerfMon, FeatureRCPC, FeatureSPE, 1429 FeatureSSBS]; 1430 list<SubtargetFeature> A710 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon, 1431 FeatureETE, FeatureMTE, FeatureFP16FML, 1432 FeatureSVE2BitPerm, FeatureBF16, FeatureMatMulInt8]; 1433 list<SubtargetFeature> A715 = [HasV9_0aOps, FeatureNEON, FeatureMTE, 1434 FeatureFP16FML, FeatureSVE, FeatureTRBE, 1435 FeatureSVE2BitPerm, FeatureBF16, FeatureETE, 1436 FeaturePerfMon, FeatureMatMulInt8, FeatureSPE]; 1437 list<SubtargetFeature> A720 = [HasV9_2aOps, FeatureMTE, FeatureFP16FML, 1438 FeatureTRBE, FeatureSVE2BitPerm, FeatureETE, 1439 FeaturePerfMon, FeatureSPE, FeatureSPE_EEF]; 1440 list<SubtargetFeature> R82 = [HasV8_0rOps, FeaturePerfMon, FeatureFullFP16, 1441 FeatureFP16FML, FeatureSSBS, FeaturePredRes, 1442 FeatureSB]; 1443 list<SubtargetFeature> X1 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1444 FeatureNEON, FeatureRCPC, FeaturePerfMon, 1445 FeatureSPE, FeatureFullFP16, FeatureDotProd, 1446 FeatureSSBS]; 1447 list<SubtargetFeature> X1C = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1448 FeatureNEON, FeatureRCPC_IMMO, FeaturePerfMon, 1449 FeatureSPE, FeatureFullFP16, FeatureDotProd, 1450 FeaturePAuth, FeatureSSBS, FeatureFlagM, 1451 FeatureLSE2]; 1452 list<SubtargetFeature> X2 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon, 1453 FeatureMatMulInt8, FeatureBF16, FeatureAM, 1454 FeatureMTE, FeatureETE, FeatureSVE2BitPerm, 1455 FeatureFP16FML]; 1456 list<SubtargetFeature> X3 = [HasV9_0aOps, FeatureSVE, FeatureNEON, 1457 FeaturePerfMon, FeatureETE, FeatureTRBE, 1458 FeatureSPE, FeatureBF16, FeatureMatMulInt8, 1459 FeatureMTE, FeatureSVE2BitPerm, FeatureFullFP16, 1460 FeatureFP16FML]; 1461 list<SubtargetFeature> X4 = [HasV9_2aOps, 1462 FeaturePerfMon, FeatureETE, FeatureTRBE, 1463 FeatureSPE, FeatureMTE, FeatureSVE2BitPerm, 1464 FeatureFP16FML, FeatureSPE_EEF]; 1465 list<SubtargetFeature> A64FX = [HasV8_2aOps, FeatureFPARMv8, FeatureNEON, 1466 FeatureSHA2, FeaturePerfMon, FeatureFullFP16, 1467 FeatureSVE, FeatureComplxNum]; 1468 list<SubtargetFeature> Carmel = [HasV8_2aOps, FeatureNEON, FeatureCrypto, 1469 FeatureFullFP16]; 1470 list<SubtargetFeature> AppleA7 = [HasV8_0aOps, FeatureCrypto, FeatureFPARMv8, 1471 FeatureNEON,FeaturePerfMon, FeatureAppleA7SysReg]; 1472 list<SubtargetFeature> AppleA10 = [HasV8_0aOps, FeatureCrypto, FeatureFPARMv8, 1473 FeatureNEON, FeaturePerfMon, FeatureCRC, 1474 FeatureRDM, FeaturePAN, FeatureLOR, FeatureVH]; 1475 list<SubtargetFeature> AppleA11 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1476 FeatureNEON, FeaturePerfMon, FeatureFullFP16]; 1477 list<SubtargetFeature> AppleA12 = [HasV8_3aOps, FeatureCrypto, FeatureFPARMv8, 1478 FeatureNEON, FeaturePerfMon, FeatureFullFP16]; 1479 list<SubtargetFeature> AppleA13 = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8, 1480 FeatureNEON, FeaturePerfMon, FeatureFullFP16, 1481 FeatureFP16FML, FeatureSHA3]; 1482 list<SubtargetFeature> AppleA14 = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8, 1483 FeatureNEON, FeaturePerfMon, FeatureFRInt3264, 1484 FeatureSpecRestrict, FeatureSSBS, FeatureSB, 1485 FeaturePredRes, FeatureCacheDeepPersist, 1486 FeatureFullFP16, FeatureFP16FML, FeatureSHA3, 1487 FeatureAltFPCmp]; 1488 list<SubtargetFeature> AppleA15 = [HasV8_6aOps, FeatureCrypto, FeatureFPARMv8, 1489 FeatureNEON, FeaturePerfMon, FeatureSHA3, 1490 FeatureFullFP16, FeatureFP16FML]; 1491 list<SubtargetFeature> AppleA16 = [HasV8_6aOps, FeatureCrypto, FeatureFPARMv8, 1492 FeatureNEON, FeaturePerfMon, FeatureSHA3, 1493 FeatureFullFP16, FeatureFP16FML, 1494 FeatureHCX]; 1495 list<SubtargetFeature> AppleA17 = [HasV8_6aOps, FeatureCrypto, FeatureFPARMv8, 1496 FeatureNEON, FeaturePerfMon, FeatureSHA3, 1497 FeatureFullFP16, FeatureFP16FML, 1498 FeatureHCX]; 1499 list<SubtargetFeature> ExynosM3 = [HasV8_0aOps, FeatureCRC, FeatureCrypto, 1500 FeaturePerfMon]; 1501 list<SubtargetFeature> ExynosM4 = [HasV8_2aOps, FeatureCrypto, FeatureDotProd, 1502 FeatureFullFP16, FeaturePerfMon]; 1503 list<SubtargetFeature> Falkor = [HasV8_0aOps, FeatureCRC, FeatureCrypto, 1504 FeatureFPARMv8, FeatureNEON, FeaturePerfMon, 1505 FeatureRDM]; 1506 list<SubtargetFeature> NeoverseE1 = [HasV8_2aOps, FeatureCrypto, FeatureDotProd, 1507 FeatureFPARMv8, FeatureFullFP16, FeatureNEON, 1508 FeatureRCPC, FeatureSSBS, FeaturePerfMon]; 1509 list<SubtargetFeature> NeoverseN1 = [HasV8_2aOps, FeatureCrypto, FeatureDotProd, 1510 FeatureFPARMv8, FeatureFullFP16, FeatureNEON, 1511 FeatureRCPC, FeatureSPE, FeatureSSBS, 1512 FeaturePerfMon]; 1513 list<SubtargetFeature> NeoverseN2 = [HasV9_0aOps, FeatureBF16, FeatureETE, 1514 FeatureMatMulInt8, FeatureMTE, FeatureSVE2, 1515 FeatureSVE2BitPerm, FeatureTRBE, 1516 FeaturePerfMon]; 1517 list<SubtargetFeature> Neoverse512TVB = [HasV8_4aOps, FeatureBF16, FeatureCacheDeepPersist, 1518 FeatureCrypto, FeatureFPARMv8, FeatureFP16FML, 1519 FeatureFullFP16, FeatureMatMulInt8, FeatureNEON, 1520 FeaturePerfMon, FeatureRandGen, FeatureSPE, 1521 FeatureSSBS, FeatureSVE]; 1522 list<SubtargetFeature> NeoverseV1 = [HasV8_4aOps, FeatureBF16, FeatureCacheDeepPersist, 1523 FeatureCrypto, FeatureFPARMv8, FeatureFP16FML, 1524 FeatureFullFP16, FeatureMatMulInt8, FeatureNEON, 1525 FeaturePerfMon, FeatureRandGen, FeatureSPE, 1526 FeatureSSBS, FeatureSVE]; 1527 list<SubtargetFeature> NeoverseV2 = [HasV9_0aOps, FeatureBF16, FeatureSPE, 1528 FeaturePerfMon, FeatureETE, FeatureMatMulInt8, 1529 FeatureNEON, FeatureSVE2BitPerm, FeatureFP16FML, 1530 FeatureMTE, FeatureRandGen]; 1531 list<SubtargetFeature> Saphira = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8, 1532 FeatureNEON, FeatureSPE, FeaturePerfMon]; 1533 list<SubtargetFeature> ThunderX = [HasV8_0aOps, FeatureCRC, FeatureCrypto, 1534 FeatureFPARMv8, FeaturePerfMon, FeatureNEON]; 1535 list<SubtargetFeature> ThunderX2T99 = [HasV8_1aOps, FeatureCRC, FeatureCrypto, 1536 FeatureFPARMv8, FeatureNEON, FeatureLSE]; 1537 list<SubtargetFeature> ThunderX3T110 = [HasV8_3aOps, FeatureCRC, FeatureCrypto, 1538 FeatureFPARMv8, FeatureNEON, FeatureLSE, 1539 FeaturePAuth, FeaturePerfMon]; 1540 list<SubtargetFeature> TSV110 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1541 FeatureNEON, FeaturePerfMon, FeatureSPE, 1542 FeatureFullFP16, FeatureFP16FML, FeatureDotProd, 1543 FeatureJS, FeatureComplxNum]; 1544 list<SubtargetFeature> Ampere1 = [HasV8_6aOps, FeatureNEON, FeaturePerfMon, 1545 FeatureSSBS, FeatureRandGen, FeatureSB, 1546 FeatureSHA2, FeatureSHA3, FeatureAES]; 1547 list<SubtargetFeature> Ampere1A = [HasV8_6aOps, FeatureNEON, FeaturePerfMon, 1548 FeatureMTE, FeatureSSBS, FeatureRandGen, 1549 FeatureSB, FeatureSM4, FeatureSHA2, 1550 FeatureSHA3, FeatureAES]; 1551 list<SubtargetFeature> Ampere1B = [HasV8_7aOps, FeatureNEON, FeaturePerfMon, 1552 FeatureMTE, FeatureSSBS, FeatureRandGen, 1553 FeatureSB, FeatureSM4, FeatureSHA2, 1554 FeatureSHA3, FeatureAES, FeatureCSSC, 1555 FeatureWFxT, FeatureFullFP16]; 1556 1557 // ETE and TRBE are future architecture extensions. We temporarily enable them 1558 // by default for users targeting generic AArch64. The extensions do not 1559 // affect code generated by the compiler and can be used only by explicitly 1560 // mentioning the new system register names in assembly. 1561 list<SubtargetFeature> Generic = [FeatureFPARMv8, FeatureNEON, FeatureETE]; 1562} 1563 1564// FeatureFuseAdrpAdd is enabled under Generic to allow linker merging 1565// optimizations. 1566def : ProcessorModel<"generic", CortexA510Model, ProcessorFeatures.Generic, 1567 [FeatureFuseAES, FeatureFuseAdrpAdd, FeaturePostRAScheduler, 1568 FeatureEnableSelectOptimize]>; 1569def : ProcessorModel<"cortex-a35", CortexA53Model, ProcessorFeatures.A53, 1570 [TuneA35]>; 1571def : ProcessorModel<"cortex-a34", CortexA53Model, ProcessorFeatures.A53, 1572 [TuneA35]>; 1573def : ProcessorModel<"cortex-a53", CortexA53Model, ProcessorFeatures.A53, 1574 [TuneA53]>; 1575def : ProcessorModel<"cortex-a55", CortexA55Model, ProcessorFeatures.A55, 1576 [TuneA55]>; 1577def : ProcessorModel<"cortex-a510", CortexA510Model, ProcessorFeatures.A510, 1578 [TuneA510]>; 1579def : ProcessorModel<"cortex-a520", CortexA510Model, ProcessorFeatures.A520, 1580 [TuneA520]>; 1581def : ProcessorModel<"cortex-a57", CortexA57Model, ProcessorFeatures.A53, 1582 [TuneA57]>; 1583def : ProcessorModel<"cortex-a65", CortexA53Model, ProcessorFeatures.A65, 1584 [TuneA65]>; 1585def : ProcessorModel<"cortex-a65ae", CortexA53Model, ProcessorFeatures.A65, 1586 [TuneA65]>; 1587def : ProcessorModel<"cortex-a72", CortexA57Model, ProcessorFeatures.A53, 1588 [TuneA72]>; 1589def : ProcessorModel<"cortex-a73", CortexA57Model, ProcessorFeatures.A53, 1590 [TuneA73]>; 1591def : ProcessorModel<"cortex-a75", CortexA57Model, ProcessorFeatures.A55, 1592 [TuneA75]>; 1593def : ProcessorModel<"cortex-a76", CortexA57Model, ProcessorFeatures.A76, 1594 [TuneA76]>; 1595def : ProcessorModel<"cortex-a76ae", CortexA57Model, ProcessorFeatures.A76, 1596 [TuneA76]>; 1597def : ProcessorModel<"cortex-a77", CortexA57Model, ProcessorFeatures.A77, 1598 [TuneA77]>; 1599def : ProcessorModel<"cortex-a78", CortexA57Model, ProcessorFeatures.A78, 1600 [TuneA78]>; 1601def : ProcessorModel<"cortex-a78c", CortexA57Model, ProcessorFeatures.A78C, 1602 [TuneA78C]>; 1603def : ProcessorModel<"cortex-a710", NeoverseN2Model, ProcessorFeatures.A710, 1604 [TuneA710]>; 1605def : ProcessorModel<"cortex-a715", NeoverseN2Model, ProcessorFeatures.A715, 1606 [TuneA715]>; 1607def : ProcessorModel<"cortex-a720", NeoverseN2Model, ProcessorFeatures.A720, 1608 [TuneA720]>; 1609def : ProcessorModel<"cortex-r82", CortexA55Model, ProcessorFeatures.R82, 1610 [TuneR82]>; 1611def : ProcessorModel<"cortex-x1", CortexA57Model, ProcessorFeatures.X1, 1612 [TuneX1]>; 1613def : ProcessorModel<"cortex-x1c", CortexA57Model, ProcessorFeatures.X1C, 1614 [TuneX1]>; 1615def : ProcessorModel<"cortex-x2", NeoverseN2Model, ProcessorFeatures.X2, 1616 [TuneX2]>; 1617def : ProcessorModel<"cortex-x3", NeoverseN2Model, ProcessorFeatures.X3, 1618 [TuneX3]>; 1619def : ProcessorModel<"cortex-x4", NeoverseN2Model, ProcessorFeatures.X4, 1620 [TuneX4]>; 1621def : ProcessorModel<"neoverse-e1", CortexA53Model, 1622 ProcessorFeatures.NeoverseE1, [TuneNeoverseE1]>; 1623def : ProcessorModel<"neoverse-n1", NeoverseN1Model, 1624 ProcessorFeatures.NeoverseN1, [TuneNeoverseN1]>; 1625def : ProcessorModel<"neoverse-n2", NeoverseN2Model, 1626 ProcessorFeatures.NeoverseN2, [TuneNeoverseN2]>; 1627def : ProcessorModel<"neoverse-512tvb", NeoverseV1Model, 1628 ProcessorFeatures.Neoverse512TVB, [TuneNeoverse512TVB]>; 1629def : ProcessorModel<"neoverse-v1", NeoverseV1Model, 1630 ProcessorFeatures.NeoverseV1, [TuneNeoverseV1]>; 1631def : ProcessorModel<"neoverse-v2", NeoverseV2Model, 1632 ProcessorFeatures.NeoverseV2, [TuneNeoverseV2]>; 1633def : ProcessorModel<"exynos-m3", ExynosM3Model, ProcessorFeatures.ExynosM3, 1634 [TuneExynosM3]>; 1635def : ProcessorModel<"exynos-m4", ExynosM4Model, ProcessorFeatures.ExynosM4, 1636 [TuneExynosM4]>; 1637def : ProcessorModel<"exynos-m5", ExynosM5Model, ProcessorFeatures.ExynosM4, 1638 [TuneExynosM4]>; 1639def : ProcessorModel<"falkor", FalkorModel, ProcessorFeatures.Falkor, 1640 [TuneFalkor]>; 1641def : ProcessorModel<"saphira", FalkorModel, ProcessorFeatures.Saphira, 1642 [TuneSaphira]>; 1643def : ProcessorModel<"kryo", KryoModel, ProcessorFeatures.A53, [TuneKryo]>; 1644 1645// Cavium ThunderX/ThunderX T8X Processors 1646def : ProcessorModel<"thunderx", ThunderXT8XModel, ProcessorFeatures.ThunderX, 1647 [TuneThunderX]>; 1648def : ProcessorModel<"thunderxt88", ThunderXT8XModel, 1649 ProcessorFeatures.ThunderX, [TuneThunderXT88]>; 1650def : ProcessorModel<"thunderxt81", ThunderXT8XModel, 1651 ProcessorFeatures.ThunderX, [TuneThunderXT81]>; 1652def : ProcessorModel<"thunderxt83", ThunderXT8XModel, 1653 ProcessorFeatures.ThunderX, [TuneThunderXT83]>; 1654// Cavium ThunderX2T9X Processors. Formerly Broadcom Vulcan. 1655def : ProcessorModel<"thunderx2t99", ThunderX2T99Model, 1656 ProcessorFeatures.ThunderX2T99, [TuneThunderX2T99]>; 1657// Marvell ThunderX3T110 Processors. 1658def : ProcessorModel<"thunderx3t110", ThunderX3T110Model, 1659 ProcessorFeatures.ThunderX3T110, [TuneThunderX3T110]>; 1660def : ProcessorModel<"tsv110", TSV110Model, ProcessorFeatures.TSV110, 1661 [TuneTSV110]>; 1662 1663// Support cyclone as an alias for apple-a7 so we can still LTO old bitcode. 1664def : ProcessorModel<"cyclone", CycloneModel, ProcessorFeatures.AppleA7, 1665 [TuneAppleA7]>; 1666 1667// iPhone and iPad CPUs 1668def : ProcessorModel<"apple-a7", CycloneModel, ProcessorFeatures.AppleA7, 1669 [TuneAppleA7]>; 1670def : ProcessorModel<"apple-a8", CycloneModel, ProcessorFeatures.AppleA7, 1671 [TuneAppleA7]>; 1672def : ProcessorModel<"apple-a9", CycloneModel, ProcessorFeatures.AppleA7, 1673 [TuneAppleA7]>; 1674def : ProcessorModel<"apple-a10", CycloneModel, ProcessorFeatures.AppleA10, 1675 [TuneAppleA10]>; 1676def : ProcessorModel<"apple-a11", CycloneModel, ProcessorFeatures.AppleA11, 1677 [TuneAppleA11]>; 1678def : ProcessorModel<"apple-a12", CycloneModel, ProcessorFeatures.AppleA12, 1679 [TuneAppleA12]>; 1680def : ProcessorModel<"apple-a13", CycloneModel, ProcessorFeatures.AppleA13, 1681 [TuneAppleA13]>; 1682def : ProcessorModel<"apple-a14", CycloneModel, ProcessorFeatures.AppleA14, 1683 [TuneAppleA14]>; 1684def : ProcessorModel<"apple-a15", CycloneModel, ProcessorFeatures.AppleA15, 1685 [TuneAppleA15]>; 1686def : ProcessorModel<"apple-a16", CycloneModel, ProcessorFeatures.AppleA16, 1687 [TuneAppleA16]>; 1688def : ProcessorModel<"apple-a17", CycloneModel, ProcessorFeatures.AppleA17, 1689 [TuneAppleA17]>; 1690// Mac CPUs 1691def : ProcessorModel<"apple-m1", CycloneModel, ProcessorFeatures.AppleA14, 1692 [TuneAppleA14]>; 1693def : ProcessorModel<"apple-m2", CycloneModel, ProcessorFeatures.AppleA15, 1694 [TuneAppleA15]>; 1695def : ProcessorModel<"apple-m3", CycloneModel, ProcessorFeatures.AppleA16, 1696 [TuneAppleA16]>; 1697 1698// watch CPUs. 1699def : ProcessorModel<"apple-s4", CycloneModel, ProcessorFeatures.AppleA12, 1700 [TuneAppleA12]>; 1701def : ProcessorModel<"apple-s5", CycloneModel, ProcessorFeatures.AppleA12, 1702 [TuneAppleA12]>; 1703 1704// Alias for the latest Apple processor model supported by LLVM. 1705def : ProcessorModel<"apple-latest", CycloneModel, ProcessorFeatures.AppleA16, 1706 [TuneAppleA16]>; 1707 1708// Fujitsu A64FX 1709def : ProcessorModel<"a64fx", A64FXModel, ProcessorFeatures.A64FX, 1710 [TuneA64FX]>; 1711 1712// Nvidia Carmel 1713def : ProcessorModel<"carmel", NoSchedModel, ProcessorFeatures.Carmel, 1714 [TuneCarmel]>; 1715 1716// Ampere Computing 1717def : ProcessorModel<"ampere1", Ampere1Model, ProcessorFeatures.Ampere1, 1718 [TuneAmpere1]>; 1719 1720def : ProcessorModel<"ampere1a", Ampere1Model, ProcessorFeatures.Ampere1A, 1721 [TuneAmpere1A]>; 1722 1723def : ProcessorModel<"ampere1b", Ampere1BModel, ProcessorFeatures.Ampere1B, 1724 [TuneAmpere1B]>; 1725 1726//===----------------------------------------------------------------------===// 1727// Assembly parser 1728//===----------------------------------------------------------------------===// 1729 1730def GenericAsmParserVariant : AsmParserVariant { 1731 int Variant = 0; 1732 string Name = "generic"; 1733 string BreakCharacters = "."; 1734 string TokenizingCharacters = "[]*!/"; 1735} 1736 1737def AppleAsmParserVariant : AsmParserVariant { 1738 int Variant = 1; 1739 string Name = "apple-neon"; 1740 string BreakCharacters = "."; 1741 string TokenizingCharacters = "[]*!/"; 1742} 1743 1744//===----------------------------------------------------------------------===// 1745// Assembly printer 1746//===----------------------------------------------------------------------===// 1747// AArch64 Uses the MC printer for asm output, so make sure the TableGen 1748// AsmWriter bits get associated with the correct class. 1749def GenericAsmWriter : AsmWriter { 1750 string AsmWriterClassName = "InstPrinter"; 1751 int PassSubtarget = 1; 1752 int Variant = 0; 1753 bit isMCAsmWriter = 1; 1754} 1755 1756def AppleAsmWriter : AsmWriter { 1757 let AsmWriterClassName = "AppleInstPrinter"; 1758 int PassSubtarget = 1; 1759 int Variant = 1; 1760 int isMCAsmWriter = 1; 1761} 1762 1763//===----------------------------------------------------------------------===// 1764// Target Declaration 1765//===----------------------------------------------------------------------===// 1766 1767def AArch64 : Target { 1768 let InstructionSet = AArch64InstrInfo; 1769 let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant]; 1770 let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter]; 1771 let AllowRegisterRenaming = 1; 1772} 1773 1774//===----------------------------------------------------------------------===// 1775// Pfm Counters 1776//===----------------------------------------------------------------------===// 1777 1778include "AArch64PfmCounters.td" 1779