1//=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// 10//===----------------------------------------------------------------------===// 11 12//===----------------------------------------------------------------------===// 13// Target-independent interfaces which we are implementing. 14//===----------------------------------------------------------------------===// 15 16include "llvm/Target/Target.td" 17 18//===----------------------------------------------------------------------===// 19// AArch64 Subtarget features. 20// 21 22def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true", 23 "Enable ARMv8 FP">; 24 25def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", 26 "Enable Advanced SIMD instructions", [FeatureFPARMv8]>; 27 28def FeatureSM4 : SubtargetFeature< 29 "sm4", "HasSM4", "true", 30 "Enable SM3 and SM4 support", [FeatureNEON]>; 31 32def FeatureSHA2 : SubtargetFeature< 33 "sha2", "HasSHA2", "true", 34 "Enable SHA1 and SHA256 support", [FeatureNEON]>; 35 36def FeatureSHA3 : SubtargetFeature< 37 "sha3", "HasSHA3", "true", 38 "Enable SHA512 and SHA3 support", [FeatureNEON, FeatureSHA2]>; 39 40def FeatureAES : SubtargetFeature< 41 "aes", "HasAES", "true", 42 "Enable AES support", [FeatureNEON]>; 43 44// Crypto has been split up and any combination is now valid (see the 45// crypto definitions above). Also, crypto is now context sensitive: 46// it has a different meaning for e.g. Armv8.4 than it has for Armv8.2. 47// Therefore, we rely on Clang, the user interacing tool, to pass on the 48// appropriate crypto options. But here in the backend, crypto has very little 49// meaning anymore. We kept the Crypto definition here for backward 50// compatibility, and now imply features SHA2 and AES, which was the 51// "traditional" meaning of Crypto. 52def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", 53 "Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>; 54 55def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", 56 "Enable ARMv8 CRC-32 checksum instructions">; 57 58def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true", 59 "Enable ARMv8 Reliability, Availability and Serviceability Extensions">; 60 61def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true", 62 "Enable ARMv8.1 Large System Extension (LSE) atomic instructions">; 63 64def FeatureOutlineAtomics : SubtargetFeature<"outline-atomics", "OutlineAtomics", "true", 65 "Enable out of line atomics to support LSE instructions">; 66 67def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true", 68 "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions">; 69 70def FeaturePAN : SubtargetFeature< 71 "pan", "HasPAN", "true", 72 "Enables ARM v8.1 Privileged Access-Never extension">; 73 74def FeatureLOR : SubtargetFeature< 75 "lor", "HasLOR", "true", 76 "Enables ARM v8.1 Limited Ordering Regions extension">; 77 78def FeatureCONTEXTIDREL2 : SubtargetFeature<"CONTEXTIDREL2", "HasCONTEXTIDREL2", 79 "true", "Enable RW operand CONTEXTIDR_EL2" >; 80 81def FeatureVH : SubtargetFeature<"vh", "HasVH", "true", 82 "Enables ARM v8.1 Virtual Host extension", [FeatureCONTEXTIDREL2] >; 83 84def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", 85 "Enable ARMv8 PMUv3 Performance Monitors extension">; 86 87def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true", 88 "Full FP16", [FeatureFPARMv8]>; 89 90def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true", 91 "Enable FP16 FML instructions", [FeatureFullFP16]>; 92 93def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true", 94 "Enable Statistical Profiling extension">; 95 96def FeaturePAN_RWV : SubtargetFeature< 97 "pan-rwv", "HasPAN_RWV", "true", 98 "Enable v8.2 PAN s1e1R and s1e1W Variants", 99 [FeaturePAN]>; 100 101// UAO PState 102def FeaturePsUAO : SubtargetFeature< "uaops", "HasPsUAO", "true", 103 "Enable v8.2 UAO PState">; 104 105def FeatureCCPP : SubtargetFeature<"ccpp", "HasCCPP", 106 "true", "Enable v8.2 data Cache Clean to Point of Persistence" >; 107 108def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true", 109 "Enable Scalable Vector Extension (SVE) instructions", [FeatureFullFP16]>; 110 111// This flag is currently still labeled as Experimental, but when fully 112// implemented this should tell the compiler to use the zeroing pseudos to 113// benefit from the reverse instructions (e.g. SUB vs SUBR) if the inactive 114// lanes are known to be zero. The pseudos will then be expanded using the 115// MOVPRFX instruction to zero the inactive lanes. This feature should only be 116// enabled if MOVPRFX instructions are known to merge with the destructive 117// operations they prefix. 118// 119// This feature could similarly be extended to support cheap merging of _any_ 120// value into the inactive lanes using the MOVPRFX instruction that uses 121// merging-predication. 122def FeatureExperimentalZeroingPseudos 123 : SubtargetFeature<"use-experimental-zeroing-pseudos", 124 "UseExperimentalZeroingPseudos", "true", 125 "Hint to the compiler that the MOVPRFX instruction is " 126 "merged with destructive operations", 127 []>; 128 129def FeatureSVE2 : SubtargetFeature<"sve2", "HasSVE2", "true", 130 "Enable Scalable Vector Extension 2 (SVE2) instructions", [FeatureSVE]>; 131 132def FeatureSVE2AES : SubtargetFeature<"sve2-aes", "HasSVE2AES", "true", 133 "Enable AES SVE2 instructions", [FeatureSVE2, FeatureAES]>; 134 135def FeatureSVE2SM4 : SubtargetFeature<"sve2-sm4", "HasSVE2SM4", "true", 136 "Enable SM4 SVE2 instructions", [FeatureSVE2, FeatureSM4]>; 137 138def FeatureSVE2SHA3 : SubtargetFeature<"sve2-sha3", "HasSVE2SHA3", "true", 139 "Enable SHA3 SVE2 instructions", [FeatureSVE2, FeatureSHA3]>; 140 141def FeatureSVE2BitPerm : SubtargetFeature<"sve2-bitperm", "HasSVE2BitPerm", "true", 142 "Enable bit permutation SVE2 instructions", [FeatureSVE2]>; 143 144def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true", 145 "Has zero-cycle register moves">; 146 147def FeatureZCZeroingGP : SubtargetFeature<"zcz-gp", "HasZeroCycleZeroingGP", "true", 148 "Has zero-cycle zeroing instructions for generic registers">; 149 150def FeatureNoZCZeroingFP : SubtargetFeature<"no-zcz-fp", "HasZeroCycleZeroingFP", "false", 151 "Has no zero-cycle zeroing instructions for FP registers">; 152 153def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true", 154 "Has zero-cycle zeroing instructions", 155 [FeatureZCZeroingGP]>; 156 157/// ... but the floating-point version doesn't quite work in rare cases on older 158/// CPUs. 159def FeatureZCZeroingFPWorkaround : SubtargetFeature<"zcz-fp-workaround", 160 "HasZeroCycleZeroingFPWorkaround", "true", 161 "The zero-cycle floating-point zeroing instruction has a bug">; 162 163def FeatureStrictAlign : SubtargetFeature<"strict-align", 164 "StrictAlign", "true", 165 "Disallow all unaligned memory " 166 "access">; 167 168foreach i = {1-7,9-15,18,20-28,30} in 169 def FeatureReserveX#i : SubtargetFeature<"reserve-x"#i, "ReserveXRegister["#i#"]", "true", 170 "Reserve X"#i#", making it unavailable " 171 "as a GPR">; 172 173foreach i = {8-15,18} in 174 def FeatureCallSavedX#i : SubtargetFeature<"call-saved-x"#i, 175 "CustomCallSavedXRegs["#i#"]", "true", "Make X"#i#" callee saved.">; 176 177def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps", 178 "true", 179 "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">; 180 181def FeaturePredictableSelectIsExpensive : SubtargetFeature< 182 "predictable-select-expensive", "PredictableSelectIsExpensive", "true", 183 "Prefer likely predicted branches over selects">; 184 185def FeatureCustomCheapAsMoveHandling : SubtargetFeature<"custom-cheap-as-move", 186 "CustomAsCheapAsMove", "true", 187 "Use custom handling of cheap instructions">; 188 189def FeatureExynosCheapAsMoveHandling : SubtargetFeature<"exynos-cheap-as-move", 190 "ExynosAsCheapAsMove", "true", 191 "Use Exynos specific handling of cheap instructions", 192 [FeatureCustomCheapAsMoveHandling]>; 193 194def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler", 195 "UsePostRAScheduler", "true", "Schedule again after register allocation">; 196 197def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store", 198 "Misaligned128StoreIsSlow", "true", "Misaligned 128 bit stores are slow">; 199 200def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128", 201 "Paired128IsSlow", "true", "Paired 128 bit loads and stores are slow">; 202 203def FeatureSlowSTRQro : SubtargetFeature<"slow-strqro-store", "STRQroIsSlow", 204 "true", "STR of Q register with register offset is slow">; 205 206def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature< 207 "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern", 208 "true", "Use alternative pattern for sextload convert to f32">; 209 210def FeatureArithmeticBccFusion : SubtargetFeature< 211 "arith-bcc-fusion", "HasArithmeticBccFusion", "true", 212 "CPU fuses arithmetic+bcc operations">; 213 214def FeatureArithmeticCbzFusion : SubtargetFeature< 215 "arith-cbz-fusion", "HasArithmeticCbzFusion", "true", 216 "CPU fuses arithmetic + cbz/cbnz operations">; 217 218def FeatureCmpBccFusion : SubtargetFeature< 219 "cmp-bcc-fusion", "HasCmpBccFusion", "true", 220 "CPU fuses cmp+bcc operations">; 221 222def FeatureFuseAddress : SubtargetFeature< 223 "fuse-address", "HasFuseAddress", "true", 224 "CPU fuses address generation and memory operations">; 225 226def FeatureFuseAES : SubtargetFeature< 227 "fuse-aes", "HasFuseAES", "true", 228 "CPU fuses AES crypto operations">; 229 230def FeatureFuseArithmeticLogic : SubtargetFeature< 231 "fuse-arith-logic", "HasFuseArithmeticLogic", "true", 232 "CPU fuses arithmetic and logic operations">; 233 234def FeatureFuseCCSelect : SubtargetFeature< 235 "fuse-csel", "HasFuseCCSelect", "true", 236 "CPU fuses conditional select operations">; 237 238def FeatureFuseCryptoEOR : SubtargetFeature< 239 "fuse-crypto-eor", "HasFuseCryptoEOR", "true", 240 "CPU fuses AES/PMULL and EOR operations">; 241 242def FeatureFuseLiterals : SubtargetFeature< 243 "fuse-literals", "HasFuseLiterals", "true", 244 "CPU fuses literal generation operations">; 245 246def FeatureDisableLatencySchedHeuristic : SubtargetFeature< 247 "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true", 248 "Disable latency scheduling heuristic">; 249 250def FeatureForce32BitJumpTables 251 : SubtargetFeature<"force-32bit-jump-tables", "Force32BitJumpTables", "true", 252 "Force jump table entries to be 32-bits wide except at MinSize">; 253 254def FeatureRCPC : SubtargetFeature<"rcpc", "HasRCPC", "true", 255 "Enable support for RCPC extension">; 256 257def FeatureUseRSqrt : SubtargetFeature< 258 "use-reciprocal-square-root", "UseRSqrt", "true", 259 "Use the reciprocal square root approximation">; 260 261def FeatureDotProd : SubtargetFeature< 262 "dotprod", "HasDotProd", "true", 263 "Enable dot product support">; 264 265def FeaturePAuth : SubtargetFeature< 266 "pauth", "HasPAuth", "true", 267 "Enable v8.3-A Pointer Authentication extension">; 268 269def FeatureJS : SubtargetFeature< 270 "jsconv", "HasJS", "true", 271 "Enable v8.3-A JavaScript FP conversion instructions", 272 [FeatureFPARMv8]>; 273 274def FeatureCCIDX : SubtargetFeature< 275 "ccidx", "HasCCIDX", "true", 276 "Enable v8.3-A Extend of the CCSIDR number of sets">; 277 278def FeatureComplxNum : SubtargetFeature< 279 "complxnum", "HasComplxNum", "true", 280 "Enable v8.3-A Floating-point complex number support", 281 [FeatureNEON]>; 282 283def FeatureNV : SubtargetFeature< 284 "nv", "HasNV", "true", 285 "Enable v8.4-A Nested Virtualization Enchancement">; 286 287def FeatureMPAM : SubtargetFeature< 288 "mpam", "HasMPAM", "true", 289 "Enable v8.4-A Memory system Partitioning and Monitoring extension">; 290 291def FeatureDIT : SubtargetFeature< 292 "dit", "HasDIT", "true", 293 "Enable v8.4-A Data Independent Timing instructions">; 294 295def FeatureTRACEV8_4 : SubtargetFeature< 296 "tracev8.4", "HasTRACEV8_4", "true", 297 "Enable v8.4-A Trace extension">; 298 299def FeatureAM : SubtargetFeature< 300 "am", "HasAM", "true", 301 "Enable v8.4-A Activity Monitors extension">; 302 303def FeatureAMVS : SubtargetFeature< 304 "amvs", "HasAMVS", "true", 305 "Enable v8.6-A Activity Monitors Virtualization support", 306 [FeatureAM]>; 307 308def FeatureSEL2 : SubtargetFeature< 309 "sel2", "HasSEL2", "true", 310 "Enable v8.4-A Secure Exception Level 2 extension">; 311 312def FeaturePMU : SubtargetFeature< 313 "pmu", "HasPMU", "true", 314 "Enable v8.4-A PMU extension">; 315 316def FeatureTLB_RMI : SubtargetFeature< 317 "tlb-rmi", "HasTLB_RMI", "true", 318 "Enable v8.4-A TLB Range and Maintenance Instructions">; 319 320def FeatureFlagM : SubtargetFeature< 321 "flagm", "HasFlagM", "true", 322 "Enable v8.4-A Flag Manipulation Instructions">; 323 324// 8.4 RCPC enchancements: LDAPR & STLR instructions with Immediate Offset 325def FeatureRCPC_IMMO : SubtargetFeature<"rcpc-immo", "HasRCPC_IMMO", "true", 326 "Enable v8.4-A RCPC instructions with Immediate Offsets", 327 [FeatureRCPC]>; 328 329def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates", 330 "NegativeImmediates", "false", 331 "Convert immediates and instructions " 332 "to their negated or complemented " 333 "equivalent when the immediate does " 334 "not fit in the encoding.">; 335 336def FeatureLSLFast : SubtargetFeature< 337 "lsl-fast", "HasLSLFast", "true", 338 "CPU has a fastpath logical shift of up to 3 places">; 339 340def FeatureAggressiveFMA : 341 SubtargetFeature<"aggressive-fma", 342 "HasAggressiveFMA", 343 "true", 344 "Enable Aggressive FMA for floating-point.">; 345 346def FeatureAltFPCmp : SubtargetFeature<"altnzcv", "HasAlternativeNZCV", "true", 347 "Enable alternative NZCV format for floating point comparisons">; 348 349def FeatureFRInt3264 : SubtargetFeature<"fptoint", "HasFRInt3264", "true", 350 "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to " 351 "an integer (in FP format) forcing it to fit into a 32- or 64-bit int" >; 352 353def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict", 354 "true", "Enable architectural speculation restriction" >; 355 356def FeatureSB : SubtargetFeature<"sb", "HasSB", 357 "true", "Enable v8.5 Speculation Barrier" >; 358 359def FeatureSSBS : SubtargetFeature<"ssbs", "HasSSBS", 360 "true", "Enable Speculative Store Bypass Safe bit" >; 361 362def FeaturePredRes : SubtargetFeature<"predres", "HasPredRes", "true", 363 "Enable v8.5a execution and data prediction invalidation instructions" >; 364 365def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP", 366 "true", "Enable v8.5 Cache Clean to Point of Deep Persistence" >; 367 368def FeatureBranchTargetId : SubtargetFeature<"bti", "HasBTI", 369 "true", "Enable Branch Target Identification" >; 370 371def FeatureRandGen : SubtargetFeature<"rand", "HasRandGen", 372 "true", "Enable Random Number generation instructions" >; 373 374def FeatureMTE : SubtargetFeature<"mte", "HasMTE", 375 "true", "Enable Memory Tagging Extension" >; 376 377def FeatureTRBE : SubtargetFeature<"trbe", "HasTRBE", 378 "true", "Enable Trace Buffer Extension">; 379 380def FeatureETE : SubtargetFeature<"ete", "HasETE", 381 "true", "Enable Embedded Trace Extension", 382 [FeatureTRBE]>; 383 384def FeatureTME : SubtargetFeature<"tme", "HasTME", 385 "true", "Enable Transactional Memory Extension" >; 386 387def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals", 388 "AllowTaggedGlobals", 389 "true", "Use an instruction sequence for taking the address of a global " 390 "that allows a memory tag in the upper address bits">; 391 392def FeatureBF16 : SubtargetFeature<"bf16", "HasBF16", 393 "true", "Enable BFloat16 Extension" >; 394 395def FeatureMatMulInt8 : SubtargetFeature<"i8mm", "HasMatMulInt8", 396 "true", "Enable Matrix Multiply Int8 Extension">; 397 398def FeatureMatMulFP32 : SubtargetFeature<"f32mm", "HasMatMulFP32", 399 "true", "Enable Matrix Multiply FP32 Extension", [FeatureSVE]>; 400 401def FeatureMatMulFP64 : SubtargetFeature<"f64mm", "HasMatMulFP64", 402 "true", "Enable Matrix Multiply FP64 Extension", [FeatureSVE]>; 403 404def FeatureXS : SubtargetFeature<"xs", "HasXS", 405 "true", "Enable Armv8.7-A limited-TLB-maintenance instruction">; 406 407def FeatureWFxT : SubtargetFeature<"wfxt", "HasWFxT", 408 "true", "Enable Armv8.7-A WFET and WFIT instruction">; 409 410def FeatureHCX : SubtargetFeature< 411 "hcx", "HasHCX", "true", "Enable Armv8.7-A HCRX_EL2 system register">; 412 413def FeatureLS64 : SubtargetFeature<"ls64", "HasLS64", 414 "true", "Enable Armv8.7-A LD64B/ST64B Accelerator Extension">; 415 416def FeatureBRBE : SubtargetFeature<"brbe", "HasBRBE", 417 "true", "Enable Branch Record Buffer Extension">; 418 419def FeatureSPE_EEF : SubtargetFeature<"spe-eef", "HasSPE_EEF", 420 "true", "Enable extra register in the Statistical Profiling Extension">; 421 422def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps", 423 "true", "Enable fine grained virtualization traps extension">; 424 425def FeatureEnhancedCounterVirtualization : 426 SubtargetFeature<"ecv", "HasEnhancedCounterVirtualization", 427 "true", "Enable enhanced counter virtualization extension">; 428 429def FeatureRME : SubtargetFeature<"rme", "HasRME", 430 "true", "Enable Realm Management Extension">; 431 432// FIXME: SME should only imply the subset of SVE(2) instructions that are 433// legal in streaming mode. 434def FeatureSME : SubtargetFeature<"sme", "HasSME", "true", 435 "Enable Scalable Matrix Extension (SME)", [FeatureSVE2, FeatureBF16]>; 436 437def FeatureSMEF64 : SubtargetFeature<"sme-f64", "HasSMEF64", "true", 438 "Enable Scalable Matrix Extension (SME) F64F64 instructions", [FeatureSME]>; 439 440def FeatureSMEI64 : SubtargetFeature<"sme-i64", "HasSMEI64", "true", 441 "Enable Scalable Matrix Extension (SME) I16I64 instructions", [FeatureSME]>; 442 443//===----------------------------------------------------------------------===// 444// Architectures. 445// 446 447def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", 448 "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM, 449 FeaturePAN, FeatureLOR, FeatureVH]>; 450 451def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true", 452 "Support ARM v8.2a instructions", [HasV8_1aOps, FeaturePsUAO, 453 FeaturePAN_RWV, FeatureRAS, FeatureCCPP]>; 454 455def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true", 456 "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC, FeaturePAuth, 457 FeatureJS, FeatureCCIDX, FeatureComplxNum]>; 458 459def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", 460 "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd, 461 FeatureNV, FeatureMPAM, FeatureDIT, 462 FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeaturePMU, FeatureTLB_RMI, 463 FeatureFlagM, FeatureRCPC_IMMO]>; 464 465def HasV8_5aOps : SubtargetFeature< 466 "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions", 467 [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict, 468 FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist, 469 FeatureBranchTargetId]>; 470 471def HasV8_6aOps : SubtargetFeature< 472 "v8.6a", "HasV8_6aOps", "true", "Support ARM v8.6a instructions", 473 [HasV8_5aOps, FeatureAMVS, FeatureBF16, FeatureFineGrainedTraps, 474 FeatureEnhancedCounterVirtualization, FeatureMatMulInt8]>; 475 476def HasV8_7aOps : SubtargetFeature< 477 "v8.7a", "HasV8_7aOps", "true", "Support ARM v8.7a instructions", 478 [HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX]>; 479 480def HasV8_0rOps : SubtargetFeature< 481 "v8r", "HasV8_0rOps", "true", "Support ARM v8r instructions", 482 [//v8.1 483 FeatureCRC, FeaturePAN, FeatureRDM, FeatureLSE, FeatureCONTEXTIDREL2, 484 //v8.2 485 FeaturePerfMon, FeatureRAS, FeaturePsUAO, FeatureSM4, 486 FeatureSHA3, FeatureCCPP, FeatureFullFP16, FeaturePAN_RWV, 487 //v8.3 488 FeatureComplxNum, FeatureCCIDX, FeatureJS, 489 FeaturePAuth, FeatureRCPC, 490 //v8.4 491 FeatureDotProd, FeatureFP16FML, FeatureTRACEV8_4, 492 FeatureTLB_RMI, FeatureFlagM, FeatureDIT, FeatureSEL2, FeatureRCPC_IMMO, 493 //v8.5 494 FeatureSSBS, FeaturePredRes, FeatureSB, FeatureSpecRestrict]>; 495 496//===----------------------------------------------------------------------===// 497// Register File Description 498//===----------------------------------------------------------------------===// 499 500include "AArch64RegisterInfo.td" 501include "AArch64RegisterBanks.td" 502include "AArch64CallingConvention.td" 503 504//===----------------------------------------------------------------------===// 505// Instruction Descriptions 506//===----------------------------------------------------------------------===// 507 508include "AArch64Schedule.td" 509include "AArch64InstrInfo.td" 510include "AArch64SchedPredicates.td" 511include "AArch64SchedPredExynos.td" 512include "AArch64Combine.td" 513 514def AArch64InstrInfo : InstrInfo; 515 516//===----------------------------------------------------------------------===// 517// Named operands for MRS/MSR/TLBI/... 518//===----------------------------------------------------------------------===// 519 520include "AArch64SystemOperands.td" 521 522//===----------------------------------------------------------------------===// 523// Access to privileged registers 524//===----------------------------------------------------------------------===// 525 526foreach i = 1-3 in 527def FeatureUseEL#i#ForTP : SubtargetFeature<"tpidr-el"#i, "UseEL"#i#"ForTP", 528 "true", "Permit use of TPIDR_EL"#i#" for the TLS base">; 529 530//===----------------------------------------------------------------------===// 531// Control codegen mitigation against Straight Line Speculation vulnerability. 532//===----------------------------------------------------------------------===// 533 534def FeatureHardenSlsRetBr : SubtargetFeature<"harden-sls-retbr", 535 "HardenSlsRetBr", "true", 536 "Harden against straight line speculation across RET and BR instructions">; 537def FeatureHardenSlsBlr : SubtargetFeature<"harden-sls-blr", 538 "HardenSlsBlr", "true", 539 "Harden against straight line speculation across BLR instructions">; 540def FeatureHardenSlsNoComdat : SubtargetFeature<"harden-sls-nocomdat", 541 "HardenSlsNoComdat", "true", 542 "Generate thunk code for SLS mitigation in the normal text section">; 543 544//===----------------------------------------------------------------------===// 545// AArch64 Processors supported. 546// 547 548//===----------------------------------------------------------------------===// 549// Unsupported features to disable for scheduling models 550//===----------------------------------------------------------------------===// 551 552class AArch64Unsupported { list<Predicate> F; } 553 554def SVEUnsupported : AArch64Unsupported { 555 let F = [HasSVE, HasSVE2, HasSVE2AES, HasSVE2SM4, HasSVE2SHA3, 556 HasSVE2BitPerm]; 557} 558 559def PAUnsupported : AArch64Unsupported { 560 let F = [HasPAuth]; 561} 562 563def SMEUnsupported : AArch64Unsupported { 564 let F = [HasSME, HasSMEF64, HasSMEI64]; 565} 566 567include "AArch64SchedA53.td" 568include "AArch64SchedA55.td" 569include "AArch64SchedA57.td" 570include "AArch64SchedCyclone.td" 571include "AArch64SchedFalkor.td" 572include "AArch64SchedKryo.td" 573include "AArch64SchedExynosM3.td" 574include "AArch64SchedExynosM4.td" 575include "AArch64SchedExynosM5.td" 576include "AArch64SchedThunderX.td" 577include "AArch64SchedThunderX2T99.td" 578include "AArch64SchedA64FX.td" 579include "AArch64SchedThunderX3T110.td" 580include "AArch64SchedTSV110.td" 581 582def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35", 583 "Cortex-A35 ARM processors", [ 584 FeatureCRC, 585 FeatureCrypto, 586 FeatureFPARMv8, 587 FeatureNEON, 588 FeaturePerfMon 589 ]>; 590 591def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", 592 "Cortex-A53 ARM processors", [ 593 FeatureBalanceFPOps, 594 FeatureCRC, 595 FeatureCrypto, 596 FeatureCustomCheapAsMoveHandling, 597 FeatureFPARMv8, 598 FeatureFuseAES, 599 FeatureNEON, 600 FeaturePerfMon, 601 FeaturePostRAScheduler, 602 ]>; 603 604def ProcA55 : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55", 605 "Cortex-A55 ARM processors", [ 606 HasV8_2aOps, 607 FeatureCrypto, 608 FeatureFPARMv8, 609 FeatureFuseAES, 610 FeatureNEON, 611 FeatureFullFP16, 612 FeatureDotProd, 613 FeatureRCPC, 614 FeaturePerfMon, 615 FeaturePostRAScheduler, 616 ]>; 617 618def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", 619 "Cortex-A57 ARM processors", [ 620 FeatureBalanceFPOps, 621 FeatureCRC, 622 FeatureCrypto, 623 FeatureCustomCheapAsMoveHandling, 624 FeatureFPARMv8, 625 FeatureFuseAES, 626 FeatureFuseLiterals, 627 FeatureNEON, 628 FeaturePerfMon, 629 FeaturePostRAScheduler, 630 FeaturePredictableSelectIsExpensive 631 ]>; 632 633def ProcA65 : SubtargetFeature<"a65", "ARMProcFamily", "CortexA65", 634 "Cortex-A65 ARM processors", [ 635 HasV8_2aOps, 636 FeatureCrypto, 637 FeatureDotProd, 638 FeatureFPARMv8, 639 FeatureFullFP16, 640 FeatureFuseAddress, 641 FeatureFuseAES, 642 FeatureFuseLiterals, 643 FeatureNEON, 644 FeatureRAS, 645 FeatureRCPC, 646 FeatureSSBS, 647 ]>; 648 649def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72", 650 "Cortex-A72 ARM processors", [ 651 FeatureCRC, 652 FeatureCrypto, 653 FeatureFPARMv8, 654 FeatureFuseAES, 655 FeatureFuseLiterals, 656 FeatureNEON, 657 FeaturePerfMon 658 ]>; 659 660def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73", 661 "Cortex-A73 ARM processors", [ 662 FeatureCRC, 663 FeatureCrypto, 664 FeatureFPARMv8, 665 FeatureFuseAES, 666 FeatureNEON, 667 FeaturePerfMon 668 ]>; 669 670def ProcA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75", 671 "Cortex-A75 ARM processors", [ 672 HasV8_2aOps, 673 FeatureCrypto, 674 FeatureFPARMv8, 675 FeatureFuseAES, 676 FeatureNEON, 677 FeatureFullFP16, 678 FeatureDotProd, 679 FeatureRCPC, 680 FeaturePerfMon 681 ]>; 682 683def ProcA76 : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76", 684 "Cortex-A76 ARM processors", [ 685 HasV8_2aOps, 686 FeatureFPARMv8, 687 FeatureFuseAES, 688 FeatureNEON, 689 FeatureRCPC, 690 FeatureCrypto, 691 FeatureFullFP16, 692 FeatureDotProd, 693 FeatureSSBS 694 ]>; 695 696def ProcA77 : SubtargetFeature<"a77", "ARMProcFamily", "CortexA77", 697 "Cortex-A77 ARM processors", [ 698 HasV8_2aOps, 699 FeatureCmpBccFusion, 700 FeatureFPARMv8, 701 FeatureFuseAES, 702 FeatureNEON, FeatureRCPC, 703 FeatureCrypto, 704 FeatureFullFP16, 705 FeatureDotProd 706 ]>; 707 708def ProcA78 : SubtargetFeature<"cortex-a78", "ARMProcFamily", 709 "CortexA78", 710 "Cortex-A78 ARM processors", [ 711 HasV8_2aOps, 712 FeatureCmpBccFusion, 713 FeatureCrypto, 714 FeatureFPARMv8, 715 FeatureFuseAES, 716 FeatureNEON, 717 FeatureRCPC, 718 FeaturePerfMon, 719 FeaturePostRAScheduler, 720 FeatureSPE, 721 FeatureFullFP16, 722 FeatureSSBS, 723 FeatureDotProd]>; 724 725def ProcA78C : SubtargetFeature<"cortex-a78c", "ARMProcFamily", 726 "CortexA78C", 727 "Cortex-A78C ARM processors", [ 728 HasV8_2aOps, 729 FeatureCmpBccFusion, 730 FeatureCrypto, 731 FeatureDotProd, 732 FeatureFlagM, 733 FeatureFP16FML, 734 FeatureFPARMv8, 735 FeatureFullFP16, 736 FeatureFuseAES, 737 FeatureNEON, 738 FeaturePAuth, 739 FeaturePerfMon, 740 FeaturePostRAScheduler, 741 FeatureRCPC, 742 FeatureSPE, 743 FeatureSSBS]>; 744 745def ProcR82 : SubtargetFeature<"cortex-r82", "ARMProcFamily", 746 "CortexR82", 747 "Cortex-R82 ARM Processors", [ 748 FeaturePostRAScheduler, 749 // All other features are implied by v8_0r ops: 750 HasV8_0rOps, 751 ]>; 752 753def ProcX1 : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1", 754 "Cortex-X1 ARM processors", [ 755 HasV8_2aOps, 756 FeatureCmpBccFusion, 757 FeatureCrypto, 758 FeatureFPARMv8, 759 FeatureFuseAES, 760 FeatureNEON, 761 FeatureRCPC, 762 FeaturePerfMon, 763 FeaturePostRAScheduler, 764 FeatureSPE, 765 FeatureFullFP16, 766 FeatureDotProd]>; 767 768def ProcA64FX : SubtargetFeature<"a64fx", "ARMProcFamily", "A64FX", 769 "Fujitsu A64FX processors", [ 770 HasV8_2aOps, 771 FeatureFPARMv8, 772 FeatureNEON, 773 FeatureSHA2, 774 FeaturePerfMon, 775 FeatureFullFP16, 776 FeatureSVE, 777 FeaturePostRAScheduler, 778 FeatureComplxNum, 779 FeatureAggressiveFMA, 780 FeatureArithmeticBccFusion, 781 FeaturePredictableSelectIsExpensive 782 ]>; 783 784def ProcCarmel : SubtargetFeature<"carmel", "ARMProcFamily", "Carmel", 785 "Nvidia Carmel processors", [ 786 HasV8_2aOps, 787 FeatureNEON, 788 FeatureCrypto, 789 FeatureFullFP16 790 ]>; 791 792// Note that cyclone does not fuse AES instructions, but newer apple chips do 793// perform the fusion and cyclone is used by default when targetting apple OSes. 794def ProcAppleA7 : SubtargetFeature<"apple-a7", "ARMProcFamily", "AppleA7", 795 "Apple A7 (the CPU formerly known as Cyclone)", [ 796 FeatureAlternateSExtLoadCVTF32Pattern, 797 FeatureArithmeticBccFusion, 798 FeatureArithmeticCbzFusion, 799 FeatureCrypto, 800 FeatureDisableLatencySchedHeuristic, 801 FeatureFPARMv8, 802 FeatureFuseAES, 803 FeatureFuseCryptoEOR, 804 FeatureNEON, 805 FeaturePerfMon, 806 FeatureZCRegMove, 807 FeatureZCZeroing, 808 FeatureZCZeroingFPWorkaround 809 ]>; 810 811def ProcAppleA10 : SubtargetFeature<"apple-a10", "ARMProcFamily", "AppleA10", 812 "Apple A10", [ 813 FeatureAlternateSExtLoadCVTF32Pattern, 814 FeatureArithmeticBccFusion, 815 FeatureArithmeticCbzFusion, 816 FeatureCrypto, 817 FeatureDisableLatencySchedHeuristic, 818 FeatureFPARMv8, 819 FeatureFuseAES, 820 FeatureFuseCryptoEOR, 821 FeatureNEON, 822 FeaturePerfMon, 823 FeatureZCRegMove, 824 FeatureZCZeroing, 825 FeatureCRC, 826 FeatureRDM, 827 FeaturePAN, 828 FeatureLOR, 829 FeatureVH, 830 ]>; 831 832def ProcAppleA11 : SubtargetFeature<"apple-a11", "ARMProcFamily", "AppleA11", 833 "Apple A11", [ 834 FeatureAlternateSExtLoadCVTF32Pattern, 835 FeatureArithmeticBccFusion, 836 FeatureArithmeticCbzFusion, 837 FeatureCrypto, 838 FeatureDisableLatencySchedHeuristic, 839 FeatureFPARMv8, 840 FeatureFuseAES, 841 FeatureFuseCryptoEOR, 842 FeatureNEON, 843 FeaturePerfMon, 844 FeatureZCRegMove, 845 FeatureZCZeroing, 846 FeatureFullFP16, 847 HasV8_2aOps 848 ]>; 849 850def ProcAppleA12 : SubtargetFeature<"apple-a12", "ARMProcFamily", "AppleA12", 851 "Apple A12", [ 852 FeatureAlternateSExtLoadCVTF32Pattern, 853 FeatureArithmeticBccFusion, 854 FeatureArithmeticCbzFusion, 855 FeatureCrypto, 856 FeatureDisableLatencySchedHeuristic, 857 FeatureFPARMv8, 858 FeatureFuseAES, 859 FeatureFuseCryptoEOR, 860 FeatureNEON, 861 FeaturePerfMon, 862 FeatureZCRegMove, 863 FeatureZCZeroing, 864 FeatureFullFP16, 865 HasV8_3aOps 866 ]>; 867 868def ProcAppleA13 : SubtargetFeature<"apple-a13", "ARMProcFamily", "AppleA13", 869 "Apple A13", [ 870 FeatureAlternateSExtLoadCVTF32Pattern, 871 FeatureArithmeticBccFusion, 872 FeatureArithmeticCbzFusion, 873 FeatureCrypto, 874 FeatureDisableLatencySchedHeuristic, 875 FeatureFPARMv8, 876 FeatureFuseAES, 877 FeatureFuseCryptoEOR, 878 FeatureNEON, 879 FeaturePerfMon, 880 FeatureZCRegMove, 881 FeatureZCZeroing, 882 FeatureFullFP16, 883 FeatureFP16FML, 884 FeatureSHA3, 885 HasV8_4aOps 886 ]>; 887 888def ProcAppleA14 : SubtargetFeature<"apple-a14", "ARMProcFamily", "AppleA14", 889 "Apple A14", [ 890 FeatureAggressiveFMA, 891 FeatureAlternateSExtLoadCVTF32Pattern, 892 FeatureAltFPCmp, 893 FeatureArithmeticBccFusion, 894 FeatureArithmeticCbzFusion, 895 FeatureCrypto, 896 FeatureDisableLatencySchedHeuristic, 897 FeatureFPARMv8, 898 FeatureFRInt3264, 899 FeatureFuseAddress, 900 FeatureFuseAES, 901 FeatureFuseArithmeticLogic, 902 FeatureFuseCCSelect, 903 FeatureFuseCryptoEOR, 904 FeatureFuseLiterals, 905 FeatureNEON, 906 FeaturePerfMon, 907 FeatureSpecRestrict, 908 FeatureSSBS, 909 FeatureSB, 910 FeaturePredRes, 911 FeatureCacheDeepPersist, 912 FeatureZCRegMove, 913 FeatureZCZeroing, 914 FeatureFullFP16, 915 FeatureFP16FML, 916 FeatureSHA3, 917 HasV8_4aOps 918 ]>; 919 920def ProcExynosM3 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3", 921 "Samsung Exynos-M3 processors", 922 [FeatureCRC, 923 FeatureCrypto, 924 FeatureExynosCheapAsMoveHandling, 925 FeatureForce32BitJumpTables, 926 FeatureFuseAddress, 927 FeatureFuseAES, 928 FeatureFuseCCSelect, 929 FeatureFuseLiterals, 930 FeatureLSLFast, 931 FeaturePerfMon, 932 FeaturePostRAScheduler, 933 FeaturePredictableSelectIsExpensive]>; 934 935def ProcExynosM4 : SubtargetFeature<"exynosm4", "ARMProcFamily", "ExynosM3", 936 "Samsung Exynos-M4 processors", 937 [HasV8_2aOps, 938 FeatureArithmeticBccFusion, 939 FeatureArithmeticCbzFusion, 940 FeatureCrypto, 941 FeatureDotProd, 942 FeatureExynosCheapAsMoveHandling, 943 FeatureForce32BitJumpTables, 944 FeatureFullFP16, 945 FeatureFuseAddress, 946 FeatureFuseAES, 947 FeatureFuseArithmeticLogic, 948 FeatureFuseCCSelect, 949 FeatureFuseLiterals, 950 FeatureLSLFast, 951 FeaturePerfMon, 952 FeaturePostRAScheduler, 953 FeatureZCZeroing]>; 954 955def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo", 956 "Qualcomm Kryo processors", [ 957 FeatureCRC, 958 FeatureCrypto, 959 FeatureCustomCheapAsMoveHandling, 960 FeatureFPARMv8, 961 FeatureNEON, 962 FeaturePerfMon, 963 FeaturePostRAScheduler, 964 FeaturePredictableSelectIsExpensive, 965 FeatureZCZeroing, 966 FeatureLSLFast 967 ]>; 968 969def ProcFalkor : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor", 970 "Qualcomm Falkor processors", [ 971 FeatureCRC, 972 FeatureCrypto, 973 FeatureCustomCheapAsMoveHandling, 974 FeatureFPARMv8, 975 FeatureNEON, 976 FeaturePerfMon, 977 FeaturePostRAScheduler, 978 FeaturePredictableSelectIsExpensive, 979 FeatureRDM, 980 FeatureZCZeroing, 981 FeatureLSLFast, 982 FeatureSlowSTRQro 983 ]>; 984 985def ProcNeoverseE1 : SubtargetFeature<"neoversee1", "ARMProcFamily", 986 "NeoverseE1", 987 "Neoverse E1 ARM processors", [ 988 HasV8_2aOps, 989 FeatureCrypto, 990 FeatureDotProd, 991 FeatureFPARMv8, 992 FeatureFullFP16, 993 FeatureNEON, 994 FeatureRCPC, 995 FeatureSSBS, 996 FeaturePostRAScheduler, 997 FeatureFuseAES, 998 ]>; 999 1000def ProcNeoverseN1 : SubtargetFeature<"neoversen1", "ARMProcFamily", 1001 "NeoverseN1", 1002 "Neoverse N1 ARM processors", [ 1003 HasV8_2aOps, 1004 FeatureCrypto, 1005 FeatureDotProd, 1006 FeatureFPARMv8, 1007 FeatureFullFP16, 1008 FeatureNEON, 1009 FeatureRCPC, 1010 FeatureSPE, 1011 FeatureSSBS, 1012 FeaturePostRAScheduler, 1013 FeatureFuseAES, 1014 ]>; 1015 1016def ProcNeoverseN2 : SubtargetFeature<"neoversen2", "ARMProcFamily", 1017 "NeoverseN2", 1018 "Neoverse N2 ARM processors", [ 1019 HasV8_5aOps, 1020 FeatureBF16, 1021 FeatureETE, 1022 FeatureMatMulInt8, 1023 FeatureMTE, 1024 FeatureSVE2, 1025 FeatureSVE2BitPerm, 1026 FeatureTRBE, 1027 FeaturePostRAScheduler, 1028 FeatureCrypto, 1029 FeatureFuseAES, 1030 ]>; 1031 1032def ProcNeoverseV1 : SubtargetFeature<"neoversev1", "ARMProcFamily", 1033 "NeoverseV1", 1034 "Neoverse V1 ARM processors", [ 1035 HasV8_4aOps, 1036 FeatureBF16, 1037 FeatureCacheDeepPersist, 1038 FeatureCrypto, 1039 FeatureFPARMv8, 1040 FeatureFP16FML, 1041 FeatureFullFP16, 1042 FeatureFuseAES, 1043 FeatureMatMulInt8, 1044 FeatureNEON, 1045 FeaturePerfMon, 1046 FeaturePostRAScheduler, 1047 FeatureRandGen, 1048 FeatureSPE, 1049 FeatureSSBS, 1050 FeatureSVE]>; 1051 1052def ProcSaphira : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira", 1053 "Qualcomm Saphira processors", [ 1054 FeatureCrypto, 1055 FeatureCustomCheapAsMoveHandling, 1056 FeatureFPARMv8, 1057 FeatureNEON, 1058 FeatureSPE, 1059 FeaturePerfMon, 1060 FeaturePostRAScheduler, 1061 FeaturePredictableSelectIsExpensive, 1062 FeatureZCZeroing, 1063 FeatureLSLFast, 1064 HasV8_4aOps]>; 1065 1066def ProcThunderX2T99 : SubtargetFeature<"thunderx2t99", "ARMProcFamily", 1067 "ThunderX2T99", 1068 "Cavium ThunderX2 processors", [ 1069 FeatureAggressiveFMA, 1070 FeatureCRC, 1071 FeatureCrypto, 1072 FeatureFPARMv8, 1073 FeatureArithmeticBccFusion, 1074 FeatureNEON, 1075 FeaturePostRAScheduler, 1076 FeaturePredictableSelectIsExpensive, 1077 FeatureLSE, 1078 HasV8_1aOps]>; 1079 1080def ProcThunderX3T110 : SubtargetFeature<"thunderx3t110", "ARMProcFamily", 1081 "ThunderX3T110", 1082 "Marvell ThunderX3 processors", [ 1083 FeatureAggressiveFMA, 1084 FeatureCRC, 1085 FeatureCrypto, 1086 FeatureFPARMv8, 1087 FeatureArithmeticBccFusion, 1088 FeatureNEON, 1089 FeaturePostRAScheduler, 1090 FeaturePredictableSelectIsExpensive, 1091 FeatureLSE, 1092 FeaturePAuth, 1093 FeatureBalanceFPOps, 1094 FeaturePerfMon, 1095 FeatureStrictAlign, 1096 HasV8_3aOps]>; 1097 1098def ProcThunderX : SubtargetFeature<"thunderx", "ARMProcFamily", "ThunderX", 1099 "Cavium ThunderX processors", [ 1100 FeatureCRC, 1101 FeatureCrypto, 1102 FeatureFPARMv8, 1103 FeaturePerfMon, 1104 FeaturePostRAScheduler, 1105 FeaturePredictableSelectIsExpensive, 1106 FeatureNEON]>; 1107 1108def ProcThunderXT88 : SubtargetFeature<"thunderxt88", "ARMProcFamily", 1109 "ThunderXT88", 1110 "Cavium ThunderX processors", [ 1111 FeatureCRC, 1112 FeatureCrypto, 1113 FeatureFPARMv8, 1114 FeaturePerfMon, 1115 FeaturePostRAScheduler, 1116 FeaturePredictableSelectIsExpensive, 1117 FeatureNEON]>; 1118 1119def ProcThunderXT81 : SubtargetFeature<"thunderxt81", "ARMProcFamily", 1120 "ThunderXT81", 1121 "Cavium ThunderX processors", [ 1122 FeatureCRC, 1123 FeatureCrypto, 1124 FeatureFPARMv8, 1125 FeaturePerfMon, 1126 FeaturePostRAScheduler, 1127 FeaturePredictableSelectIsExpensive, 1128 FeatureNEON]>; 1129 1130def ProcThunderXT83 : SubtargetFeature<"thunderxt83", "ARMProcFamily", 1131 "ThunderXT83", 1132 "Cavium ThunderX processors", [ 1133 FeatureCRC, 1134 FeatureCrypto, 1135 FeatureFPARMv8, 1136 FeaturePerfMon, 1137 FeaturePostRAScheduler, 1138 FeaturePredictableSelectIsExpensive, 1139 FeatureNEON]>; 1140 1141def ProcTSV110 : SubtargetFeature<"tsv110", "ARMProcFamily", "TSV110", 1142 "HiSilicon TS-V110 processors", [ 1143 HasV8_2aOps, 1144 FeatureCrypto, 1145 FeatureCustomCheapAsMoveHandling, 1146 FeatureFPARMv8, 1147 FeatureFuseAES, 1148 FeatureNEON, 1149 FeaturePerfMon, 1150 FeaturePostRAScheduler, 1151 FeatureSPE, 1152 FeatureFullFP16, 1153 FeatureFP16FML, 1154 FeatureDotProd]>; 1155 1156def : ProcessorModel<"generic", NoSchedModel, [ 1157 FeatureFPARMv8, 1158 FeatureFuseAES, 1159 FeatureNEON, 1160 FeaturePerfMon, 1161 FeaturePostRAScheduler, 1162// ETE and TRBE are future architecture extensions. We temporarily enable them 1163// by default for users targeting generic AArch64, until it is decided in which 1164// armv8.x-a architecture revision they will end up. The extensions do not 1165// affect code generated by the compiler and can be used only by explicitly 1166// mentioning the new system register names in assembly. 1167 FeatureETE 1168 ]>; 1169 1170def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>; 1171def : ProcessorModel<"cortex-a34", CortexA53Model, [ProcA35]>; 1172def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>; 1173def : ProcessorModel<"cortex-a55", CortexA55Model, [ProcA55]>; 1174def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>; 1175def : ProcessorModel<"cortex-a65", CortexA53Model, [ProcA65]>; 1176def : ProcessorModel<"cortex-a65ae", CortexA53Model, [ProcA65]>; 1177def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA72]>; 1178def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA73]>; 1179def : ProcessorModel<"cortex-a75", CortexA57Model, [ProcA75]>; 1180def : ProcessorModel<"cortex-a76", CortexA57Model, [ProcA76]>; 1181def : ProcessorModel<"cortex-a76ae", CortexA57Model, [ProcA76]>; 1182def : ProcessorModel<"cortex-a77", CortexA57Model, [ProcA77]>; 1183def : ProcessorModel<"cortex-a78", CortexA57Model, [ProcA78]>; 1184def : ProcessorModel<"cortex-a78c", CortexA57Model, [ProcA78C]>; 1185def : ProcessorModel<"cortex-r82", CortexA55Model, [ProcR82]>; 1186def : ProcessorModel<"cortex-x1", CortexA57Model, [ProcX1]>; 1187def : ProcessorModel<"neoverse-e1", CortexA53Model, [ProcNeoverseE1]>; 1188def : ProcessorModel<"neoverse-n1", CortexA57Model, [ProcNeoverseN1]>; 1189def : ProcessorModel<"neoverse-n2", CortexA57Model, [ProcNeoverseN2]>; 1190def : ProcessorModel<"neoverse-v1", CortexA57Model, [ProcNeoverseV1]>; 1191def : ProcessorModel<"exynos-m3", ExynosM3Model, [ProcExynosM3]>; 1192def : ProcessorModel<"exynos-m4", ExynosM4Model, [ProcExynosM4]>; 1193def : ProcessorModel<"exynos-m5", ExynosM5Model, [ProcExynosM4]>; 1194def : ProcessorModel<"falkor", FalkorModel, [ProcFalkor]>; 1195def : ProcessorModel<"saphira", FalkorModel, [ProcSaphira]>; 1196def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>; 1197// Cavium ThunderX/ThunderX T8X Processors 1198def : ProcessorModel<"thunderx", ThunderXT8XModel, [ProcThunderX]>; 1199def : ProcessorModel<"thunderxt88", ThunderXT8XModel, [ProcThunderXT88]>; 1200def : ProcessorModel<"thunderxt81", ThunderXT8XModel, [ProcThunderXT81]>; 1201def : ProcessorModel<"thunderxt83", ThunderXT8XModel, [ProcThunderXT83]>; 1202// Cavium ThunderX2T9X Processors. Formerly Broadcom Vulcan. 1203def : ProcessorModel<"thunderx2t99", ThunderX2T99Model, [ProcThunderX2T99]>; 1204// Marvell ThunderX3T110 Processors. 1205def : ProcessorModel<"thunderx3t110", ThunderX3T110Model, [ProcThunderX3T110]>; 1206def : ProcessorModel<"tsv110", TSV110Model, [ProcTSV110]>; 1207 1208// Support cyclone as an alias for apple-a7 so we can still LTO old bitcode. 1209def : ProcessorModel<"cyclone", CycloneModel, [ProcAppleA7]>; 1210 1211// iPhone and iPad CPUs 1212def : ProcessorModel<"apple-a7", CycloneModel, [ProcAppleA7]>; 1213def : ProcessorModel<"apple-a8", CycloneModel, [ProcAppleA7]>; 1214def : ProcessorModel<"apple-a9", CycloneModel, [ProcAppleA7]>; 1215def : ProcessorModel<"apple-a10", CycloneModel, [ProcAppleA10]>; 1216def : ProcessorModel<"apple-a11", CycloneModel, [ProcAppleA11]>; 1217def : ProcessorModel<"apple-a12", CycloneModel, [ProcAppleA12]>; 1218def : ProcessorModel<"apple-a13", CycloneModel, [ProcAppleA13]>; 1219def : ProcessorModel<"apple-a14", CycloneModel, [ProcAppleA14]>; 1220 1221// Mac CPUs 1222def : ProcessorModel<"apple-m1", CycloneModel, [ProcAppleA14]>; 1223 1224// watch CPUs. 1225def : ProcessorModel<"apple-s4", CycloneModel, [ProcAppleA12]>; 1226def : ProcessorModel<"apple-s5", CycloneModel, [ProcAppleA12]>; 1227 1228// Alias for the latest Apple processor model supported by LLVM. 1229def : ProcessorModel<"apple-latest", CycloneModel, [ProcAppleA14]>; 1230 1231// Fujitsu A64FX 1232def : ProcessorModel<"a64fx", A64FXModel, [ProcA64FX]>; 1233 1234// Nvidia Carmel 1235def : ProcessorModel<"carmel", NoSchedModel, [ProcCarmel]>; 1236 1237//===----------------------------------------------------------------------===// 1238// Assembly parser 1239//===----------------------------------------------------------------------===// 1240 1241def GenericAsmParserVariant : AsmParserVariant { 1242 int Variant = 0; 1243 string Name = "generic"; 1244 string BreakCharacters = "."; 1245 string TokenizingCharacters = "[]*!/"; 1246} 1247 1248def AppleAsmParserVariant : AsmParserVariant { 1249 int Variant = 1; 1250 string Name = "apple-neon"; 1251 string BreakCharacters = "."; 1252 string TokenizingCharacters = "[]*!/"; 1253} 1254 1255//===----------------------------------------------------------------------===// 1256// Assembly printer 1257//===----------------------------------------------------------------------===// 1258// AArch64 Uses the MC printer for asm output, so make sure the TableGen 1259// AsmWriter bits get associated with the correct class. 1260def GenericAsmWriter : AsmWriter { 1261 string AsmWriterClassName = "InstPrinter"; 1262 int PassSubtarget = 1; 1263 int Variant = 0; 1264 bit isMCAsmWriter = 1; 1265} 1266 1267def AppleAsmWriter : AsmWriter { 1268 let AsmWriterClassName = "AppleInstPrinter"; 1269 int PassSubtarget = 1; 1270 int Variant = 1; 1271 int isMCAsmWriter = 1; 1272} 1273 1274//===----------------------------------------------------------------------===// 1275// Target Declaration 1276//===----------------------------------------------------------------------===// 1277 1278def AArch64 : Target { 1279 let InstructionSet = AArch64InstrInfo; 1280 let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant]; 1281 let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter]; 1282 let AllowRegisterRenaming = 1; 1283} 1284 1285//===----------------------------------------------------------------------===// 1286// Pfm Counters 1287//===----------------------------------------------------------------------===// 1288 1289include "AArch64PfmCounters.td" 1290