1//=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// 10//===----------------------------------------------------------------------===// 11 12//===----------------------------------------------------------------------===// 13// Target-independent interfaces which we are implementing. 14//===----------------------------------------------------------------------===// 15 16include "llvm/Target/Target.td" 17 18//===----------------------------------------------------------------------===// 19// AArch64 Subtarget features. 20// 21 22def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true", 23 "Enable ARMv8 FP">; 24 25def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", 26 "Enable Advanced SIMD instructions", [FeatureFPARMv8]>; 27 28def FeatureSM4 : SubtargetFeature< 29 "sm4", "HasSM4", "true", 30 "Enable SM3 and SM4 support", [FeatureNEON]>; 31 32def FeatureSHA2 : SubtargetFeature< 33 "sha2", "HasSHA2", "true", 34 "Enable SHA1 and SHA256 support", [FeatureNEON]>; 35 36def FeatureSHA3 : SubtargetFeature< 37 "sha3", "HasSHA3", "true", 38 "Enable SHA512 and SHA3 support", [FeatureNEON, FeatureSHA2]>; 39 40def FeatureAES : SubtargetFeature< 41 "aes", "HasAES", "true", 42 "Enable AES support", [FeatureNEON]>; 43 44// Crypto has been split up and any combination is now valid (see the 45// crypto definitions above). Also, crypto is now context sensitive: 46// it has a different meaning for e.g. Armv8.4 than it has for Armv8.2. 47// Therefore, we rely on Clang, the user interacing tool, to pass on the 48// appropriate crypto options. But here in the backend, crypto has very little 49// meaning anymore. We kept the Crypto definition here for backward 50// compatibility, and now imply features SHA2 and AES, which was the 51// "traditional" meaning of Crypto. 52def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", 53 "Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>; 54 55def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", 56 "Enable ARMv8 CRC-32 checksum instructions">; 57 58def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true", 59 "Enable ARMv8 Reliability, Availability and Serviceability Extensions">; 60 61def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true", 62 "Enable ARMv8.1 Large System Extension (LSE) atomic instructions">; 63 64def FeatureLSE2 : SubtargetFeature<"lse2", "HasLSE2", "true", 65 "Enable ARMv8.4 Large System Extension 2 (LSE2) atomicity rules">; 66 67def FeatureOutlineAtomics : SubtargetFeature<"outline-atomics", "OutlineAtomics", "true", 68 "Enable out of line atomics to support LSE instructions">; 69 70def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true", 71 "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions">; 72 73def FeaturePAN : SubtargetFeature< 74 "pan", "HasPAN", "true", 75 "Enables ARM v8.1 Privileged Access-Never extension">; 76 77def FeatureLOR : SubtargetFeature< 78 "lor", "HasLOR", "true", 79 "Enables ARM v8.1 Limited Ordering Regions extension">; 80 81def FeatureCONTEXTIDREL2 : SubtargetFeature<"CONTEXTIDREL2", "HasCONTEXTIDREL2", 82 "true", "Enable RW operand CONTEXTIDR_EL2" >; 83 84def FeatureVH : SubtargetFeature<"vh", "HasVH", "true", 85 "Enables ARM v8.1 Virtual Host extension", [FeatureCONTEXTIDREL2] >; 86 87def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", 88 "Enable ARMv8 PMUv3 Performance Monitors extension">; 89 90def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true", 91 "Full FP16", [FeatureFPARMv8]>; 92 93def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true", 94 "Enable FP16 FML instructions", [FeatureFullFP16]>; 95 96def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true", 97 "Enable Statistical Profiling extension">; 98 99def FeaturePAN_RWV : SubtargetFeature< 100 "pan-rwv", "HasPAN_RWV", "true", 101 "Enable v8.2 PAN s1e1R and s1e1W Variants", 102 [FeaturePAN]>; 103 104// UAO PState 105def FeaturePsUAO : SubtargetFeature< "uaops", "HasPsUAO", "true", 106 "Enable v8.2 UAO PState">; 107 108def FeatureCCPP : SubtargetFeature<"ccpp", "HasCCPP", 109 "true", "Enable v8.2 data Cache Clean to Point of Persistence" >; 110 111def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true", 112 "Enable Scalable Vector Extension (SVE) instructions", [FeatureFullFP16]>; 113 114// This flag is currently still labeled as Experimental, but when fully 115// implemented this should tell the compiler to use the zeroing pseudos to 116// benefit from the reverse instructions (e.g. SUB vs SUBR) if the inactive 117// lanes are known to be zero. The pseudos will then be expanded using the 118// MOVPRFX instruction to zero the inactive lanes. This feature should only be 119// enabled if MOVPRFX instructions are known to merge with the destructive 120// operations they prefix. 121// 122// This feature could similarly be extended to support cheap merging of _any_ 123// value into the inactive lanes using the MOVPRFX instruction that uses 124// merging-predication. 125def FeatureExperimentalZeroingPseudos 126 : SubtargetFeature<"use-experimental-zeroing-pseudos", 127 "UseExperimentalZeroingPseudos", "true", 128 "Hint to the compiler that the MOVPRFX instruction is " 129 "merged with destructive operations", 130 []>; 131 132def FeatureUseScalarIncVL : SubtargetFeature<"use-scalar-inc-vl", 133 "UseScalarIncVL", "true", "Prefer inc/dec over add+cnt">; 134 135def FeatureSVE2 : SubtargetFeature<"sve2", "HasSVE2", "true", 136 "Enable Scalable Vector Extension 2 (SVE2) instructions", 137 [FeatureSVE, FeatureUseScalarIncVL]>; 138 139def FeatureSVE2AES : SubtargetFeature<"sve2-aes", "HasSVE2AES", "true", 140 "Enable AES SVE2 instructions", [FeatureSVE2, FeatureAES]>; 141 142def FeatureSVE2SM4 : SubtargetFeature<"sve2-sm4", "HasSVE2SM4", "true", 143 "Enable SM4 SVE2 instructions", [FeatureSVE2, FeatureSM4]>; 144 145def FeatureSVE2SHA3 : SubtargetFeature<"sve2-sha3", "HasSVE2SHA3", "true", 146 "Enable SHA3 SVE2 instructions", [FeatureSVE2, FeatureSHA3]>; 147 148def FeatureSVE2BitPerm : SubtargetFeature<"sve2-bitperm", "HasSVE2BitPerm", "true", 149 "Enable bit permutation SVE2 instructions", [FeatureSVE2]>; 150 151def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true", 152 "Has zero-cycle register moves">; 153 154def FeatureZCZeroingGP : SubtargetFeature<"zcz-gp", "HasZeroCycleZeroingGP", "true", 155 "Has zero-cycle zeroing instructions for generic registers">; 156 157def FeatureNoZCZeroingFP : SubtargetFeature<"no-zcz-fp", "HasZeroCycleZeroingFP", "false", 158 "Has no zero-cycle zeroing instructions for FP registers">; 159 160def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true", 161 "Has zero-cycle zeroing instructions", 162 [FeatureZCZeroingGP]>; 163 164/// ... but the floating-point version doesn't quite work in rare cases on older 165/// CPUs. 166def FeatureZCZeroingFPWorkaround : SubtargetFeature<"zcz-fp-workaround", 167 "HasZeroCycleZeroingFPWorkaround", "true", 168 "The zero-cycle floating-point zeroing instruction has a bug">; 169 170def FeatureStrictAlign : SubtargetFeature<"strict-align", 171 "StrictAlign", "true", 172 "Disallow all unaligned memory " 173 "access">; 174 175foreach i = {1-7,9-15,18,20-28,30} in 176 def FeatureReserveX#i : SubtargetFeature<"reserve-x"#i, "ReserveXRegister["#i#"]", "true", 177 "Reserve X"#i#", making it unavailable " 178 "as a GPR">; 179 180foreach i = {8-15,18} in 181 def FeatureCallSavedX#i : SubtargetFeature<"call-saved-x"#i, 182 "CustomCallSavedXRegs["#i#"]", "true", "Make X"#i#" callee saved.">; 183 184def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps", 185 "true", 186 "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">; 187 188def FeaturePredictableSelectIsExpensive : SubtargetFeature< 189 "predictable-select-expensive", "PredictableSelectIsExpensive", "true", 190 "Prefer likely predicted branches over selects">; 191 192def FeatureCustomCheapAsMoveHandling : SubtargetFeature<"custom-cheap-as-move", 193 "CustomAsCheapAsMove", "true", 194 "Use custom handling of cheap instructions">; 195 196def FeatureExynosCheapAsMoveHandling : SubtargetFeature<"exynos-cheap-as-move", 197 "ExynosAsCheapAsMove", "true", 198 "Use Exynos specific handling of cheap instructions", 199 [FeatureCustomCheapAsMoveHandling]>; 200 201def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler", 202 "UsePostRAScheduler", "true", "Schedule again after register allocation">; 203 204def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store", 205 "Misaligned128StoreIsSlow", "true", "Misaligned 128 bit stores are slow">; 206 207def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128", 208 "Paired128IsSlow", "true", "Paired 128 bit loads and stores are slow">; 209 210def FeatureSlowSTRQro : SubtargetFeature<"slow-strqro-store", "STRQroIsSlow", 211 "true", "STR of Q register with register offset is slow">; 212 213def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature< 214 "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern", 215 "true", "Use alternative pattern for sextload convert to f32">; 216 217def FeatureArithmeticBccFusion : SubtargetFeature< 218 "arith-bcc-fusion", "HasArithmeticBccFusion", "true", 219 "CPU fuses arithmetic+bcc operations">; 220 221def FeatureArithmeticCbzFusion : SubtargetFeature< 222 "arith-cbz-fusion", "HasArithmeticCbzFusion", "true", 223 "CPU fuses arithmetic + cbz/cbnz operations">; 224 225def FeatureCmpBccFusion : SubtargetFeature< 226 "cmp-bcc-fusion", "HasCmpBccFusion", "true", 227 "CPU fuses cmp+bcc operations">; 228 229def FeatureFuseAddress : SubtargetFeature< 230 "fuse-address", "HasFuseAddress", "true", 231 "CPU fuses address generation and memory operations">; 232 233def FeatureFuseAES : SubtargetFeature< 234 "fuse-aes", "HasFuseAES", "true", 235 "CPU fuses AES crypto operations">; 236 237def FeatureFuseArithmeticLogic : SubtargetFeature< 238 "fuse-arith-logic", "HasFuseArithmeticLogic", "true", 239 "CPU fuses arithmetic and logic operations">; 240 241def FeatureFuseCCSelect : SubtargetFeature< 242 "fuse-csel", "HasFuseCCSelect", "true", 243 "CPU fuses conditional select operations">; 244 245def FeatureFuseCryptoEOR : SubtargetFeature< 246 "fuse-crypto-eor", "HasFuseCryptoEOR", "true", 247 "CPU fuses AES/PMULL and EOR operations">; 248 249def FeatureFuseLiterals : SubtargetFeature< 250 "fuse-literals", "HasFuseLiterals", "true", 251 "CPU fuses literal generation operations">; 252 253def FeatureDisableLatencySchedHeuristic : SubtargetFeature< 254 "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true", 255 "Disable latency scheduling heuristic">; 256 257def FeatureForce32BitJumpTables 258 : SubtargetFeature<"force-32bit-jump-tables", "Force32BitJumpTables", "true", 259 "Force jump table entries to be 32-bits wide except at MinSize">; 260 261def FeatureRCPC : SubtargetFeature<"rcpc", "HasRCPC", "true", 262 "Enable support for RCPC extension">; 263 264def FeatureUseRSqrt : SubtargetFeature< 265 "use-reciprocal-square-root", "UseRSqrt", "true", 266 "Use the reciprocal square root approximation">; 267 268def FeatureDotProd : SubtargetFeature< 269 "dotprod", "HasDotProd", "true", 270 "Enable dot product support">; 271 272def FeaturePAuth : SubtargetFeature< 273 "pauth", "HasPAuth", "true", 274 "Enable v8.3-A Pointer Authentication extension">; 275 276def FeatureJS : SubtargetFeature< 277 "jsconv", "HasJS", "true", 278 "Enable v8.3-A JavaScript FP conversion instructions", 279 [FeatureFPARMv8]>; 280 281def FeatureCCIDX : SubtargetFeature< 282 "ccidx", "HasCCIDX", "true", 283 "Enable v8.3-A Extend of the CCSIDR number of sets">; 284 285def FeatureComplxNum : SubtargetFeature< 286 "complxnum", "HasComplxNum", "true", 287 "Enable v8.3-A Floating-point complex number support", 288 [FeatureNEON]>; 289 290def FeatureNV : SubtargetFeature< 291 "nv", "HasNV", "true", 292 "Enable v8.4-A Nested Virtualization Enchancement">; 293 294def FeatureMPAM : SubtargetFeature< 295 "mpam", "HasMPAM", "true", 296 "Enable v8.4-A Memory system Partitioning and Monitoring extension">; 297 298def FeatureDIT : SubtargetFeature< 299 "dit", "HasDIT", "true", 300 "Enable v8.4-A Data Independent Timing instructions">; 301 302def FeatureTRACEV8_4 : SubtargetFeature< 303 "tracev8.4", "HasTRACEV8_4", "true", 304 "Enable v8.4-A Trace extension">; 305 306def FeatureAM : SubtargetFeature< 307 "am", "HasAM", "true", 308 "Enable v8.4-A Activity Monitors extension">; 309 310def FeatureAMVS : SubtargetFeature< 311 "amvs", "HasAMVS", "true", 312 "Enable v8.6-A Activity Monitors Virtualization support", 313 [FeatureAM]>; 314 315def FeatureSEL2 : SubtargetFeature< 316 "sel2", "HasSEL2", "true", 317 "Enable v8.4-A Secure Exception Level 2 extension">; 318 319def FeatureTLB_RMI : SubtargetFeature< 320 "tlb-rmi", "HasTLB_RMI", "true", 321 "Enable v8.4-A TLB Range and Maintenance Instructions">; 322 323def FeatureFlagM : SubtargetFeature< 324 "flagm", "HasFlagM", "true", 325 "Enable v8.4-A Flag Manipulation Instructions">; 326 327// 8.4 RCPC enchancements: LDAPR & STLR instructions with Immediate Offset 328def FeatureRCPC_IMMO : SubtargetFeature<"rcpc-immo", "HasRCPC_IMMO", "true", 329 "Enable v8.4-A RCPC instructions with Immediate Offsets", 330 [FeatureRCPC]>; 331 332def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates", 333 "NegativeImmediates", "false", 334 "Convert immediates and instructions " 335 "to their negated or complemented " 336 "equivalent when the immediate does " 337 "not fit in the encoding.">; 338 339def FeatureLSLFast : SubtargetFeature< 340 "lsl-fast", "HasLSLFast", "true", 341 "CPU has a fastpath logical shift of up to 3 places">; 342 343def FeatureAggressiveFMA : 344 SubtargetFeature<"aggressive-fma", 345 "HasAggressiveFMA", 346 "true", 347 "Enable Aggressive FMA for floating-point.">; 348 349def FeatureAltFPCmp : SubtargetFeature<"altnzcv", "HasAlternativeNZCV", "true", 350 "Enable alternative NZCV format for floating point comparisons">; 351 352def FeatureFRInt3264 : SubtargetFeature<"fptoint", "HasFRInt3264", "true", 353 "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to " 354 "an integer (in FP format) forcing it to fit into a 32- or 64-bit int" >; 355 356def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict", 357 "true", "Enable architectural speculation restriction" >; 358 359def FeatureSB : SubtargetFeature<"sb", "HasSB", 360 "true", "Enable v8.5 Speculation Barrier" >; 361 362def FeatureSSBS : SubtargetFeature<"ssbs", "HasSSBS", 363 "true", "Enable Speculative Store Bypass Safe bit" >; 364 365def FeaturePredRes : SubtargetFeature<"predres", "HasPredRes", "true", 366 "Enable v8.5a execution and data prediction invalidation instructions" >; 367 368def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP", 369 "true", "Enable v8.5 Cache Clean to Point of Deep Persistence" >; 370 371def FeatureBranchTargetId : SubtargetFeature<"bti", "HasBTI", 372 "true", "Enable Branch Target Identification" >; 373 374def FeatureRandGen : SubtargetFeature<"rand", "HasRandGen", 375 "true", "Enable Random Number generation instructions" >; 376 377def FeatureMTE : SubtargetFeature<"mte", "HasMTE", 378 "true", "Enable Memory Tagging Extension" >; 379 380def FeatureTRBE : SubtargetFeature<"trbe", "HasTRBE", 381 "true", "Enable Trace Buffer Extension">; 382 383def FeatureETE : SubtargetFeature<"ete", "HasETE", 384 "true", "Enable Embedded Trace Extension", 385 [FeatureTRBE]>; 386 387def FeatureTME : SubtargetFeature<"tme", "HasTME", 388 "true", "Enable Transactional Memory Extension" >; 389 390def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals", 391 "AllowTaggedGlobals", 392 "true", "Use an instruction sequence for taking the address of a global " 393 "that allows a memory tag in the upper address bits">; 394 395def FeatureBF16 : SubtargetFeature<"bf16", "HasBF16", 396 "true", "Enable BFloat16 Extension" >; 397 398def FeatureMatMulInt8 : SubtargetFeature<"i8mm", "HasMatMulInt8", 399 "true", "Enable Matrix Multiply Int8 Extension">; 400 401def FeatureMatMulFP32 : SubtargetFeature<"f32mm", "HasMatMulFP32", 402 "true", "Enable Matrix Multiply FP32 Extension", [FeatureSVE]>; 403 404def FeatureMatMulFP64 : SubtargetFeature<"f64mm", "HasMatMulFP64", 405 "true", "Enable Matrix Multiply FP64 Extension", [FeatureSVE]>; 406 407def FeatureXS : SubtargetFeature<"xs", "HasXS", 408 "true", "Enable Armv8.7-A limited-TLB-maintenance instruction">; 409 410def FeatureWFxT : SubtargetFeature<"wfxt", "HasWFxT", 411 "true", "Enable Armv8.7-A WFET and WFIT instruction">; 412 413def FeatureHCX : SubtargetFeature< 414 "hcx", "HasHCX", "true", "Enable Armv8.7-A HCRX_EL2 system register">; 415 416def FeatureLS64 : SubtargetFeature<"ls64", "HasLS64", 417 "true", "Enable Armv8.7-A LD64B/ST64B Accelerator Extension">; 418 419def FeatureHBC : SubtargetFeature<"hbc", "HasHBC", 420 "true", "Enable Armv8.8-A Hinted Conditional Branches Extension">; 421 422def FeatureMOPS : SubtargetFeature<"mops", "HasMOPS", 423 "true", "Enable Armv8.8-A memcpy and memset acceleration instructions">; 424 425def FeatureBRBE : SubtargetFeature<"brbe", "HasBRBE", 426 "true", "Enable Branch Record Buffer Extension">; 427 428def FeatureSPE_EEF : SubtargetFeature<"spe-eef", "HasSPE_EEF", 429 "true", "Enable extra register in the Statistical Profiling Extension">; 430 431def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps", 432 "true", "Enable fine grained virtualization traps extension">; 433 434def FeatureEnhancedCounterVirtualization : 435 SubtargetFeature<"ecv", "HasEnhancedCounterVirtualization", 436 "true", "Enable enhanced counter virtualization extension">; 437 438def FeatureRME : SubtargetFeature<"rme", "HasRME", 439 "true", "Enable Realm Management Extension">; 440 441// A subset of SVE(2) instructions are legal in Streaming SVE execution mode 442// defined by SME. 443def FeatureStreamingSVE : SubtargetFeature<"streaming-sve", 444 "HasStreamingSVE", "true", 445 "Enable subset of SVE(2) instructions for Streaming SVE execution mode">; 446def FeatureSME : SubtargetFeature<"sme", "HasSME", "true", 447 "Enable Scalable Matrix Extension (SME)", [FeatureStreamingSVE, FeatureBF16]>; 448 449def FeatureSMEF64 : SubtargetFeature<"sme-f64", "HasSMEF64", "true", 450 "Enable Scalable Matrix Extension (SME) F64F64 instructions", [FeatureSME]>; 451 452def FeatureSMEI64 : SubtargetFeature<"sme-i64", "HasSMEI64", "true", 453 "Enable Scalable Matrix Extension (SME) I16I64 instructions", [FeatureSME]>; 454 455def FeatureAppleA7SysReg : SubtargetFeature<"apple-a7-sysreg", "HasAppleA7SysReg", "true", 456 "Apple A7 (the CPU formerly known as Cyclone)">; 457 458def FeatureEL2VMSA : SubtargetFeature<"el2vmsa", "HasEL2VMSA", "true", 459 "Enable Exception Level 2 Virtual Memory System Architecture">; 460 461def FeatureEL3 : SubtargetFeature<"el3", "HasEL3", "true", 462 "Enable Exception Level 3">; 463 464def FeatureFixCortexA53_835769 : SubtargetFeature<"fix-cortex-a53-835769", 465 "FixCortexA53_835769", "true", "Mitigate Cortex-A53 Erratum 835769">; 466 467def FeatureNoBTIAtReturnTwice : SubtargetFeature<"no-bti-at-return-twice", 468 "NoBTIAtReturnTwice", "true", 469 "Don't place a BTI instruction " 470 "after a return-twice">; 471 472//===----------------------------------------------------------------------===// 473// Architectures. 474// 475def HasV8_0aOps : SubtargetFeature<"v8a", "HasV8_0aOps", "true", 476 "Support ARM v8.0a instructions", [FeatureEL2VMSA, FeatureEL3]>; 477 478def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", 479 "Support ARM v8.1a instructions", [HasV8_0aOps, FeatureCRC, FeatureLSE, 480 FeatureRDM, FeaturePAN, FeatureLOR, FeatureVH]>; 481 482def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true", 483 "Support ARM v8.2a instructions", [HasV8_1aOps, FeaturePsUAO, 484 FeaturePAN_RWV, FeatureRAS, FeatureCCPP]>; 485 486def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true", 487 "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC, FeaturePAuth, 488 FeatureJS, FeatureCCIDX, FeatureComplxNum]>; 489 490def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", 491 "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd, 492 FeatureNV, FeatureMPAM, FeatureDIT, 493 FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeatureTLB_RMI, 494 FeatureFlagM, FeatureRCPC_IMMO, FeatureLSE2]>; 495 496def HasV8_5aOps : SubtargetFeature< 497 "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions", 498 [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict, 499 FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist, 500 FeatureBranchTargetId]>; 501 502def HasV8_6aOps : SubtargetFeature< 503 "v8.6a", "HasV8_6aOps", "true", "Support ARM v8.6a instructions", 504 [HasV8_5aOps, FeatureAMVS, FeatureBF16, FeatureFineGrainedTraps, 505 FeatureEnhancedCounterVirtualization, FeatureMatMulInt8]>; 506 507def HasV8_7aOps : SubtargetFeature< 508 "v8.7a", "HasV8_7aOps", "true", "Support ARM v8.7a instructions", 509 [HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX]>; 510 511def HasV8_8aOps : SubtargetFeature< 512 "v8.8a", "HasV8_8aOps", "true", "Support ARM v8.8a instructions", 513 [HasV8_7aOps, FeatureHBC, FeatureMOPS]>; 514 515def HasV9_0aOps : SubtargetFeature< 516 "v9a", "HasV9_0aOps", "true", "Support ARM v9a instructions", 517 [HasV8_5aOps, FeatureSVE2]>; 518 519def HasV9_1aOps : SubtargetFeature< 520 "v9.1a", "HasV9_1aOps", "true", "Support ARM v9.1a instructions", 521 [HasV8_6aOps, HasV9_0aOps]>; 522 523def HasV9_2aOps : SubtargetFeature< 524 "v9.2a", "HasV9_2aOps", "true", "Support ARM v9.2a instructions", 525 [HasV8_7aOps, HasV9_1aOps]>; 526 527def HasV9_3aOps : SubtargetFeature< 528 "v9.3a", "HasV9_3aOps", "true", "Support ARM v9.3a instructions", 529 [HasV8_8aOps, HasV9_2aOps]>; 530 531def HasV8_0rOps : SubtargetFeature< 532 "v8r", "HasV8_0rOps", "true", "Support ARM v8r instructions", 533 [//v8.1 534 FeatureCRC, FeaturePAN, FeatureRDM, FeatureLSE, FeatureCONTEXTIDREL2, 535 //v8.2 536 FeatureRAS, FeaturePsUAO, FeatureCCPP, FeaturePAN_RWV, 537 //v8.3 538 FeatureComplxNum, FeatureCCIDX, FeatureJS, 539 FeaturePAuth, FeatureRCPC, 540 //v8.4 541 FeatureDotProd, FeatureTRACEV8_4, FeatureTLB_RMI, 542 FeatureFlagM, FeatureDIT, FeatureSEL2, FeatureRCPC_IMMO]>; 543 544//===----------------------------------------------------------------------===// 545// Register File Description 546//===----------------------------------------------------------------------===// 547 548include "AArch64RegisterInfo.td" 549include "AArch64RegisterBanks.td" 550include "AArch64CallingConvention.td" 551 552//===----------------------------------------------------------------------===// 553// Instruction Descriptions 554//===----------------------------------------------------------------------===// 555 556include "AArch64Schedule.td" 557include "AArch64InstrInfo.td" 558include "AArch64SchedPredicates.td" 559include "AArch64SchedPredExynos.td" 560include "AArch64Combine.td" 561 562def AArch64InstrInfo : InstrInfo; 563 564//===----------------------------------------------------------------------===// 565// Named operands for MRS/MSR/TLBI/... 566//===----------------------------------------------------------------------===// 567 568include "AArch64SystemOperands.td" 569 570//===----------------------------------------------------------------------===// 571// Access to privileged registers 572//===----------------------------------------------------------------------===// 573 574foreach i = 1-3 in 575def FeatureUseEL#i#ForTP : SubtargetFeature<"tpidr-el"#i, "UseEL"#i#"ForTP", 576 "true", "Permit use of TPIDR_EL"#i#" for the TLS base">; 577 578//===----------------------------------------------------------------------===// 579// Control codegen mitigation against Straight Line Speculation vulnerability. 580//===----------------------------------------------------------------------===// 581 582def FeatureHardenSlsRetBr : SubtargetFeature<"harden-sls-retbr", 583 "HardenSlsRetBr", "true", 584 "Harden against straight line speculation across RET and BR instructions">; 585def FeatureHardenSlsBlr : SubtargetFeature<"harden-sls-blr", 586 "HardenSlsBlr", "true", 587 "Harden against straight line speculation across BLR instructions">; 588def FeatureHardenSlsNoComdat : SubtargetFeature<"harden-sls-nocomdat", 589 "HardenSlsNoComdat", "true", 590 "Generate thunk code for SLS mitigation in the normal text section">; 591 592//===----------------------------------------------------------------------===// 593// AArch64 Processors supported. 594// 595 596//===----------------------------------------------------------------------===// 597// Unsupported features to disable for scheduling models 598//===----------------------------------------------------------------------===// 599 600class AArch64Unsupported { list<Predicate> F; } 601 602def SVEUnsupported : AArch64Unsupported { 603 let F = [HasSVE, HasSVE2, HasSVE2AES, HasSVE2SM4, HasSVE2SHA3, 604 HasSVE2BitPerm, HasSVEorStreamingSVE, HasSVE2orStreamingSVE]; 605} 606 607def PAUnsupported : AArch64Unsupported { 608 let F = [HasPAuth]; 609} 610 611def SMEUnsupported : AArch64Unsupported { 612 let F = [HasSME, HasSMEF64, HasSMEI64]; 613} 614 615include "AArch64SchedA53.td" 616include "AArch64SchedA55.td" 617include "AArch64SchedA57.td" 618include "AArch64SchedCyclone.td" 619include "AArch64SchedFalkor.td" 620include "AArch64SchedKryo.td" 621include "AArch64SchedExynosM3.td" 622include "AArch64SchedExynosM4.td" 623include "AArch64SchedExynosM5.td" 624include "AArch64SchedThunderX.td" 625include "AArch64SchedThunderX2T99.td" 626include "AArch64SchedA64FX.td" 627include "AArch64SchedThunderX3T110.td" 628include "AArch64SchedTSV110.td" 629 630def TuneA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35", 631 "Cortex-A35 ARM processors">; 632 633def TuneA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", 634 "Cortex-A53 ARM processors", [ 635 FeatureFuseAES, 636 FeatureBalanceFPOps, 637 FeatureCustomCheapAsMoveHandling, 638 FeaturePostRAScheduler]>; 639 640def TuneA55 : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55", 641 "Cortex-A55 ARM processors", [ 642 FeatureFuseAES, 643 FeaturePostRAScheduler, 644 FeatureFuseAddress]>; 645 646def TuneA510 : SubtargetFeature<"a510", "ARMProcFamily", "CortexA510", 647 "Cortex-A510 ARM processors", [ 648 FeatureFuseAES, 649 FeaturePostRAScheduler 650 ]>; 651 652def TuneA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", 653 "Cortex-A57 ARM processors", [ 654 FeatureFuseAES, 655 FeatureBalanceFPOps, 656 FeatureCustomCheapAsMoveHandling, 657 FeatureFuseLiterals, 658 FeaturePostRAScheduler, 659 FeaturePredictableSelectIsExpensive]>; 660 661def TuneA65 : SubtargetFeature<"a65", "ARMProcFamily", "CortexA65", 662 "Cortex-A65 ARM processors", [ 663 FeatureFuseAES, 664 FeatureFuseAddress, 665 FeatureFuseLiterals]>; 666 667def TuneA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72", 668 "Cortex-A72 ARM processors", [ 669 FeatureFuseAES, 670 FeatureFuseLiterals]>; 671 672def TuneA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73", 673 "Cortex-A73 ARM processors", [ 674 FeatureFuseAES]>; 675 676def TuneA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75", 677 "Cortex-A75 ARM processors", [ 678 FeatureFuseAES]>; 679 680def TuneA76 : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76", 681 "Cortex-A76 ARM processors", [ 682 FeatureFuseAES]>; 683 684def TuneA77 : SubtargetFeature<"a77", "ARMProcFamily", "CortexA77", 685 "Cortex-A77 ARM processors", [ 686 FeatureCmpBccFusion, 687 FeatureFuseAES]>; 688 689def TuneA78 : SubtargetFeature<"a78", "ARMProcFamily", "CortexA78", 690 "Cortex-A78 ARM processors", [ 691 FeatureCmpBccFusion, 692 FeatureFuseAES, 693 FeaturePostRAScheduler]>; 694 695def TuneA78C : SubtargetFeature<"a78c", "ARMProcFamily", 696 "CortexA78C", 697 "Cortex-A78C ARM processors", [ 698 FeatureCmpBccFusion, 699 FeatureFuseAES, 700 FeaturePostRAScheduler]>; 701 702def TuneA710 : SubtargetFeature<"a710", "ARMProcFamily", "CortexA710", 703 "Cortex-A710 ARM processors", [ 704 FeatureFuseAES, 705 FeaturePostRAScheduler, 706 FeatureCmpBccFusion]>; 707 708def TuneR82 : SubtargetFeature<"cortex-r82", "ARMProcFamily", 709 "CortexR82", 710 "Cortex-R82 ARM processors", [ 711 FeaturePostRAScheduler]>; 712 713def TuneX1 : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1", 714 "Cortex-X1 ARM processors", [ 715 FeatureCmpBccFusion, 716 FeatureFuseAES, 717 FeaturePostRAScheduler]>; 718 719def TuneX2 : SubtargetFeature<"cortex-x2", "ARMProcFamily", "CortexX2", 720 "Cortex-X2 ARM processors", [ 721 FeatureFuseAES, 722 FeaturePostRAScheduler, 723 FeatureCmpBccFusion]>; 724 725def TuneA64FX : SubtargetFeature<"a64fx", "ARMProcFamily", "A64FX", 726 "Fujitsu A64FX processors", [ 727 FeaturePostRAScheduler, 728 FeatureAggressiveFMA, 729 FeatureArithmeticBccFusion, 730 FeaturePredictableSelectIsExpensive 731 ]>; 732 733def TuneCarmel : SubtargetFeature<"carmel", "ARMProcFamily", "Carmel", 734 "Nvidia Carmel processors">; 735 736// Note that cyclone does not fuse AES instructions, but newer apple chips do 737// perform the fusion and cyclone is used by default when targetting apple OSes. 738def TuneAppleA7 : SubtargetFeature<"apple-a7", "ARMProcFamily", "AppleA7", 739 "Apple A7 (the CPU formerly known as Cyclone)", [ 740 FeatureAlternateSExtLoadCVTF32Pattern, 741 FeatureArithmeticBccFusion, 742 FeatureArithmeticCbzFusion, 743 FeatureDisableLatencySchedHeuristic, 744 FeatureFuseAES, FeatureFuseCryptoEOR, 745 FeatureZCRegMove, 746 FeatureZCZeroing, 747 FeatureZCZeroingFPWorkaround] 748 >; 749 750def TuneAppleA10 : SubtargetFeature<"apple-a10", "ARMProcFamily", "AppleA10", 751 "Apple A10", [ 752 FeatureAlternateSExtLoadCVTF32Pattern, 753 FeatureArithmeticBccFusion, 754 FeatureArithmeticCbzFusion, 755 FeatureDisableLatencySchedHeuristic, 756 FeatureFuseAES, 757 FeatureFuseCryptoEOR, 758 FeatureZCRegMove, 759 FeatureZCZeroing] 760 >; 761 762def TuneAppleA11 : SubtargetFeature<"apple-a11", "ARMProcFamily", "AppleA11", 763 "Apple A11", [ 764 FeatureAlternateSExtLoadCVTF32Pattern, 765 FeatureArithmeticBccFusion, 766 FeatureArithmeticCbzFusion, 767 FeatureDisableLatencySchedHeuristic, 768 FeatureFuseAES, 769 FeatureFuseCryptoEOR, 770 FeatureZCRegMove, 771 FeatureZCZeroing] 772 >; 773 774def TuneAppleA12 : SubtargetFeature<"apple-a12", "ARMProcFamily", "AppleA12", 775 "Apple A12", [ 776 FeatureAlternateSExtLoadCVTF32Pattern, 777 FeatureArithmeticBccFusion, 778 FeatureArithmeticCbzFusion, 779 FeatureDisableLatencySchedHeuristic, 780 FeatureFuseAES, 781 FeatureFuseCryptoEOR, 782 FeatureZCRegMove, 783 FeatureZCZeroing] 784 >; 785 786def TuneAppleA13 : SubtargetFeature<"apple-a13", "ARMProcFamily", "AppleA13", 787 "Apple A13", [ 788 FeatureAlternateSExtLoadCVTF32Pattern, 789 FeatureArithmeticBccFusion, 790 FeatureArithmeticCbzFusion, 791 FeatureDisableLatencySchedHeuristic, 792 FeatureFuseAES, 793 FeatureFuseCryptoEOR, 794 FeatureZCRegMove, 795 FeatureZCZeroing] 796 >; 797 798def TuneAppleA14 : SubtargetFeature<"apple-a14", "ARMProcFamily", "AppleA14", 799 "Apple A14", [ 800 FeatureAggressiveFMA, 801 FeatureAlternateSExtLoadCVTF32Pattern, 802 FeatureArithmeticBccFusion, 803 FeatureArithmeticCbzFusion, 804 FeatureDisableLatencySchedHeuristic, 805 FeatureFuseAddress, 806 FeatureFuseAES, 807 FeatureFuseArithmeticLogic, 808 FeatureFuseCCSelect, 809 FeatureFuseCryptoEOR, 810 FeatureFuseLiterals, 811 FeatureZCRegMove, 812 FeatureZCZeroing]>; 813 814def TuneExynosM3 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3", 815 "Samsung Exynos-M3 processors", 816 [FeatureExynosCheapAsMoveHandling, 817 FeatureForce32BitJumpTables, 818 FeatureFuseAddress, 819 FeatureFuseAES, 820 FeatureFuseCCSelect, 821 FeatureFuseLiterals, 822 FeatureLSLFast, 823 FeaturePostRAScheduler, 824 FeaturePredictableSelectIsExpensive]>; 825 826def TuneExynosM4 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3", 827 "Samsung Exynos-M3 processors", 828 [FeatureArithmeticBccFusion, 829 FeatureArithmeticCbzFusion, 830 FeatureExynosCheapAsMoveHandling, 831 FeatureForce32BitJumpTables, 832 FeatureFuseAddress, 833 FeatureFuseAES, 834 FeatureFuseArithmeticLogic, 835 FeatureFuseCCSelect, 836 FeatureFuseLiterals, 837 FeatureLSLFast, 838 FeaturePostRAScheduler, 839 FeatureZCZeroing]>; 840 841def TuneKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo", 842 "Qualcomm Kryo processors", [ 843 FeatureCustomCheapAsMoveHandling, 844 FeaturePostRAScheduler, 845 FeaturePredictableSelectIsExpensive, 846 FeatureZCZeroing, 847 FeatureLSLFast] 848 >; 849 850def TuneFalkor : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor", 851 "Qualcomm Falkor processors", [ 852 FeatureCustomCheapAsMoveHandling, 853 FeaturePostRAScheduler, 854 FeaturePredictableSelectIsExpensive, 855 FeatureZCZeroing, 856 FeatureLSLFast, 857 FeatureSlowSTRQro 858 ]>; 859 860def TuneNeoverseE1 : SubtargetFeature<"neoversee1", "ARMProcFamily", "NeoverseE1", 861 "Neoverse E1 ARM processors", [ 862 FeaturePostRAScheduler, 863 FeatureFuseAES 864 ]>; 865 866def TuneNeoverseN1 : SubtargetFeature<"neoversen1", "ARMProcFamily", "NeoverseN1", 867 "Neoverse N1 ARM processors", [ 868 FeaturePostRAScheduler, 869 FeatureFuseAES 870 ]>; 871 872def TuneNeoverseN2 : SubtargetFeature<"neoversen2", "ARMProcFamily", "NeoverseN2", 873 "Neoverse N2 ARM processors", [ 874 FeaturePostRAScheduler, 875 FeatureFuseAES 876 ]>; 877def TuneNeoverse512TVB : SubtargetFeature<"neoverse512tvb", "ARMProcFamily", "Neoverse512TVB", 878 "Neoverse 512-TVB ARM processors", [ 879 FeaturePostRAScheduler, 880 FeatureFuseAES 881 ]>; 882 883def TuneNeoverseV1 : SubtargetFeature<"neoversev1", "ARMProcFamily", "NeoverseV1", 884 "Neoverse V1 ARM processors", [ 885 FeatureFuseAES, 886 FeaturePostRAScheduler]>; 887 888def TuneSaphira : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira", 889 "Qualcomm Saphira processors", [ 890 FeatureCustomCheapAsMoveHandling, 891 FeaturePostRAScheduler, 892 FeaturePredictableSelectIsExpensive, 893 FeatureZCZeroing, 894 FeatureLSLFast]>; 895 896def TuneThunderX2T99 : SubtargetFeature<"thunderx2t99", "ARMProcFamily", "ThunderX2T99", 897 "Cavium ThunderX2 processors", [ 898 FeatureAggressiveFMA, 899 FeatureArithmeticBccFusion, 900 FeaturePostRAScheduler, 901 FeaturePredictableSelectIsExpensive]>; 902 903def TuneThunderX3T110 : SubtargetFeature<"thunderx3t110", "ARMProcFamily", 904 "ThunderX3T110", 905 "Marvell ThunderX3 processors", [ 906 FeatureAggressiveFMA, 907 FeatureArithmeticBccFusion, 908 FeaturePostRAScheduler, 909 FeaturePredictableSelectIsExpensive, 910 FeatureBalanceFPOps, 911 FeatureStrictAlign]>; 912 913def TuneThunderX : SubtargetFeature<"thunderx", "ARMProcFamily", "ThunderX", 914 "Cavium ThunderX processors", [ 915 FeaturePostRAScheduler, 916 FeaturePredictableSelectIsExpensive]>; 917 918def TuneThunderXT88 : SubtargetFeature<"thunderxt88", "ARMProcFamily", 919 "ThunderXT88", 920 "Cavium ThunderX processors", [ 921 FeaturePostRAScheduler, 922 FeaturePredictableSelectIsExpensive]>; 923 924def TuneThunderXT81 : SubtargetFeature<"thunderxt81", "ARMProcFamily", 925 "ThunderXT81", 926 "Cavium ThunderX processors", [ 927 FeaturePostRAScheduler, 928 FeaturePredictableSelectIsExpensive]>; 929 930def TuneThunderXT83 : SubtargetFeature<"thunderxt83", "ARMProcFamily", 931 "ThunderXT83", 932 "Cavium ThunderX processors", [ 933 FeaturePostRAScheduler, 934 FeaturePredictableSelectIsExpensive]>; 935 936def TuneTSV110 : SubtargetFeature<"tsv110", "ARMProcFamily", "TSV110", 937 "HiSilicon TS-V110 processors", [ 938 FeatureCustomCheapAsMoveHandling, 939 FeatureFuseAES, 940 FeaturePostRAScheduler]>; 941 942 943def ProcessorFeatures { 944 list<SubtargetFeature> A53 = [HasV8_0aOps, FeatureCRC, FeatureCrypto, 945 FeatureFPARMv8, FeatureNEON, FeaturePerfMon]; 946 list<SubtargetFeature> A55 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 947 FeatureNEON, FeatureFullFP16, FeatureDotProd, 948 FeatureRCPC, FeaturePerfMon]; 949 list<SubtargetFeature> A510 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon, 950 FeatureMatMulInt8, FeatureBF16, FeatureAM, 951 FeatureMTE, FeatureETE, FeatureSVE2BitPerm, 952 FeatureFP16FML]; 953 list<SubtargetFeature> A65 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 954 FeatureNEON, FeatureFullFP16, FeatureDotProd, 955 FeatureRCPC, FeatureSSBS, FeatureRAS]; 956 list<SubtargetFeature> A76 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 957 FeatureNEON, FeatureFullFP16, FeatureDotProd, 958 FeatureRCPC, FeatureSSBS]; 959 list<SubtargetFeature> A77 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 960 FeatureNEON, FeatureFullFP16, FeatureDotProd, 961 FeatureRCPC, FeatureSSBS]; 962 list<SubtargetFeature> A78 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 963 FeatureNEON, FeatureFullFP16, FeatureDotProd, 964 FeatureRCPC, FeaturePerfMon, FeatureSPE, 965 FeatureSSBS]; 966 list<SubtargetFeature> A78C = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 967 FeatureNEON, FeatureFullFP16, FeatureDotProd, 968 FeatureFlagM, FeatureFP16FML, FeaturePAuth, 969 FeaturePerfMon, FeatureRCPC, FeatureSPE, 970 FeatureSSBS]; 971 list<SubtargetFeature> A710 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon, 972 FeatureETE, FeatureMTE, FeatureFP16FML, 973 FeatureSVE2BitPerm, FeatureBF16, FeatureMatMulInt8]; 974 list<SubtargetFeature> R82 = [HasV8_0rOps, FeaturePerfMon, FeatureFullFP16, 975 FeatureFP16FML, FeatureSSBS, FeaturePredRes, 976 FeatureSB, FeatureSpecRestrict]; 977 list<SubtargetFeature> X1 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 978 FeatureNEON, FeatureRCPC, FeaturePerfMon, 979 FeatureSPE, FeatureFullFP16, FeatureDotProd, 980 FeatureSSBS]; 981 list<SubtargetFeature> X1C = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 982 FeatureNEON, FeatureRCPC, FeaturePerfMon, 983 FeatureSPE, FeatureFullFP16, FeatureDotProd, 984 FeaturePAuth, FeatureSSBS]; 985 list<SubtargetFeature> X2 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon, 986 FeatureMatMulInt8, FeatureBF16, FeatureAM, 987 FeatureMTE, FeatureETE, FeatureSVE2BitPerm, 988 FeatureFP16FML]; 989 list<SubtargetFeature> A64FX = [HasV8_2aOps, FeatureFPARMv8, FeatureNEON, 990 FeatureSHA2, FeaturePerfMon, FeatureFullFP16, 991 FeatureSVE, FeatureComplxNum]; 992 list<SubtargetFeature> Carmel = [HasV8_2aOps, FeatureNEON, FeatureCrypto, 993 FeatureFullFP16]; 994 list<SubtargetFeature> AppleA7 = [HasV8_0aOps, FeatureCrypto, FeatureFPARMv8, 995 FeatureNEON,FeaturePerfMon, FeatureAppleA7SysReg]; 996 list<SubtargetFeature> AppleA10 = [HasV8_0aOps, FeatureCrypto, FeatureFPARMv8, 997 FeatureNEON, FeaturePerfMon, FeatureCRC, 998 FeatureRDM, FeaturePAN, FeatureLOR, FeatureVH]; 999 list<SubtargetFeature> AppleA11 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1000 FeatureNEON, FeaturePerfMon, FeatureFullFP16]; 1001 list<SubtargetFeature> AppleA12 = [HasV8_3aOps, FeatureCrypto, FeatureFPARMv8, 1002 FeatureNEON, FeaturePerfMon, FeatureFullFP16]; 1003 list<SubtargetFeature> AppleA13 = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8, 1004 FeatureNEON, FeaturePerfMon, FeatureFullFP16, 1005 FeatureFP16FML, FeatureSHA3]; 1006 list<SubtargetFeature> AppleA14 = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8, 1007 FeatureNEON, FeaturePerfMon, FeatureFRInt3264, 1008 FeatureSpecRestrict, FeatureSSBS, FeatureSB, 1009 FeaturePredRes, FeatureCacheDeepPersist, 1010 FeatureFullFP16, FeatureFP16FML, FeatureSHA3, 1011 FeatureAltFPCmp]; 1012 list<SubtargetFeature> ExynosM3 = [HasV8_0aOps, FeatureCRC, FeatureCrypto, 1013 FeaturePerfMon]; 1014 list<SubtargetFeature> ExynosM4 = [HasV8_2aOps, FeatureCrypto, FeatureDotProd, 1015 FeatureFullFP16, FeaturePerfMon]; 1016 list<SubtargetFeature> Falkor = [HasV8_0aOps, FeatureCRC, FeatureCrypto, 1017 FeatureFPARMv8, FeatureNEON, FeaturePerfMon, 1018 FeatureRDM]; 1019 list<SubtargetFeature> NeoverseE1 = [HasV8_2aOps, FeatureCrypto, FeatureDotProd, 1020 FeatureFPARMv8, FeatureFullFP16, FeatureNEON, 1021 FeatureRCPC, FeatureSSBS]; 1022 list<SubtargetFeature> NeoverseN1 = [HasV8_2aOps, FeatureCrypto, FeatureDotProd, 1023 FeatureFPARMv8, FeatureFullFP16, FeatureNEON, 1024 FeatureRCPC, FeatureSPE, FeatureSSBS]; 1025 list<SubtargetFeature> NeoverseN2 = [HasV8_5aOps, FeatureBF16, FeatureETE, 1026 FeatureMatMulInt8, FeatureMTE, FeatureSVE2, 1027 FeatureSVE2BitPerm, FeatureTRBE, FeatureCrypto]; 1028 list<SubtargetFeature> Neoverse512TVB = [HasV8_4aOps, FeatureBF16, FeatureCacheDeepPersist, 1029 FeatureCrypto, FeatureFPARMv8, FeatureFP16FML, 1030 FeatureFullFP16, FeatureMatMulInt8, FeatureNEON, 1031 FeaturePerfMon, FeatureRandGen, FeatureSPE, 1032 FeatureSSBS, FeatureSVE]; 1033 list<SubtargetFeature> NeoverseV1 = [HasV8_4aOps, FeatureBF16, FeatureCacheDeepPersist, 1034 FeatureCrypto, FeatureFPARMv8, FeatureFP16FML, 1035 FeatureFullFP16, FeatureMatMulInt8, FeatureNEON, 1036 FeaturePerfMon, FeatureRandGen, FeatureSPE, 1037 FeatureSSBS, FeatureSVE]; 1038 list<SubtargetFeature> Saphira = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8, 1039 FeatureNEON, FeatureSPE, FeaturePerfMon]; 1040 list<SubtargetFeature> ThunderX = [HasV8_0aOps, FeatureCRC, FeatureCrypto, 1041 FeatureFPARMv8, FeaturePerfMon, FeatureNEON]; 1042 list<SubtargetFeature> ThunderX2T99 = [HasV8_1aOps, FeatureCRC, FeatureCrypto, 1043 FeatureFPARMv8, FeatureNEON, FeatureLSE]; 1044 list<SubtargetFeature> ThunderX3T110 = [HasV8_3aOps, FeatureCRC, FeatureCrypto, 1045 FeatureFPARMv8, FeatureNEON, FeatureLSE, 1046 FeaturePAuth, FeaturePerfMon]; 1047 list<SubtargetFeature> TSV110 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1048 FeatureNEON, FeaturePerfMon, FeatureSPE, 1049 FeatureFullFP16, FeatureFP16FML, FeatureDotProd]; 1050 1051 // ETE and TRBE are future architecture extensions. We temporarily enable them 1052 // by default for users targeting generic AArch64. The extensions do not 1053 // affect code generated by the compiler and can be used only by explicitly 1054 // mentioning the new system register names in assembly. 1055 list<SubtargetFeature> Generic = [FeatureFPARMv8, FeatureNEON, FeaturePerfMon, FeatureETE]; 1056} 1057 1058 1059def : ProcessorModel<"generic", CortexA55Model, ProcessorFeatures.Generic, 1060 [FeatureFuseAES, FeaturePostRAScheduler]>; 1061def : ProcessorModel<"cortex-a35", CortexA53Model, ProcessorFeatures.A53, 1062 [TuneA35]>; 1063def : ProcessorModel<"cortex-a34", CortexA53Model, ProcessorFeatures.A53, 1064 [TuneA35]>; 1065def : ProcessorModel<"cortex-a53", CortexA53Model, ProcessorFeatures.A53, 1066 [TuneA53]>; 1067def : ProcessorModel<"cortex-a55", CortexA55Model, ProcessorFeatures.A55, 1068 [TuneA55]>; 1069def : ProcessorModel<"cortex-a510", CortexA55Model, ProcessorFeatures.A510, 1070 [TuneA510]>; 1071def : ProcessorModel<"cortex-a57", CortexA57Model, ProcessorFeatures.A53, 1072 [TuneA57]>; 1073def : ProcessorModel<"cortex-a65", CortexA53Model, ProcessorFeatures.A65, 1074 [TuneA65]>; 1075def : ProcessorModel<"cortex-a65ae", CortexA53Model, ProcessorFeatures.A65, 1076 [TuneA65]>; 1077def : ProcessorModel<"cortex-a72", CortexA57Model, ProcessorFeatures.A53, 1078 [TuneA72]>; 1079def : ProcessorModel<"cortex-a73", CortexA57Model, ProcessorFeatures.A53, 1080 [TuneA73]>; 1081def : ProcessorModel<"cortex-a75", CortexA57Model, ProcessorFeatures.A55, 1082 [TuneA75]>; 1083def : ProcessorModel<"cortex-a76", CortexA57Model, ProcessorFeatures.A76, 1084 [TuneA76]>; 1085def : ProcessorModel<"cortex-a76ae", CortexA57Model, ProcessorFeatures.A76, 1086 [TuneA76]>; 1087def : ProcessorModel<"cortex-a77", CortexA57Model, ProcessorFeatures.A77, 1088 [TuneA77]>; 1089def : ProcessorModel<"cortex-a78", CortexA57Model, ProcessorFeatures.A78, 1090 [TuneA78]>; 1091def : ProcessorModel<"cortex-a78c", CortexA57Model, ProcessorFeatures.A78C, 1092 [TuneA78C]>; 1093def : ProcessorModel<"cortex-a710", CortexA57Model, ProcessorFeatures.A710, 1094 [TuneA710]>; 1095def : ProcessorModel<"cortex-r82", CortexA55Model, ProcessorFeatures.R82, 1096 [TuneR82]>; 1097def : ProcessorModel<"cortex-x1", CortexA57Model, ProcessorFeatures.X1, 1098 [TuneX1]>; 1099def : ProcessorModel<"cortex-x1c", CortexA57Model, ProcessorFeatures.X1C, 1100 [TuneX1]>; 1101def : ProcessorModel<"cortex-x2", CortexA57Model, ProcessorFeatures.X2, 1102 [TuneX2]>; 1103def : ProcessorModel<"neoverse-e1", CortexA53Model, 1104 ProcessorFeatures.NeoverseE1, [TuneNeoverseE1]>; 1105def : ProcessorModel<"neoverse-n1", CortexA57Model, 1106 ProcessorFeatures.NeoverseN1, [TuneNeoverseN1]>; 1107def : ProcessorModel<"neoverse-n2", CortexA57Model, 1108 ProcessorFeatures.NeoverseN2, [TuneNeoverseN2]>; 1109def : ProcessorModel<"neoverse-512tvb", CortexA57Model, 1110 ProcessorFeatures.Neoverse512TVB, [TuneNeoverse512TVB]>; 1111def : ProcessorModel<"neoverse-v1", CortexA57Model, 1112 ProcessorFeatures.NeoverseV1, [TuneNeoverseV1]>; 1113def : ProcessorModel<"exynos-m3", ExynosM3Model, ProcessorFeatures.ExynosM3, 1114 [TuneExynosM3]>; 1115def : ProcessorModel<"exynos-m4", ExynosM4Model, ProcessorFeatures.ExynosM4, 1116 [TuneExynosM4]>; 1117def : ProcessorModel<"exynos-m5", ExynosM5Model, ProcessorFeatures.ExynosM4, 1118 [TuneExynosM4]>; 1119def : ProcessorModel<"falkor", FalkorModel, ProcessorFeatures.Falkor, 1120 [TuneFalkor]>; 1121def : ProcessorModel<"saphira", FalkorModel, ProcessorFeatures.Saphira, 1122 [TuneSaphira]>; 1123def : ProcessorModel<"kryo", KryoModel, ProcessorFeatures.A53, [TuneKryo]>; 1124 1125// Cavium ThunderX/ThunderX T8X Processors 1126def : ProcessorModel<"thunderx", ThunderXT8XModel, ProcessorFeatures.ThunderX, 1127 [TuneThunderX]>; 1128def : ProcessorModel<"thunderxt88", ThunderXT8XModel, 1129 ProcessorFeatures.ThunderX, [TuneThunderXT88]>; 1130def : ProcessorModel<"thunderxt81", ThunderXT8XModel, 1131 ProcessorFeatures.ThunderX, [TuneThunderXT81]>; 1132def : ProcessorModel<"thunderxt83", ThunderXT8XModel, 1133 ProcessorFeatures.ThunderX, [TuneThunderXT83]>; 1134// Cavium ThunderX2T9X Processors. Formerly Broadcom Vulcan. 1135def : ProcessorModel<"thunderx2t99", ThunderX2T99Model, 1136 ProcessorFeatures.ThunderX2T99, [TuneThunderX2T99]>; 1137// Marvell ThunderX3T110 Processors. 1138def : ProcessorModel<"thunderx3t110", ThunderX3T110Model, 1139 ProcessorFeatures.ThunderX3T110, [TuneThunderX3T110]>; 1140def : ProcessorModel<"tsv110", TSV110Model, ProcessorFeatures.TSV110, 1141 [TuneTSV110]>; 1142 1143// Support cyclone as an alias for apple-a7 so we can still LTO old bitcode. 1144def : ProcessorModel<"cyclone", CycloneModel, ProcessorFeatures.AppleA7, 1145 [TuneAppleA7]>; 1146 1147// iPhone and iPad CPUs 1148def : ProcessorModel<"apple-a7", CycloneModel, ProcessorFeatures.AppleA7, 1149 [TuneAppleA7]>; 1150def : ProcessorModel<"apple-a8", CycloneModel, ProcessorFeatures.AppleA7, 1151 [TuneAppleA7]>; 1152def : ProcessorModel<"apple-a9", CycloneModel, ProcessorFeatures.AppleA7, 1153 [TuneAppleA7]>; 1154def : ProcessorModel<"apple-a10", CycloneModel, ProcessorFeatures.AppleA10, 1155 [TuneAppleA10]>; 1156def : ProcessorModel<"apple-a11", CycloneModel, ProcessorFeatures.AppleA11, 1157 [TuneAppleA11]>; 1158def : ProcessorModel<"apple-a12", CycloneModel, ProcessorFeatures.AppleA12, 1159 [TuneAppleA12]>; 1160def : ProcessorModel<"apple-a13", CycloneModel, ProcessorFeatures.AppleA13, 1161 [TuneAppleA13]>; 1162def : ProcessorModel<"apple-a14", CycloneModel, ProcessorFeatures.AppleA14, 1163 [TuneAppleA14]>; 1164 1165// Mac CPUs 1166def : ProcessorModel<"apple-m1", CycloneModel, ProcessorFeatures.AppleA14, 1167 [TuneAppleA14]>; 1168 1169// watch CPUs. 1170def : ProcessorModel<"apple-s4", CycloneModel, ProcessorFeatures.AppleA12, 1171 [TuneAppleA12]>; 1172def : ProcessorModel<"apple-s5", CycloneModel, ProcessorFeatures.AppleA12, 1173 [TuneAppleA12]>; 1174 1175// Alias for the latest Apple processor model supported by LLVM. 1176def : ProcessorModel<"apple-latest", CycloneModel, ProcessorFeatures.AppleA14, 1177 [TuneAppleA14]>; 1178 1179// Fujitsu A64FX 1180def : ProcessorModel<"a64fx", A64FXModel, ProcessorFeatures.A64FX, 1181 [TuneA64FX]>; 1182 1183// Nvidia Carmel 1184def : ProcessorModel<"carmel", NoSchedModel, ProcessorFeatures.Carmel, 1185 [TuneCarmel]>; 1186 1187//===----------------------------------------------------------------------===// 1188// Assembly parser 1189//===----------------------------------------------------------------------===// 1190 1191def GenericAsmParserVariant : AsmParserVariant { 1192 int Variant = 0; 1193 string Name = "generic"; 1194 string BreakCharacters = "."; 1195 string TokenizingCharacters = "[]*!/"; 1196} 1197 1198def AppleAsmParserVariant : AsmParserVariant { 1199 int Variant = 1; 1200 string Name = "apple-neon"; 1201 string BreakCharacters = "."; 1202 string TokenizingCharacters = "[]*!/"; 1203} 1204 1205//===----------------------------------------------------------------------===// 1206// Assembly printer 1207//===----------------------------------------------------------------------===// 1208// AArch64 Uses the MC printer for asm output, so make sure the TableGen 1209// AsmWriter bits get associated with the correct class. 1210def GenericAsmWriter : AsmWriter { 1211 string AsmWriterClassName = "InstPrinter"; 1212 int PassSubtarget = 1; 1213 int Variant = 0; 1214 bit isMCAsmWriter = 1; 1215} 1216 1217def AppleAsmWriter : AsmWriter { 1218 let AsmWriterClassName = "AppleInstPrinter"; 1219 int PassSubtarget = 1; 1220 int Variant = 1; 1221 int isMCAsmWriter = 1; 1222} 1223 1224//===----------------------------------------------------------------------===// 1225// Target Declaration 1226//===----------------------------------------------------------------------===// 1227 1228def AArch64 : Target { 1229 let InstructionSet = AArch64InstrInfo; 1230 let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant]; 1231 let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter]; 1232 let AllowRegisterRenaming = 1; 1233} 1234 1235//===----------------------------------------------------------------------===// 1236// Pfm Counters 1237//===----------------------------------------------------------------------===// 1238 1239include "AArch64PfmCounters.td" 1240