1//=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// 10//===----------------------------------------------------------------------===// 11 12//===----------------------------------------------------------------------===// 13// Target-independent interfaces which we are implementing. 14//===----------------------------------------------------------------------===// 15 16include "llvm/Target/Target.td" 17 18//===----------------------------------------------------------------------===// 19// AArch64 Subtarget features. 20// 21 22// Each SubtargetFeature which corresponds to an Arm Architecture feature should 23// be annotated with the respective FEAT_ feature name from the Architecture 24// Reference Manual. If a SubtargetFeature enables instructions from multiple 25// Arm Architecture Features, it should list all the relevant features. Not all 26// FEAT_ features have a corresponding SubtargetFeature. 27 28def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true", 29 "Enable ARMv8 FP (FEAT_FP)">; 30 31def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", 32 "Enable Advanced SIMD instructions (FEAT_AdvSIMD)", [FeatureFPARMv8]>; 33 34def FeatureSM4 : SubtargetFeature< 35 "sm4", "HasSM4", "true", 36 "Enable SM3 and SM4 support (FEAT_SM4, FEAT_SM3)", [FeatureNEON]>; 37 38def FeatureSHA2 : SubtargetFeature< 39 "sha2", "HasSHA2", "true", 40 "Enable SHA1 and SHA256 support (FEAT_SHA1, FEAT_SHA256)", [FeatureNEON]>; 41 42def FeatureSHA3 : SubtargetFeature< 43 "sha3", "HasSHA3", "true", 44 "Enable SHA512 and SHA3 support (FEAT_SHA3, FEAT_SHA512)", [FeatureNEON, FeatureSHA2]>; 45 46def FeatureAES : SubtargetFeature< 47 "aes", "HasAES", "true", 48 "Enable AES support (FEAT_AES, FEAT_PMULL)", [FeatureNEON]>; 49 50// Crypto has been split up and any combination is now valid (see the 51// crypto definitions above). Also, crypto is now context sensitive: 52// it has a different meaning for e.g. Armv8.4 than it has for Armv8.2. 53// Therefore, we rely on Clang, the user interfacing tool, to pass on the 54// appropriate crypto options. But here in the backend, crypto has very little 55// meaning anymore. We kept the Crypto definition here for backward 56// compatibility, and now imply features SHA2 and AES, which was the 57// "traditional" meaning of Crypto. 58def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", 59 "Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>; 60 61def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", 62 "Enable ARMv8 CRC-32 checksum instructions (FEAT_CRC32)">; 63 64def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true", 65 "Enable ARMv8 Reliability, Availability and Serviceability Extensions (FEAT_RAS, FEAT_RASv1p1)">; 66 67def FeatureRASv2 : SubtargetFeature<"rasv2", "HasRASv2", "true", 68 "Enable ARMv8.9-A Reliability, Availability and Serviceability Extensions (FEAT_RASv2)", 69 [FeatureRAS]>; 70 71def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true", 72 "Enable ARMv8.1 Large System Extension (LSE) atomic instructions (FEAT_LSE)">; 73 74def FeatureLSE2 : SubtargetFeature<"lse2", "HasLSE2", "true", 75 "Enable ARMv8.4 Large System Extension 2 (LSE2) atomicity rules (FEAT_LSE2)">; 76 77def FeatureOutlineAtomics : SubtargetFeature<"outline-atomics", "OutlineAtomics", "true", 78 "Enable out of line atomics to support LSE instructions">; 79 80def FeatureFMV : SubtargetFeature<"fmv", "HasFMV", "true", 81 "Enable Function Multi Versioning support.">; 82 83def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true", 84 "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions (FEAT_RDM)">; 85 86def FeaturePAN : SubtargetFeature< 87 "pan", "HasPAN", "true", 88 "Enables ARM v8.1 Privileged Access-Never extension (FEAT_PAN)">; 89 90def FeatureLOR : SubtargetFeature< 91 "lor", "HasLOR", "true", 92 "Enables ARM v8.1 Limited Ordering Regions extension (FEAT_LOR)">; 93 94def FeatureCONTEXTIDREL2 : SubtargetFeature<"CONTEXTIDREL2", "HasCONTEXTIDREL2", 95 "true", "Enable RW operand CONTEXTIDR_EL2" >; 96 97def FeatureVH : SubtargetFeature<"vh", "HasVH", "true", 98 "Enables ARM v8.1 Virtual Host extension (FEAT_VHE)", [FeatureCONTEXTIDREL2] >; 99 100// This SubtargetFeature is special. It controls only whether codegen will turn 101// `llvm.readcyclecounter()` into an access to a PMUv3 System Register. The 102// `FEAT_PMUv3*` system registers are always available for assembly/disassembly. 103def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", 104 "Enable Code Generation for ARMv8 PMUv3 Performance Monitors extension (FEAT_PMUv3)">; 105 106def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true", 107 "Full FP16 (FEAT_FP16)", [FeatureFPARMv8]>; 108 109def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true", 110 "Enable FP16 FML instructions (FEAT_FHM)", [FeatureFullFP16]>; 111 112def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true", 113 "Enable Statistical Profiling extension (FEAT_SPE)">; 114 115def FeaturePAN_RWV : SubtargetFeature< 116 "pan-rwv", "HasPAN_RWV", "true", 117 "Enable v8.2 PAN s1e1R and s1e1W Variants (FEAT_PAN2)", 118 [FeaturePAN]>; 119 120// UAO PState 121def FeaturePsUAO : SubtargetFeature< "uaops", "HasPsUAO", "true", 122 "Enable v8.2 UAO PState (FEAT_UAO)">; 123 124def FeatureCCPP : SubtargetFeature<"ccpp", "HasCCPP", 125 "true", "Enable v8.2 data Cache Clean to Point of Persistence (FEAT_DPB)" >; 126 127def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true", 128 "Enable Scalable Vector Extension (SVE) instructions (FEAT_SVE)", [FeatureFullFP16]>; 129 130def FeatureFPMR : SubtargetFeature<"fpmr", "HasFPMR", "true", 131 "Enable FPMR Register (FEAT_FPMR)">; 132 133def FeatureFP8 : SubtargetFeature<"fp8", "HasFP8", "true", 134 "Enable FP8 instructions (FEAT_FP8)">; 135 136// This flag is currently still labeled as Experimental, but when fully 137// implemented this should tell the compiler to use the zeroing pseudos to 138// benefit from the reverse instructions (e.g. SUB vs SUBR) if the inactive 139// lanes are known to be zero. The pseudos will then be expanded using the 140// MOVPRFX instruction to zero the inactive lanes. This feature should only be 141// enabled if MOVPRFX instructions are known to merge with the destructive 142// operations they prefix. 143// 144// This feature could similarly be extended to support cheap merging of _any_ 145// value into the inactive lanes using the MOVPRFX instruction that uses 146// merging-predication. 147def FeatureExperimentalZeroingPseudos 148 : SubtargetFeature<"use-experimental-zeroing-pseudos", 149 "UseExperimentalZeroingPseudos", "true", 150 "Hint to the compiler that the MOVPRFX instruction is " 151 "merged with destructive operations", 152 []>; 153 154def FeatureUseScalarIncVL : SubtargetFeature<"use-scalar-inc-vl", 155 "UseScalarIncVL", "true", "Prefer inc/dec over add+cnt">; 156 157def FeatureBF16 : SubtargetFeature<"bf16", "HasBF16", 158 "true", "Enable BFloat16 Extension (FEAT_BF16)" >; 159 160def FeatureNoSVEFPLD1R : SubtargetFeature<"no-sve-fp-ld1r", 161 "NoSVEFPLD1R", "true", "Avoid using LD1RX instructions for FP">; 162 163def FeatureSVE2 : SubtargetFeature<"sve2", "HasSVE2", "true", 164 "Enable Scalable Vector Extension 2 (SVE2) instructions (FEAT_SVE2)", 165 [FeatureSVE, FeatureUseScalarIncVL]>; 166 167def FeatureSVE2AES : SubtargetFeature<"sve2-aes", "HasSVE2AES", "true", 168 "Enable AES SVE2 instructions (FEAT_SVE_AES, FEAT_SVE_PMULL128)", 169 [FeatureSVE2, FeatureAES]>; 170 171def FeatureSVE2SM4 : SubtargetFeature<"sve2-sm4", "HasSVE2SM4", "true", 172 "Enable SM4 SVE2 instructions (FEAT_SVE_SM4)", [FeatureSVE2, FeatureSM4]>; 173 174def FeatureSVE2SHA3 : SubtargetFeature<"sve2-sha3", "HasSVE2SHA3", "true", 175 "Enable SHA3 SVE2 instructions (FEAT_SVE_SHA3)", [FeatureSVE2, FeatureSHA3]>; 176 177def FeatureSVE2BitPerm : SubtargetFeature<"sve2-bitperm", "HasSVE2BitPerm", "true", 178 "Enable bit permutation SVE2 instructions (FEAT_SVE_BitPerm)", [FeatureSVE2]>; 179 180def FeatureSVE2p1: SubtargetFeature<"sve2p1", "HasSVE2p1", "true", 181 "Enable Scalable Vector Extension 2.1 instructions", [FeatureSVE2]>; 182 183def FeatureB16B16 : SubtargetFeature<"b16b16", "HasB16B16", "true", 184 "Enable SVE2.1 or SME2.1 non-widening BFloat16 to BFloat16 instructions (FEAT_B16B16)", [FeatureBF16]>; 185 186def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true", 187 "Has zero-cycle register moves">; 188 189def FeatureZCZeroingGP : SubtargetFeature<"zcz-gp", "HasZeroCycleZeroingGP", "true", 190 "Has zero-cycle zeroing instructions for generic registers">; 191 192// It is generally beneficial to rewrite "fmov s0, wzr" to "movi d0, #0". 193// as movi is more efficient across all cores. Newer cores can eliminate 194// fmovs early and there is no difference with movi, but this not true for 195// all implementations. 196def FeatureNoZCZeroingFP : SubtargetFeature<"no-zcz-fp", "HasZeroCycleZeroingFP", "false", 197 "Has no zero-cycle zeroing instructions for FP registers">; 198 199def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true", 200 "Has zero-cycle zeroing instructions", 201 [FeatureZCZeroingGP]>; 202 203/// ... but the floating-point version doesn't quite work in rare cases on older 204/// CPUs. 205def FeatureZCZeroingFPWorkaround : SubtargetFeature<"zcz-fp-workaround", 206 "HasZeroCycleZeroingFPWorkaround", "true", 207 "The zero-cycle floating-point zeroing instruction has a bug">; 208 209def FeatureStrictAlign : SubtargetFeature<"strict-align", 210 "RequiresStrictAlign", "true", 211 "Disallow all unaligned memory " 212 "access">; 213 214foreach i = {1-7,9-15,18,20-28,30} in 215 def FeatureReserveX#i : SubtargetFeature<"reserve-x"#i, "ReserveXRegister["#i#"]", "true", 216 "Reserve X"#i#", making it unavailable " 217 "as a GPR">; 218 219foreach i = {8-15,18} in 220 def FeatureCallSavedX#i : SubtargetFeature<"call-saved-x"#i, 221 "CustomCallSavedXRegs["#i#"]", "true", "Make X"#i#" callee saved.">; 222 223def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps", 224 "true", 225 "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">; 226 227def FeaturePredictableSelectIsExpensive : SubtargetFeature< 228 "predictable-select-expensive", "PredictableSelectIsExpensive", "true", 229 "Prefer likely predicted branches over selects">; 230 231def FeatureEnableSelectOptimize : SubtargetFeature< 232 "enable-select-opt", "EnableSelectOptimize", "true", 233 "Enable the select optimize pass for select loop heuristics">; 234 235def FeatureExynosCheapAsMoveHandling : SubtargetFeature<"exynos-cheap-as-move", 236 "HasExynosCheapAsMoveHandling", "true", 237 "Use Exynos specific handling of cheap instructions">; 238 239def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler", 240 "UsePostRAScheduler", "true", "Schedule again after register allocation">; 241 242def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store", 243 "IsMisaligned128StoreSlow", "true", "Misaligned 128 bit stores are slow">; 244 245def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128", 246 "IsPaired128Slow", "true", "Paired 128 bit loads and stores are slow">; 247 248def FeatureAscendStoreAddress : SubtargetFeature<"ascend-store-address", 249 "IsStoreAddressAscend", "true", 250 "Schedule vector stores by ascending address">; 251 252def FeatureSlowSTRQro : SubtargetFeature<"slow-strqro-store", "IsSTRQroSlow", 253 "true", "STR of Q register with register offset is slow">; 254 255def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature< 256 "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern", 257 "true", "Use alternative pattern for sextload convert to f32">; 258 259def FeatureArithmeticBccFusion : SubtargetFeature< 260 "arith-bcc-fusion", "HasArithmeticBccFusion", "true", 261 "CPU fuses arithmetic+bcc operations">; 262 263def FeatureArithmeticCbzFusion : SubtargetFeature< 264 "arith-cbz-fusion", "HasArithmeticCbzFusion", "true", 265 "CPU fuses arithmetic + cbz/cbnz operations">; 266 267def FeatureCmpBccFusion : SubtargetFeature< 268 "cmp-bcc-fusion", "HasCmpBccFusion", "true", 269 "CPU fuses cmp+bcc operations">; 270 271def FeatureFuseAddress : SubtargetFeature< 272 "fuse-address", "HasFuseAddress", "true", 273 "CPU fuses address generation and memory operations">; 274 275def FeatureFuseAES : SubtargetFeature< 276 "fuse-aes", "HasFuseAES", "true", 277 "CPU fuses AES crypto operations">; 278 279def FeatureFuseArithmeticLogic : SubtargetFeature< 280 "fuse-arith-logic", "HasFuseArithmeticLogic", "true", 281 "CPU fuses arithmetic and logic operations">; 282 283def FeatureFuseCCSelect : SubtargetFeature< 284 "fuse-csel", "HasFuseCCSelect", "true", 285 "CPU fuses conditional select operations">; 286 287def FeatureFuseCryptoEOR : SubtargetFeature< 288 "fuse-crypto-eor", "HasFuseCryptoEOR", "true", 289 "CPU fuses AES/PMULL and EOR operations">; 290 291def FeatureFuseAdrpAdd : SubtargetFeature< 292 "fuse-adrp-add", "HasFuseAdrpAdd", "true", 293 "CPU fuses adrp+add operations">; 294 295def FeatureFuseLiterals : SubtargetFeature< 296 "fuse-literals", "HasFuseLiterals", "true", 297 "CPU fuses literal generation operations">; 298 299def FeatureFuseAddSub2RegAndConstOne : SubtargetFeature< 300 "fuse-addsub-2reg-const1", "HasFuseAddSub2RegAndConstOne", "true", 301 "CPU fuses (a + b + 1) and (a - b - 1)">; 302 303def FeatureDisableLatencySchedHeuristic : SubtargetFeature< 304 "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true", 305 "Disable latency scheduling heuristic">; 306 307def FeatureStorePairSuppress : SubtargetFeature< 308 "store-pair-suppress", "EnableStorePairSuppress", "true", 309 "Enable Store Pair Suppression heuristics">; 310 311def FeatureForce32BitJumpTables 312 : SubtargetFeature<"force-32bit-jump-tables", "Force32BitJumpTables", "true", 313 "Force jump table entries to be 32-bits wide except at MinSize">; 314 315def FeatureRCPC : SubtargetFeature<"rcpc", "HasRCPC", "true", 316 "Enable support for RCPC extension (FEAT_LRCPC)">; 317 318def FeatureUseRSqrt : SubtargetFeature< 319 "use-reciprocal-square-root", "UseRSqrt", "true", 320 "Use the reciprocal square root approximation">; 321 322def FeatureDotProd : SubtargetFeature< 323 "dotprod", "HasDotProd", "true", 324 "Enable dot product support (FEAT_DotProd)">; 325 326def FeaturePAuth : SubtargetFeature< 327 "pauth", "HasPAuth", "true", 328 "Enable v8.3-A Pointer Authentication extension (FEAT_PAuth)">; 329 330def FeatureJS : SubtargetFeature< 331 "jsconv", "HasJS", "true", 332 "Enable v8.3-A JavaScript FP conversion instructions (FEAT_JSCVT)", 333 [FeatureFPARMv8]>; 334 335def FeatureCCIDX : SubtargetFeature< 336 "ccidx", "HasCCIDX", "true", 337 "Enable v8.3-A Extend of the CCSIDR number of sets (FEAT_CCIDX)">; 338 339def FeatureComplxNum : SubtargetFeature< 340 "complxnum", "HasComplxNum", "true", 341 "Enable v8.3-A Floating-point complex number support (FEAT_FCMA)", 342 [FeatureNEON]>; 343 344def FeatureNV : SubtargetFeature< 345 "nv", "HasNV", "true", 346 "Enable v8.4-A Nested Virtualization Enchancement (FEAT_NV, FEAT_NV2)">; 347 348def FeatureMPAM : SubtargetFeature< 349 "mpam", "HasMPAM", "true", 350 "Enable v8.4-A Memory system Partitioning and Monitoring extension (FEAT_MPAM)">; 351 352def FeatureDIT : SubtargetFeature< 353 "dit", "HasDIT", "true", 354 "Enable v8.4-A Data Independent Timing instructions (FEAT_DIT)">; 355 356def FeatureTRACEV8_4 : SubtargetFeature< 357 "tracev8.4", "HasTRACEV8_4", "true", 358 "Enable v8.4-A Trace extension (FEAT_TRF)">; 359 360def FeatureAM : SubtargetFeature< 361 "am", "HasAM", "true", 362 "Enable v8.4-A Activity Monitors extension (FEAT_AMUv1)">; 363 364def FeatureAMVS : SubtargetFeature< 365 "amvs", "HasAMVS", "true", 366 "Enable v8.6-A Activity Monitors Virtualization support (FEAT_AMUv1p1)", 367 [FeatureAM]>; 368 369def FeatureSEL2 : SubtargetFeature< 370 "sel2", "HasSEL2", "true", 371 "Enable v8.4-A Secure Exception Level 2 extension (FEAT_SEL2)">; 372 373def FeatureTLB_RMI : SubtargetFeature< 374 "tlb-rmi", "HasTLB_RMI", "true", 375 "Enable v8.4-A TLB Range and Maintenance Instructions (FEAT_TLBIOS, FEAT_TLBIRANGE)">; 376 377def FeatureFlagM : SubtargetFeature< 378 "flagm", "HasFlagM", "true", 379 "Enable v8.4-A Flag Manipulation Instructions (FEAT_FlagM)">; 380 381// 8.4 RCPC enchancements: LDAPR & STLR instructions with Immediate Offset 382def FeatureRCPC_IMMO : SubtargetFeature<"rcpc-immo", "HasRCPC_IMMO", "true", 383 "Enable v8.4-A RCPC instructions with Immediate Offsets (FEAT_LRCPC2)", 384 [FeatureRCPC]>; 385 386def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates", 387 "NegativeImmediates", "false", 388 "Convert immediates and instructions " 389 "to their negated or complemented " 390 "equivalent when the immediate does " 391 "not fit in the encoding.">; 392 393def FeatureAddrLSLFast : SubtargetFeature< 394 "addr-lsl-fast", "HasAddrLSLFast", "true", 395 "Address operands with logical shift of up to 3 places are cheap">; 396 397def FeatureALULSLFast : SubtargetFeature< 398 "alu-lsl-fast", "HasALULSLFast", "true", 399 "Add/Sub operations with lsl shift <= 4 are cheap">; 400 401def FeatureAggressiveFMA : 402 SubtargetFeature<"aggressive-fma", 403 "HasAggressiveFMA", 404 "true", 405 "Enable Aggressive FMA for floating-point.">; 406 407def FeatureAltFPCmp : SubtargetFeature<"altnzcv", "HasAlternativeNZCV", "true", 408 "Enable alternative NZCV format for floating point comparisons (FEAT_FlagM2)">; 409 410def FeatureFRInt3264 : SubtargetFeature<"fptoint", "HasFRInt3264", "true", 411 "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to " 412 "an integer (in FP format) forcing it to fit into a 32- or 64-bit int (FEAT_FRINTTS)" >; 413 414def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict", 415 "true", "Enable architectural speculation restriction (FEAT_CSV2_2)">; 416 417def FeatureSB : SubtargetFeature<"sb", "HasSB", 418 "true", "Enable v8.5 Speculation Barrier (FEAT_SB)" >; 419 420def FeatureSSBS : SubtargetFeature<"ssbs", "HasSSBS", 421 "true", "Enable Speculative Store Bypass Safe bit (FEAT_SSBS, FEAT_SSBS2)" >; 422 423def FeaturePredRes : SubtargetFeature<"predres", "HasPredRes", "true", 424 "Enable v8.5a execution and data prediction invalidation instructions (FEAT_SPECRES)" >; 425 426def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP", 427 "true", "Enable v8.5 Cache Clean to Point of Deep Persistence (FEAT_DPB2)" >; 428 429def FeatureBranchTargetId : SubtargetFeature<"bti", "HasBTI", 430 "true", "Enable Branch Target Identification (FEAT_BTI)" >; 431 432def FeatureRandGen : SubtargetFeature<"rand", "HasRandGen", 433 "true", "Enable Random Number generation instructions (FEAT_RNG)" >; 434 435def FeatureMTE : SubtargetFeature<"mte", "HasMTE", 436 "true", "Enable Memory Tagging Extension (FEAT_MTE, FEAT_MTE2)" >; 437 438def FeatureTRBE : SubtargetFeature<"trbe", "HasTRBE", 439 "true", "Enable Trace Buffer Extension (FEAT_TRBE)">; 440 441def FeatureETE : SubtargetFeature<"ete", "HasETE", 442 "true", "Enable Embedded Trace Extension (FEAT_ETE)", 443 [FeatureTRBE]>; 444 445def FeatureTME : SubtargetFeature<"tme", "HasTME", 446 "true", "Enable Transactional Memory Extension (FEAT_TME)" >; 447 448def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals", 449 "AllowTaggedGlobals", 450 "true", "Use an instruction sequence for taking the address of a global " 451 "that allows a memory tag in the upper address bits">; 452 453def FeatureMatMulInt8 : SubtargetFeature<"i8mm", "HasMatMulInt8", 454 "true", "Enable Matrix Multiply Int8 Extension (FEAT_I8MM)">; 455 456def FeatureMatMulFP32 : SubtargetFeature<"f32mm", "HasMatMulFP32", 457 "true", "Enable Matrix Multiply FP32 Extension (FEAT_F32MM)", [FeatureSVE]>; 458 459def FeatureMatMulFP64 : SubtargetFeature<"f64mm", "HasMatMulFP64", 460 "true", "Enable Matrix Multiply FP64 Extension (FEAT_F64MM)", [FeatureSVE]>; 461 462def FeatureXS : SubtargetFeature<"xs", "HasXS", 463 "true", "Enable Armv8.7-A limited-TLB-maintenance instruction (FEAT_XS)">; 464 465def FeatureWFxT : SubtargetFeature<"wfxt", "HasWFxT", 466 "true", "Enable Armv8.7-A WFET and WFIT instruction (FEAT_WFxT)">; 467 468def FeatureHCX : SubtargetFeature< 469 "hcx", "HasHCX", "true", "Enable Armv8.7-A HCRX_EL2 system register (FEAT_HCX)">; 470 471def FeatureLS64 : SubtargetFeature<"ls64", "HasLS64", 472 "true", "Enable Armv8.7-A LD64B/ST64B Accelerator Extension (FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA)">; 473 474def FeatureHBC : SubtargetFeature<"hbc", "HasHBC", 475 "true", "Enable Armv8.8-A Hinted Conditional Branches Extension (FEAT_HBC)">; 476 477def FeatureMOPS : SubtargetFeature<"mops", "HasMOPS", 478 "true", "Enable Armv8.8-A memcpy and memset acceleration instructions (FEAT_MOPS)">; 479 480def FeatureNMI : SubtargetFeature<"nmi", "HasNMI", 481 "true", "Enable Armv8.8-A Non-maskable Interrupts (FEAT_NMI, FEAT_GICv3_NMI)">; 482 483def FeatureBRBE : SubtargetFeature<"brbe", "HasBRBE", 484 "true", "Enable Branch Record Buffer Extension (FEAT_BRBE)">; 485 486def FeatureSPE_EEF : SubtargetFeature<"spe-eef", "HasSPE_EEF", 487 "true", "Enable extra register in the Statistical Profiling Extension (FEAT_SPEv1p2)">; 488 489def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps", 490 "true", "Enable fine grained virtualization traps extension (FEAT_FGT)">; 491 492def FeatureEnhancedCounterVirtualization : 493 SubtargetFeature<"ecv", "HasEnhancedCounterVirtualization", 494 "true", "Enable enhanced counter virtualization extension (FEAT_ECV)">; 495 496def FeatureRME : SubtargetFeature<"rme", "HasRME", 497 "true", "Enable Realm Management Extension (FEAT_RME)">; 498 499def FeatureSME : SubtargetFeature<"sme", "HasSME", "true", 500 "Enable Scalable Matrix Extension (SME) (FEAT_SME)", [FeatureBF16, FeatureUseScalarIncVL]>; 501 502def FeatureSMEF64F64 : SubtargetFeature<"sme-f64f64", "HasSMEF64F64", "true", 503 "Enable Scalable Matrix Extension (SME) F64F64 instructions (FEAT_SME_F64F64)", [FeatureSME]>; 504 505def FeatureSMEI16I64 : SubtargetFeature<"sme-i16i64", "HasSMEI16I64", "true", 506 "Enable Scalable Matrix Extension (SME) I16I64 instructions (FEAT_SME_I16I64)", [FeatureSME]>; 507 508def FeatureSMEF16F16 : SubtargetFeature<"sme-f16f16", "HasSMEF16F16", "true", 509 "Enable SME2.1 non-widening Float16 instructions (FEAT_SME_F16F16)", []>; 510 511def FeatureSMEFA64 : SubtargetFeature<"sme-fa64", "HasSMEFA64", "true", 512 "Enable the full A64 instruction set in streaming SVE mode (FEAT_SME_FA64)", [FeatureSME, FeatureSVE2]>; 513 514def FeatureSME2 : SubtargetFeature<"sme2", "HasSME2", "true", 515 "Enable Scalable Matrix Extension 2 (SME2) instructions", [FeatureSME]>; 516 517def FeatureSME2p1 : SubtargetFeature<"sme2p1", "HasSME2p1", "true", 518 "Enable Scalable Matrix Extension 2.1 (FEAT_SME2p1) instructions", [FeatureSME2]>; 519 520def FeatureFAMINMAX: SubtargetFeature<"faminmax", "HasFAMINMAX", "true", 521 "Enable FAMIN and FAMAX instructions (FEAT_FAMINMAX)">; 522 523def FeatureFP8FMA : SubtargetFeature<"fp8fma", "HasFP8FMA", "true", 524 "Enable fp8 multiply-add instructions (FEAT_FP8FMA)">; 525 526def FeatureSSVE_FP8FMA : SubtargetFeature<"ssve-fp8fma", "HasSSVE_FP8FMA", "true", 527 "Enable SVE2 fp8 multiply-add instructions (FEAT_SSVE_FP8FMA)", [FeatureSME2]>; 528 529def FeatureFP8DOT2: SubtargetFeature<"fp8dot2", "HasFP8DOT2", "true", 530 "Enable fp8 2-way dot instructions (FEAT_FP8DOT2)">; 531 532def FeatureSSVE_FP8DOT2 : SubtargetFeature<"ssve-fp8dot2", "HasSSVE_FP8DOT2", "true", 533 "Enable SVE2 fp8 2-way dot product instructions (FEAT_SSVE_FP8DOT2)", [FeatureSME2]>; 534 535def FeatureFP8DOT4: SubtargetFeature<"fp8dot4", "HasFP8DOT4", "true", 536 "Enable fp8 4-way dot instructions (FEAT_FP8DOT4)">; 537 538def FeatureSSVE_FP8DOT4 : SubtargetFeature<"ssve-fp8dot4", "HasSSVE_FP8DOT4", "true", 539 "Enable SVE2 fp8 4-way dot product instructions (FEAT_SSVE_FP8DOT4)", [FeatureSME2]>; 540def FeatureLUT: SubtargetFeature<"lut", "HasLUT", "true", 541 "Enable Lookup Table instructions (FEAT_LUT)">; 542 543def FeatureSME_LUTv2 : SubtargetFeature<"sme-lutv2", "HasSME_LUTv2", "true", 544 "Enable Scalable Matrix Extension (SME) LUTv2 instructions (FEAT_SME_LUTv2)">; 545 546def FeatureSMEF8F16 : SubtargetFeature<"sme-f8f16", "HasSMEF8F16", "true", 547 "Enable Scalable Matrix Extension (SME) F8F16 instructions(FEAT_SME_F8F16)", [FeatureSME2, FeatureFP8]>; 548 549def FeatureSMEF8F32 : SubtargetFeature<"sme-f8f32", "HasSMEF8F32", "true", 550 "Enable Scalable Matrix Extension (SME) F8F32 instructions (FEAT_SME_F8F32)", [FeatureSME2, FeatureFP8]>; 551 552def FeatureAppleA7SysReg : SubtargetFeature<"apple-a7-sysreg", "HasAppleA7SysReg", "true", 553 "Apple A7 (the CPU formerly known as Cyclone)">; 554 555def FeatureEL2VMSA : SubtargetFeature<"el2vmsa", "HasEL2VMSA", "true", 556 "Enable Exception Level 2 Virtual Memory System Architecture">; 557 558def FeatureEL3 : SubtargetFeature<"el3", "HasEL3", "true", 559 "Enable Exception Level 3">; 560 561def FeatureCSSC : SubtargetFeature<"cssc", "HasCSSC", "true", 562 "Enable Common Short Sequence Compression (CSSC) instructions (FEAT_CSSC)">; 563 564def FeatureFixCortexA53_835769 : SubtargetFeature<"fix-cortex-a53-835769", 565 "FixCortexA53_835769", "true", "Mitigate Cortex-A53 Erratum 835769">; 566 567def FeatureNoBTIAtReturnTwice : SubtargetFeature<"no-bti-at-return-twice", 568 "NoBTIAtReturnTwice", "true", 569 "Don't place a BTI instruction " 570 "after a return-twice">; 571 572def FeatureCHK : SubtargetFeature<"chk", "HasCHK", 573 "true", "Enable Armv8.0-A Check Feature Status Extension (FEAT_CHK)">; 574 575def FeatureGCS : SubtargetFeature<"gcs", "HasGCS", 576 "true", "Enable Armv9.4-A Guarded Call Stack Extension", [FeatureCHK]>; 577 578def FeatureCLRBHB : SubtargetFeature<"clrbhb", "HasCLRBHB", 579 "true", "Enable Clear BHB instruction (FEAT_CLRBHB)">; 580 581def FeaturePRFM_SLC : SubtargetFeature<"prfm-slc-target", "HasPRFM_SLC", 582 "true", "Enable SLC target for PRFM instruction">; 583 584def FeatureSPECRES2 : SubtargetFeature<"specres2", "HasSPECRES2", 585 "true", "Enable Speculation Restriction Instruction (FEAT_SPECRES2)", 586 [FeaturePredRes]>; 587 588def FeatureMEC : SubtargetFeature<"mec", "HasMEC", 589 "true", "Enable Memory Encryption Contexts Extension", [FeatureRME]>; 590 591def FeatureITE : SubtargetFeature<"ite", "HasITE", 592 "true", "Enable Armv9.4-A Instrumentation Extension FEAT_ITE", [FeatureETE, 593 FeatureTRBE]>; 594 595def FeatureRCPC3 : SubtargetFeature<"rcpc3", "HasRCPC3", 596 "true", "Enable Armv8.9-A RCPC instructions for A64 and Advanced SIMD and floating-point instruction set (FEAT_LRCPC3)", 597 [FeatureRCPC_IMMO]>; 598 599def FeatureTHE : SubtargetFeature<"the", "HasTHE", 600 "true", "Enable Armv8.9-A Translation Hardening Extension (FEAT_THE)">; 601 602def FeatureLSE128 : SubtargetFeature<"lse128", "HasLSE128", 603 "true", "Enable Armv9.4-A 128-bit Atomic Instructions (FEAT_LSE128)", 604 [FeatureLSE]>; 605 606// FEAT_D128, FEAT_LVA3, FEAT_SYSREG128, and FEAT_SYSINSTR128 are mutually implicit. 607// Therefore group them all under a single feature flag, d128: 608def FeatureD128 : SubtargetFeature<"d128", "HasD128", 609 "true", "Enable Armv9.4-A 128-bit Page Table Descriptors, System Registers " 610 "and Instructions (FEAT_D128, FEAT_LVA3, FEAT_SYSREG128, FEAT_SYSINSTR128)", 611 [FeatureLSE128]>; 612 613def FeatureDisableLdp : SubtargetFeature<"disable-ldp", "HasDisableLdp", 614 "true", "Do not emit ldp">; 615 616def FeatureDisableStp : SubtargetFeature<"disable-stp", "HasDisableStp", 617 "true", "Do not emit stp">; 618 619def FeatureLdpAlignedOnly : SubtargetFeature<"ldp-aligned-only", "HasLdpAlignedOnly", 620 "true", "In order to emit ldp, first check if the load will be aligned to 2 * element_size">; 621 622def FeatureStpAlignedOnly : SubtargetFeature<"stp-aligned-only", "HasStpAlignedOnly", 623 "true", "In order to emit stp, first check if the store will be aligned to 2 * element_size">; 624 625// AArch64 2023 Architecture Extensions (v9.5-A) 626 627def FeatureCPA : SubtargetFeature<"cpa", "HasCPA", "true", 628 "Enable Armv9.5-A Checked Pointer Arithmetic (FEAT_CPA)">; 629 630def FeaturePAuthLR : SubtargetFeature<"pauth-lr", "HasPAuthLR", 631 "true", "Enable Armv9.5-A PAC enhancements (FEAT_PAuth_LR)">; 632 633def FeatureTLBIW : SubtargetFeature<"tlbiw", "HasTLBIW", "true", 634 "Enable ARMv9.5-A TLBI VMALL for Dirty State (FEAT_TLBIW)">; 635 636//===----------------------------------------------------------------------===// 637// Architectures. 638// 639def HasV8_0aOps : SubtargetFeature<"v8a", "HasV8_0aOps", "true", 640 "Support ARM v8.0a instructions", [FeatureEL2VMSA, FeatureEL3]>; 641 642def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", 643 "Support ARM v8.1a instructions", [HasV8_0aOps, FeatureCRC, FeatureLSE, 644 FeatureRDM, FeaturePAN, FeatureLOR, FeatureVH]>; 645 646def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true", 647 "Support ARM v8.2a instructions", [HasV8_1aOps, FeaturePsUAO, 648 FeaturePAN_RWV, FeatureRAS, FeatureCCPP]>; 649 650def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true", 651 "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC, FeaturePAuth, 652 FeatureJS, FeatureCCIDX, FeatureComplxNum]>; 653 654def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", 655 "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd, 656 FeatureNV, FeatureMPAM, FeatureDIT, 657 FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeatureTLB_RMI, 658 FeatureFlagM, FeatureRCPC_IMMO, FeatureLSE2]>; 659 660def HasV8_5aOps : SubtargetFeature< 661 "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions", 662 [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict, 663 FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist, 664 FeatureBranchTargetId]>; 665 666def HasV8_6aOps : SubtargetFeature< 667 "v8.6a", "HasV8_6aOps", "true", "Support ARM v8.6a instructions", 668 [HasV8_5aOps, FeatureAMVS, FeatureBF16, FeatureFineGrainedTraps, 669 FeatureEnhancedCounterVirtualization, FeatureMatMulInt8]>; 670 671def HasV8_7aOps : SubtargetFeature< 672 "v8.7a", "HasV8_7aOps", "true", "Support ARM v8.7a instructions", 673 [HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX]>; 674 675def HasV8_8aOps : SubtargetFeature< 676 "v8.8a", "HasV8_8aOps", "true", "Support ARM v8.8a instructions", 677 [HasV8_7aOps, FeatureHBC, FeatureMOPS, FeatureNMI]>; 678 679def HasV8_9aOps : SubtargetFeature< 680 "v8.9a", "HasV8_9aOps", "true", "Support ARM v8.9a instructions", 681 [HasV8_8aOps, FeatureCLRBHB, FeaturePRFM_SLC, FeatureSPECRES2, 682 FeatureCSSC, FeatureRASv2, FeatureCHK]>; 683 684def HasV9_0aOps : SubtargetFeature< 685 "v9a", "HasV9_0aOps", "true", "Support ARM v9a instructions", 686 [HasV8_5aOps, FeatureMEC, FeatureSVE2]>; 687 688def HasV9_1aOps : SubtargetFeature< 689 "v9.1a", "HasV9_1aOps", "true", "Support ARM v9.1a instructions", 690 [HasV8_6aOps, HasV9_0aOps]>; 691 692def HasV9_2aOps : SubtargetFeature< 693 "v9.2a", "HasV9_2aOps", "true", "Support ARM v9.2a instructions", 694 [HasV8_7aOps, HasV9_1aOps]>; 695 696def HasV9_3aOps : SubtargetFeature< 697 "v9.3a", "HasV9_3aOps", "true", "Support ARM v9.3a instructions", 698 [HasV8_8aOps, HasV9_2aOps]>; 699 700def HasV9_4aOps : SubtargetFeature< 701 "v9.4a", "HasV9_4aOps", "true", "Support ARM v9.4a instructions", 702 [HasV8_9aOps, HasV9_3aOps]>; 703 704def HasV9_5aOps : SubtargetFeature< 705 "v9.5a", "HasV9_5aOps", "true", "Support ARM v9.5a instructions", 706 [HasV9_4aOps, FeatureCPA]>; 707 708def HasV8_0rOps : SubtargetFeature< 709 "v8r", "HasV8_0rOps", "true", "Support ARM v8r instructions", 710 [//v8.1 711 FeatureCRC, FeaturePAN, FeatureRDM, FeatureLSE, FeatureCONTEXTIDREL2, 712 //v8.2 713 FeatureRAS, FeaturePsUAO, FeatureCCPP, FeaturePAN_RWV, 714 //v8.3 715 FeatureComplxNum, FeatureCCIDX, FeatureJS, 716 FeaturePAuth, FeatureRCPC, 717 //v8.4 718 FeatureDotProd, FeatureTRACEV8_4, FeatureTLB_RMI, 719 FeatureFlagM, FeatureDIT, FeatureSEL2, FeatureRCPC_IMMO, 720 // Not mandatory in v8.0-R, but included here on the grounds that it 721 // only enables names of system registers 722 FeatureSpecRestrict 723 ]>; 724 725// Only intended to be used by disassemblers. 726def FeatureAll 727 : SubtargetFeature<"all", "IsAll", "true", "Enable all instructions", []>; 728 729class AssemblerPredicateWithAll<dag cond, string name=""> 730 : AssemblerPredicate<(any_of FeatureAll, cond), name>; 731 732//===----------------------------------------------------------------------===// 733// Register File Description 734//===----------------------------------------------------------------------===// 735 736include "AArch64RegisterInfo.td" 737include "AArch64RegisterBanks.td" 738include "AArch64CallingConvention.td" 739 740//===----------------------------------------------------------------------===// 741// Instruction Descriptions 742//===----------------------------------------------------------------------===// 743 744include "AArch64Schedule.td" 745include "AArch64InstrInfo.td" 746include "AArch64SchedPredicates.td" 747include "AArch64SchedPredExynos.td" 748include "AArch64SchedPredNeoverse.td" 749include "AArch64Combine.td" 750 751def AArch64InstrInfo : InstrInfo; 752 753//===----------------------------------------------------------------------===// 754// Named operands for MRS/MSR/TLBI/... 755//===----------------------------------------------------------------------===// 756 757include "AArch64SystemOperands.td" 758 759//===----------------------------------------------------------------------===// 760// Access to privileged registers 761//===----------------------------------------------------------------------===// 762 763foreach i = 1-3 in 764def FeatureUseEL#i#ForTP : SubtargetFeature<"tpidr-el"#i, "UseEL"#i#"ForTP", 765 "true", "Permit use of TPIDR_EL"#i#" for the TLS base">; 766def FeatureUseROEL0ForTP : SubtargetFeature<"tpidrro-el0", "UseROEL0ForTP", 767 "true", "Permit use of TPIDRRO_EL0 for the TLS base">; 768 769//===----------------------------------------------------------------------===// 770// Control codegen mitigation against Straight Line Speculation vulnerability. 771//===----------------------------------------------------------------------===// 772 773def FeatureHardenSlsRetBr : SubtargetFeature<"harden-sls-retbr", 774 "HardenSlsRetBr", "true", 775 "Harden against straight line speculation across RET and BR instructions">; 776def FeatureHardenSlsBlr : SubtargetFeature<"harden-sls-blr", 777 "HardenSlsBlr", "true", 778 "Harden against straight line speculation across BLR instructions">; 779def FeatureHardenSlsNoComdat : SubtargetFeature<"harden-sls-nocomdat", 780 "HardenSlsNoComdat", "true", 781 "Generate thunk code for SLS mitigation in the normal text section">; 782 783//===----------------------------------------------------------------------===// 784// AArch64 Processors supported. 785// 786 787//===----------------------------------------------------------------------===// 788// Unsupported features to disable for scheduling models 789//===----------------------------------------------------------------------===// 790 791class AArch64Unsupported { list<Predicate> F; } 792 793let F = [HasSVE2p1, HasSVE2p1_or_HasSME2, HasSVE2p1_or_HasSME2p1] in 794def SVE2p1Unsupported : AArch64Unsupported; 795 796def SVE2Unsupported : AArch64Unsupported { 797 let F = !listconcat([HasSVE2, HasSVE2orSME, HasSVE2orSME2, HasSSVE_FP8FMA, HasSMEF8F16, 798 HasSMEF8F32, HasSVE2AES, HasSVE2SHA3, HasSVE2SM4, HasSVE2BitPerm], 799 SVE2p1Unsupported.F); 800} 801 802def SVEUnsupported : AArch64Unsupported { 803 let F = !listconcat([HasSVE, HasSVEorSME], 804 SVE2Unsupported.F); 805} 806 807let F = [HasSME2p1, HasSVE2p1_or_HasSME2p1] in 808def SME2p1Unsupported : AArch64Unsupported; 809 810def SME2Unsupported : AArch64Unsupported { 811 let F = !listconcat([HasSME2, HasSVE2orSME2, HasSVE2p1_or_HasSME2, HasSSVE_FP8FMA, 812 HasSMEF8F16, HasSMEF8F32], 813 SME2p1Unsupported.F); 814} 815 816def SMEUnsupported : AArch64Unsupported { 817 let F = !listconcat([HasSME, HasSMEI16I64, HasSMEF16F16, HasSMEF64F64, HasSMEFA64], 818 SME2Unsupported.F); 819} 820 821let F = [HasPAuth, HasPAuthLR] in 822def PAUnsupported : AArch64Unsupported; 823 824include "AArch64SchedA53.td" 825include "AArch64SchedA55.td" 826include "AArch64SchedA510.td" 827include "AArch64SchedA57.td" 828include "AArch64SchedCyclone.td" 829include "AArch64SchedFalkor.td" 830include "AArch64SchedKryo.td" 831include "AArch64SchedExynosM3.td" 832include "AArch64SchedExynosM4.td" 833include "AArch64SchedExynosM5.td" 834include "AArch64SchedThunderX.td" 835include "AArch64SchedThunderX2T99.td" 836include "AArch64SchedA64FX.td" 837include "AArch64SchedThunderX3T110.td" 838include "AArch64SchedTSV110.td" 839include "AArch64SchedAmpere1.td" 840include "AArch64SchedNeoverseN1.td" 841include "AArch64SchedNeoverseN2.td" 842include "AArch64SchedNeoverseV1.td" 843include "AArch64SchedNeoverseV2.td" 844 845def TuneA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35", 846 "Cortex-A35 ARM processors">; 847 848def TuneA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", 849 "Cortex-A53 ARM processors", [ 850 FeatureFuseAES, 851 FeatureFuseAdrpAdd, 852 FeatureBalanceFPOps, 853 FeaturePostRAScheduler]>; 854 855def TuneA55 : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55", 856 "Cortex-A55 ARM processors", [ 857 FeatureFuseAES, 858 FeatureFuseAdrpAdd, 859 FeaturePostRAScheduler, 860 FeatureFuseAddress]>; 861 862def TuneA510 : SubtargetFeature<"a510", "ARMProcFamily", "CortexA510", 863 "Cortex-A510 ARM processors", [ 864 FeatureFuseAES, 865 FeatureFuseAdrpAdd, 866 FeaturePostRAScheduler 867 ]>; 868 869def TuneA520 : SubtargetFeature<"a520", "ARMProcFamily", "CortexA520", 870 "Cortex-A520 ARM processors", [ 871 FeatureFuseAES, 872 FeatureFuseAdrpAdd, 873 FeaturePostRAScheduler]>; 874 875def TuneA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", 876 "Cortex-A57 ARM processors", [ 877 FeatureFuseAES, 878 FeatureBalanceFPOps, 879 FeatureFuseAdrpAdd, 880 FeatureFuseLiterals, 881 FeaturePostRAScheduler, 882 FeatureEnableSelectOptimize, 883 FeaturePredictableSelectIsExpensive]>; 884 885def TuneA65 : SubtargetFeature<"a65", "ARMProcFamily", "CortexA65", 886 "Cortex-A65 ARM processors", [ 887 FeatureFuseAES, 888 FeatureFuseAddress, 889 FeatureFuseAdrpAdd, 890 FeatureFuseLiterals, 891 FeatureEnableSelectOptimize, 892 FeaturePredictableSelectIsExpensive]>; 893 894def TuneA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72", 895 "Cortex-A72 ARM processors", [ 896 FeatureFuseAES, 897 FeatureFuseAdrpAdd, 898 FeatureFuseLiterals, 899 FeatureEnableSelectOptimize, 900 FeaturePredictableSelectIsExpensive]>; 901 902def TuneA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73", 903 "Cortex-A73 ARM processors", [ 904 FeatureFuseAES, 905 FeatureFuseAdrpAdd, 906 FeatureEnableSelectOptimize, 907 FeaturePredictableSelectIsExpensive]>; 908 909def TuneA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75", 910 "Cortex-A75 ARM processors", [ 911 FeatureFuseAES, 912 FeatureFuseAdrpAdd, 913 FeatureEnableSelectOptimize, 914 FeaturePredictableSelectIsExpensive]>; 915 916def TuneA76 : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76", 917 "Cortex-A76 ARM processors", [ 918 FeatureFuseAES, 919 FeatureFuseAdrpAdd, 920 FeatureAddrLSLFast, 921 FeatureALULSLFast, 922 FeatureEnableSelectOptimize, 923 FeaturePredictableSelectIsExpensive]>; 924 925def TuneA77 : SubtargetFeature<"a77", "ARMProcFamily", "CortexA77", 926 "Cortex-A77 ARM processors", [ 927 FeatureCmpBccFusion, 928 FeatureFuseAES, 929 FeatureFuseAdrpAdd, 930 FeatureAddrLSLFast, 931 FeatureALULSLFast, 932 FeatureEnableSelectOptimize, 933 FeaturePredictableSelectIsExpensive]>; 934 935def TuneA78 : SubtargetFeature<"a78", "ARMProcFamily", "CortexA78", 936 "Cortex-A78 ARM processors", [ 937 FeatureCmpBccFusion, 938 FeatureFuseAES, 939 FeatureFuseAdrpAdd, 940 FeatureAddrLSLFast, 941 FeatureALULSLFast, 942 FeaturePostRAScheduler, 943 FeatureEnableSelectOptimize, 944 FeaturePredictableSelectIsExpensive]>; 945 946def TuneA78C : SubtargetFeature<"a78c", "ARMProcFamily", 947 "CortexA78C", 948 "Cortex-A78C ARM processors", [ 949 FeatureCmpBccFusion, 950 FeatureFuseAES, 951 FeatureFuseAdrpAdd, 952 FeatureAddrLSLFast, 953 FeatureALULSLFast, 954 FeaturePostRAScheduler, 955 FeatureEnableSelectOptimize, 956 FeaturePredictableSelectIsExpensive]>; 957 958def TuneA710 : SubtargetFeature<"a710", "ARMProcFamily", "CortexA710", 959 "Cortex-A710 ARM processors", [ 960 FeatureCmpBccFusion, 961 FeatureFuseAES, 962 FeatureFuseAdrpAdd, 963 FeatureAddrLSLFast, 964 FeatureALULSLFast, 965 FeaturePostRAScheduler, 966 FeatureEnableSelectOptimize, 967 FeaturePredictableSelectIsExpensive]>; 968 969def TuneA715 : SubtargetFeature<"a715", "ARMProcFamily", "CortexA715", 970 "Cortex-A715 ARM processors", [ 971 FeatureFuseAES, 972 FeaturePostRAScheduler, 973 FeatureCmpBccFusion, 974 FeatureAddrLSLFast, 975 FeatureALULSLFast, 976 FeatureFuseAdrpAdd, 977 FeatureEnableSelectOptimize, 978 FeaturePredictableSelectIsExpensive]>; 979 980def TuneA720 : SubtargetFeature<"a720", "ARMProcFamily", "CortexA720", 981 "Cortex-A720 ARM processors", [ 982 FeatureFuseAES, 983 FeaturePostRAScheduler, 984 FeatureCmpBccFusion, 985 FeatureAddrLSLFast, 986 FeatureALULSLFast, 987 FeatureFuseAdrpAdd, 988 FeatureEnableSelectOptimize, 989 FeaturePredictableSelectIsExpensive]>; 990 991def TuneR82 : SubtargetFeature<"cortex-r82", "ARMProcFamily", 992 "CortexR82", 993 "Cortex-R82 ARM processors", [ 994 FeaturePostRAScheduler]>; 995 996def TuneX1 : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1", 997 "Cortex-X1 ARM processors", [ 998 FeatureCmpBccFusion, 999 FeatureFuseAES, 1000 FeatureFuseAdrpAdd, 1001 FeatureAddrLSLFast, 1002 FeatureALULSLFast, 1003 FeaturePostRAScheduler, 1004 FeatureEnableSelectOptimize, 1005 FeaturePredictableSelectIsExpensive]>; 1006 1007def TuneX2 : SubtargetFeature<"cortex-x2", "ARMProcFamily", "CortexX2", 1008 "Cortex-X2 ARM processors", [ 1009 FeatureCmpBccFusion, 1010 FeatureFuseAES, 1011 FeatureFuseAdrpAdd, 1012 FeatureAddrLSLFast, 1013 FeatureALULSLFast, 1014 FeaturePostRAScheduler, 1015 FeatureEnableSelectOptimize, 1016 FeaturePredictableSelectIsExpensive]>; 1017 1018def TuneX3 : SubtargetFeature<"cortex-x3", "ARMProcFamily", "CortexX3", 1019 "Cortex-X3 ARM processors", [ 1020 FeatureAddrLSLFast, 1021 FeatureALULSLFast, 1022 FeatureFuseAdrpAdd, 1023 FeatureFuseAES, 1024 FeaturePostRAScheduler, 1025 FeatureEnableSelectOptimize, 1026 FeaturePredictableSelectIsExpensive]>; 1027 1028def TuneX4 : SubtargetFeature<"cortex-x4", "ARMProcFamily", "CortexX4", 1029 "Cortex-X4 ARM processors", [ 1030 FeatureAddrLSLFast, 1031 FeatureALULSLFast, 1032 FeatureFuseAdrpAdd, 1033 FeatureFuseAES, 1034 FeaturePostRAScheduler, 1035 FeatureEnableSelectOptimize, 1036 FeaturePredictableSelectIsExpensive]>; 1037 1038def TuneA64FX : SubtargetFeature<"a64fx", "ARMProcFamily", "A64FX", 1039 "Fujitsu A64FX processors", [ 1040 FeaturePostRAScheduler, 1041 FeatureAggressiveFMA, 1042 FeatureArithmeticBccFusion, 1043 FeatureStorePairSuppress, 1044 FeaturePredictableSelectIsExpensive]>; 1045 1046def TuneCarmel : SubtargetFeature<"carmel", "ARMProcFamily", "Carmel", 1047 "Nvidia Carmel processors">; 1048 1049// Note that cyclone does not fuse AES instructions, but newer apple chips do 1050// perform the fusion and cyclone is used by default when targetting apple OSes. 1051def TuneAppleA7 : SubtargetFeature<"apple-a7", "ARMProcFamily", "AppleA7", 1052 "Apple A7 (the CPU formerly known as Cyclone)", [ 1053 FeatureAlternateSExtLoadCVTF32Pattern, 1054 FeatureArithmeticBccFusion, 1055 FeatureArithmeticCbzFusion, 1056 FeatureDisableLatencySchedHeuristic, 1057 FeatureFuseAES, FeatureFuseCryptoEOR, 1058 FeatureStorePairSuppress, 1059 FeatureZCRegMove, 1060 FeatureZCZeroing, 1061 FeatureZCZeroingFPWorkaround]>; 1062 1063def TuneAppleA10 : SubtargetFeature<"apple-a10", "ARMProcFamily", "AppleA10", 1064 "Apple A10", [ 1065 FeatureAlternateSExtLoadCVTF32Pattern, 1066 FeatureArithmeticBccFusion, 1067 FeatureArithmeticCbzFusion, 1068 FeatureDisableLatencySchedHeuristic, 1069 FeatureFuseAES, 1070 FeatureFuseCryptoEOR, 1071 FeatureStorePairSuppress, 1072 FeatureZCRegMove, 1073 FeatureZCZeroing]>; 1074 1075def TuneAppleA11 : SubtargetFeature<"apple-a11", "ARMProcFamily", "AppleA11", 1076 "Apple A11", [ 1077 FeatureAlternateSExtLoadCVTF32Pattern, 1078 FeatureArithmeticBccFusion, 1079 FeatureArithmeticCbzFusion, 1080 FeatureDisableLatencySchedHeuristic, 1081 FeatureFuseAES, 1082 FeatureFuseCryptoEOR, 1083 FeatureStorePairSuppress, 1084 FeatureZCRegMove, 1085 FeatureZCZeroing]>; 1086 1087def TuneAppleA12 : SubtargetFeature<"apple-a12", "ARMProcFamily", "AppleA12", 1088 "Apple A12", [ 1089 FeatureAlternateSExtLoadCVTF32Pattern, 1090 FeatureArithmeticBccFusion, 1091 FeatureArithmeticCbzFusion, 1092 FeatureDisableLatencySchedHeuristic, 1093 FeatureFuseAES, 1094 FeatureFuseCryptoEOR, 1095 FeatureStorePairSuppress, 1096 FeatureZCRegMove, 1097 FeatureZCZeroing]>; 1098 1099def TuneAppleA13 : SubtargetFeature<"apple-a13", "ARMProcFamily", "AppleA13", 1100 "Apple A13", [ 1101 FeatureAlternateSExtLoadCVTF32Pattern, 1102 FeatureArithmeticBccFusion, 1103 FeatureArithmeticCbzFusion, 1104 FeatureDisableLatencySchedHeuristic, 1105 FeatureFuseAES, 1106 FeatureFuseCryptoEOR, 1107 FeatureStorePairSuppress, 1108 FeatureZCRegMove, 1109 FeatureZCZeroing]>; 1110 1111def TuneAppleA14 : SubtargetFeature<"apple-a14", "ARMProcFamily", "AppleA14", 1112 "Apple A14", [ 1113 FeatureAggressiveFMA, 1114 FeatureAlternateSExtLoadCVTF32Pattern, 1115 FeatureArithmeticBccFusion, 1116 FeatureArithmeticCbzFusion, 1117 FeatureDisableLatencySchedHeuristic, 1118 FeatureFuseAddress, 1119 FeatureFuseAES, 1120 FeatureFuseArithmeticLogic, 1121 FeatureFuseCCSelect, 1122 FeatureFuseCryptoEOR, 1123 FeatureFuseAdrpAdd, 1124 FeatureFuseLiterals, 1125 FeatureStorePairSuppress, 1126 FeatureZCRegMove, 1127 FeatureZCZeroing]>; 1128 1129def TuneAppleA15 : SubtargetFeature<"apple-a15", "ARMProcFamily", "AppleA15", 1130 "Apple A15", [ 1131 FeatureAlternateSExtLoadCVTF32Pattern, 1132 FeatureArithmeticBccFusion, 1133 FeatureArithmeticCbzFusion, 1134 FeatureDisableLatencySchedHeuristic, 1135 FeatureFuseAddress, 1136 FeatureFuseAES, 1137 FeatureFuseArithmeticLogic, 1138 FeatureFuseCCSelect, 1139 FeatureFuseCryptoEOR, 1140 FeatureFuseLiterals, 1141 FeatureStorePairSuppress, 1142 FeatureZCRegMove, 1143 FeatureZCZeroing]>; 1144 1145def TuneAppleA16 : SubtargetFeature<"apple-a16", "ARMProcFamily", "AppleA16", 1146 "Apple A16", [ 1147 FeatureAlternateSExtLoadCVTF32Pattern, 1148 FeatureArithmeticBccFusion, 1149 FeatureArithmeticCbzFusion, 1150 FeatureDisableLatencySchedHeuristic, 1151 FeatureFuseAddress, 1152 FeatureFuseAES, 1153 FeatureFuseArithmeticLogic, 1154 FeatureFuseCCSelect, 1155 FeatureFuseCryptoEOR, 1156 FeatureFuseLiterals, 1157 FeatureStorePairSuppress, 1158 FeatureZCRegMove, 1159 FeatureZCZeroing]>; 1160 1161def TuneAppleA17 : SubtargetFeature<"apple-a17", "ARMProcFamily", "AppleA17", 1162 "Apple A17", [ 1163 FeatureAlternateSExtLoadCVTF32Pattern, 1164 FeatureArithmeticBccFusion, 1165 FeatureArithmeticCbzFusion, 1166 FeatureDisableLatencySchedHeuristic, 1167 FeatureFuseAddress, 1168 FeatureFuseAES, 1169 FeatureFuseArithmeticLogic, 1170 FeatureFuseCCSelect, 1171 FeatureFuseCryptoEOR, 1172 FeatureFuseLiterals, 1173 FeatureStorePairSuppress, 1174 FeatureZCRegMove, 1175 FeatureZCZeroing]>; 1176 1177def TuneExynosM3 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3", 1178 "Samsung Exynos-M3 processors", 1179 [FeatureExynosCheapAsMoveHandling, 1180 FeatureForce32BitJumpTables, 1181 FeatureFuseAddress, 1182 FeatureFuseAES, 1183 FeatureFuseCCSelect, 1184 FeatureFuseAdrpAdd, 1185 FeatureFuseLiterals, 1186 FeatureStorePairSuppress, 1187 FeatureAddrLSLFast, 1188 FeatureALULSLFast, 1189 FeaturePostRAScheduler, 1190 FeaturePredictableSelectIsExpensive]>; 1191 1192// Re-uses some scheduling and tunings from the ExynosM3 proc family. 1193def TuneExynosM4 : SubtargetFeature<"exynosm4", "ARMProcFamily", "ExynosM3", 1194 "Samsung Exynos-M4 processors", 1195 [FeatureArithmeticBccFusion, 1196 FeatureArithmeticCbzFusion, 1197 FeatureExynosCheapAsMoveHandling, 1198 FeatureForce32BitJumpTables, 1199 FeatureFuseAddress, 1200 FeatureFuseAES, 1201 FeatureFuseArithmeticLogic, 1202 FeatureFuseCCSelect, 1203 FeatureFuseAdrpAdd, 1204 FeatureFuseLiterals, 1205 FeatureStorePairSuppress, 1206 FeatureAddrLSLFast, 1207 FeatureALULSLFast, 1208 FeaturePostRAScheduler, 1209 FeatureZCZeroing]>; 1210 1211def TuneKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo", 1212 "Qualcomm Kryo processors", [ 1213 FeaturePostRAScheduler, 1214 FeaturePredictableSelectIsExpensive, 1215 FeatureZCZeroing, 1216 FeatureAddrLSLFast, 1217 FeatureALULSLFast, 1218 FeatureStorePairSuppress]>; 1219 1220def TuneFalkor : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor", 1221 "Qualcomm Falkor processors", [ 1222 FeaturePostRAScheduler, 1223 FeaturePredictableSelectIsExpensive, 1224 FeatureZCZeroing, 1225 FeatureStorePairSuppress, 1226 FeatureAddrLSLFast, 1227 FeatureALULSLFast, 1228 FeatureSlowSTRQro]>; 1229 1230def TuneNeoverseE1 : SubtargetFeature<"neoversee1", "ARMProcFamily", "NeoverseE1", 1231 "Neoverse E1 ARM processors", [ 1232 FeatureFuseAES, 1233 FeatureFuseAdrpAdd, 1234 FeaturePostRAScheduler]>; 1235 1236def TuneNeoverseN1 : SubtargetFeature<"neoversen1", "ARMProcFamily", "NeoverseN1", 1237 "Neoverse N1 ARM processors", [ 1238 FeatureFuseAES, 1239 FeatureFuseAdrpAdd, 1240 FeatureAddrLSLFast, 1241 FeatureALULSLFast, 1242 FeaturePostRAScheduler, 1243 FeatureEnableSelectOptimize, 1244 FeaturePredictableSelectIsExpensive]>; 1245 1246def TuneNeoverseN2 : SubtargetFeature<"neoversen2", "ARMProcFamily", "NeoverseN2", 1247 "Neoverse N2 ARM processors", [ 1248 FeatureFuseAES, 1249 FeatureFuseAdrpAdd, 1250 FeatureAddrLSLFast, 1251 FeatureALULSLFast, 1252 FeaturePostRAScheduler, 1253 FeatureEnableSelectOptimize, 1254 FeaturePredictableSelectIsExpensive]>; 1255 1256def TuneNeoverse512TVB : SubtargetFeature<"neoverse512tvb", "ARMProcFamily", "Neoverse512TVB", 1257 "Neoverse 512-TVB ARM processors", [ 1258 FeatureFuseAES, 1259 FeatureFuseAdrpAdd, 1260 FeatureAddrLSLFast, 1261 FeatureALULSLFast, 1262 FeaturePostRAScheduler, 1263 FeatureEnableSelectOptimize, 1264 FeaturePredictableSelectIsExpensive]>; 1265 1266def TuneNeoverseV1 : SubtargetFeature<"neoversev1", "ARMProcFamily", "NeoverseV1", 1267 "Neoverse V1 ARM processors", [ 1268 FeatureFuseAES, 1269 FeatureFuseAdrpAdd, 1270 FeatureAddrLSLFast, 1271 FeatureALULSLFast, 1272 FeaturePostRAScheduler, 1273 FeatureEnableSelectOptimize, 1274 FeaturePredictableSelectIsExpensive, 1275 FeatureNoSVEFPLD1R]>; 1276 1277def TuneNeoverseV2 : SubtargetFeature<"neoversev2", "ARMProcFamily", "NeoverseV2", 1278 "Neoverse V2 ARM processors", [ 1279 FeatureFuseAES, 1280 FeatureFuseAdrpAdd, 1281 FeatureAddrLSLFast, 1282 FeatureALULSLFast, 1283 FeaturePostRAScheduler, 1284 FeatureEnableSelectOptimize, 1285 FeaturePredictableSelectIsExpensive]>; 1286 1287def TuneSaphira : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira", 1288 "Qualcomm Saphira processors", [ 1289 FeaturePostRAScheduler, 1290 FeaturePredictableSelectIsExpensive, 1291 FeatureZCZeroing, 1292 FeatureStorePairSuppress, 1293 FeatureAddrLSLFast, 1294 FeatureALULSLFast]>; 1295 1296def TuneThunderX2T99 : SubtargetFeature<"thunderx2t99", "ARMProcFamily", "ThunderX2T99", 1297 "Cavium ThunderX2 processors", [ 1298 FeatureAggressiveFMA, 1299 FeatureArithmeticBccFusion, 1300 FeaturePostRAScheduler, 1301 FeatureStorePairSuppress, 1302 FeaturePredictableSelectIsExpensive]>; 1303 1304def TuneThunderX3T110 : SubtargetFeature<"thunderx3t110", "ARMProcFamily", 1305 "ThunderX3T110", 1306 "Marvell ThunderX3 processors", [ 1307 FeatureAggressiveFMA, 1308 FeatureArithmeticBccFusion, 1309 FeaturePostRAScheduler, 1310 FeaturePredictableSelectIsExpensive, 1311 FeatureBalanceFPOps, 1312 FeatureStorePairSuppress, 1313 FeatureStrictAlign]>; 1314 1315def TuneThunderX : SubtargetFeature<"thunderx", "ARMProcFamily", "ThunderX", 1316 "Cavium ThunderX processors", [ 1317 FeaturePostRAScheduler, 1318 FeatureStorePairSuppress, 1319 FeaturePredictableSelectIsExpensive]>; 1320 1321def TuneThunderXT88 : SubtargetFeature<"thunderxt88", "ARMProcFamily", 1322 "ThunderXT88", 1323 "Cavium ThunderX processors", [ 1324 FeaturePostRAScheduler, 1325 FeatureStorePairSuppress, 1326 FeaturePredictableSelectIsExpensive]>; 1327 1328def TuneThunderXT81 : SubtargetFeature<"thunderxt81", "ARMProcFamily", 1329 "ThunderXT81", 1330 "Cavium ThunderX processors", [ 1331 FeaturePostRAScheduler, 1332 FeatureStorePairSuppress, 1333 FeaturePredictableSelectIsExpensive]>; 1334 1335def TuneThunderXT83 : SubtargetFeature<"thunderxt83", "ARMProcFamily", 1336 "ThunderXT83", 1337 "Cavium ThunderX processors", [ 1338 FeaturePostRAScheduler, 1339 FeatureStorePairSuppress, 1340 FeaturePredictableSelectIsExpensive]>; 1341 1342def TuneTSV110 : SubtargetFeature<"tsv110", "ARMProcFamily", "TSV110", 1343 "HiSilicon TS-V110 processors", [ 1344 FeatureFuseAES, 1345 FeatureStorePairSuppress, 1346 FeaturePostRAScheduler]>; 1347 1348def TuneAmpere1 : SubtargetFeature<"ampere1", "ARMProcFamily", "Ampere1", 1349 "Ampere Computing Ampere-1 processors", [ 1350 FeaturePostRAScheduler, 1351 FeatureFuseAES, 1352 FeatureAddrLSLFast, 1353 FeatureALULSLFast, 1354 FeatureAggressiveFMA, 1355 FeatureArithmeticBccFusion, 1356 FeatureCmpBccFusion, 1357 FeatureFuseAddress, 1358 FeatureFuseLiterals, 1359 FeatureStorePairSuppress, 1360 FeatureLdpAlignedOnly, 1361 FeatureStpAlignedOnly]>; 1362 1363def TuneAmpere1A : SubtargetFeature<"ampere1a", "ARMProcFamily", "Ampere1A", 1364 "Ampere Computing Ampere-1A processors", [ 1365 FeaturePostRAScheduler, 1366 FeatureFuseAES, 1367 FeatureAddrLSLFast, 1368 FeatureALULSLFast, 1369 FeatureAggressiveFMA, 1370 FeatureArithmeticBccFusion, 1371 FeatureCmpBccFusion, 1372 FeatureFuseAddress, 1373 FeatureFuseLiterals, 1374 FeatureFuseLiterals, 1375 FeatureStorePairSuppress, 1376 FeatureLdpAlignedOnly, 1377 FeatureStpAlignedOnly]>; 1378 1379def ProcessorFeatures { 1380 list<SubtargetFeature> A53 = [HasV8_0aOps, FeatureCRC, FeatureCrypto, 1381 FeatureFPARMv8, FeatureNEON, FeaturePerfMon]; 1382 list<SubtargetFeature> A55 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1383 FeatureNEON, FeatureFullFP16, FeatureDotProd, 1384 FeatureRCPC, FeaturePerfMon]; 1385 list<SubtargetFeature> A510 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon, 1386 FeatureMatMulInt8, FeatureBF16, FeatureAM, 1387 FeatureMTE, FeatureETE, FeatureSVE2BitPerm, 1388 FeatureFP16FML]; 1389 list<SubtargetFeature> A520 = [HasV9_2aOps, FeaturePerfMon, FeatureAM, 1390 FeatureMTE, FeatureETE, FeatureSVE2BitPerm, 1391 FeatureFP16FML]; 1392 list<SubtargetFeature> A65 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1393 FeatureNEON, FeatureFullFP16, FeatureDotProd, 1394 FeatureRCPC, FeatureSSBS, FeatureRAS, 1395 FeaturePerfMon]; 1396 list<SubtargetFeature> A76 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1397 FeatureNEON, FeatureFullFP16, FeatureDotProd, 1398 FeatureRCPC, FeatureSSBS, FeaturePerfMon]; 1399 list<SubtargetFeature> A77 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1400 FeatureNEON, FeatureFullFP16, FeatureDotProd, 1401 FeatureRCPC, FeaturePerfMon, FeatureSSBS]; 1402 list<SubtargetFeature> A78 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1403 FeatureNEON, FeatureFullFP16, FeatureDotProd, 1404 FeatureRCPC, FeaturePerfMon, FeatureSPE, 1405 FeatureSSBS]; 1406 list<SubtargetFeature> A78C = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1407 FeatureNEON, FeatureFullFP16, FeatureDotProd, 1408 FeatureFlagM, FeaturePAuth, 1409 FeaturePerfMon, FeatureRCPC, FeatureSPE, 1410 FeatureSSBS]; 1411 list<SubtargetFeature> A710 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon, 1412 FeatureETE, FeatureMTE, FeatureFP16FML, 1413 FeatureSVE2BitPerm, FeatureBF16, FeatureMatMulInt8]; 1414 list<SubtargetFeature> A715 = [HasV9_0aOps, FeatureNEON, FeatureMTE, 1415 FeatureFP16FML, FeatureSVE, FeatureTRBE, 1416 FeatureSVE2BitPerm, FeatureBF16, FeatureETE, 1417 FeaturePerfMon, FeatureMatMulInt8, FeatureSPE]; 1418 list<SubtargetFeature> A720 = [HasV9_2aOps, FeatureMTE, FeatureFP16FML, 1419 FeatureTRBE, FeatureSVE2BitPerm, FeatureETE, 1420 FeaturePerfMon, FeatureSPE, FeatureSPE_EEF]; 1421 list<SubtargetFeature> R82 = [HasV8_0rOps, FeaturePerfMon, FeatureFullFP16, 1422 FeatureFP16FML, FeatureSSBS, FeaturePredRes, 1423 FeatureSB]; 1424 list<SubtargetFeature> X1 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1425 FeatureNEON, FeatureRCPC, FeaturePerfMon, 1426 FeatureSPE, FeatureFullFP16, FeatureDotProd, 1427 FeatureSSBS]; 1428 list<SubtargetFeature> X1C = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1429 FeatureNEON, FeatureRCPC_IMMO, FeaturePerfMon, 1430 FeatureSPE, FeatureFullFP16, FeatureDotProd, 1431 FeaturePAuth, FeatureSSBS, FeatureFlagM, 1432 FeatureLSE2]; 1433 list<SubtargetFeature> X2 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon, 1434 FeatureMatMulInt8, FeatureBF16, FeatureAM, 1435 FeatureMTE, FeatureETE, FeatureSVE2BitPerm, 1436 FeatureFP16FML]; 1437 list<SubtargetFeature> X3 = [HasV9_0aOps, FeatureSVE, FeatureNEON, 1438 FeaturePerfMon, FeatureETE, FeatureTRBE, 1439 FeatureSPE, FeatureBF16, FeatureMatMulInt8, 1440 FeatureMTE, FeatureSVE2BitPerm, FeatureFullFP16, 1441 FeatureFP16FML]; 1442 list<SubtargetFeature> X4 = [HasV9_2aOps, 1443 FeaturePerfMon, FeatureETE, FeatureTRBE, 1444 FeatureSPE, FeatureMTE, FeatureSVE2BitPerm, 1445 FeatureFP16FML, FeatureSPE_EEF]; 1446 list<SubtargetFeature> A64FX = [HasV8_2aOps, FeatureFPARMv8, FeatureNEON, 1447 FeatureSHA2, FeaturePerfMon, FeatureFullFP16, 1448 FeatureSVE, FeatureComplxNum]; 1449 list<SubtargetFeature> Carmel = [HasV8_2aOps, FeatureNEON, FeatureCrypto, 1450 FeatureFullFP16]; 1451 list<SubtargetFeature> AppleA7 = [HasV8_0aOps, FeatureCrypto, FeatureFPARMv8, 1452 FeatureNEON,FeaturePerfMon, FeatureAppleA7SysReg]; 1453 list<SubtargetFeature> AppleA10 = [HasV8_0aOps, FeatureCrypto, FeatureFPARMv8, 1454 FeatureNEON, FeaturePerfMon, FeatureCRC, 1455 FeatureRDM, FeaturePAN, FeatureLOR, FeatureVH]; 1456 list<SubtargetFeature> AppleA11 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1457 FeatureNEON, FeaturePerfMon, FeatureFullFP16]; 1458 list<SubtargetFeature> AppleA12 = [HasV8_3aOps, FeatureCrypto, FeatureFPARMv8, 1459 FeatureNEON, FeaturePerfMon, FeatureFullFP16]; 1460 list<SubtargetFeature> AppleA13 = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8, 1461 FeatureNEON, FeaturePerfMon, FeatureFullFP16, 1462 FeatureFP16FML, FeatureSHA3]; 1463 list<SubtargetFeature> AppleA14 = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8, 1464 FeatureNEON, FeaturePerfMon, FeatureFRInt3264, 1465 FeatureSpecRestrict, FeatureSSBS, FeatureSB, 1466 FeaturePredRes, FeatureCacheDeepPersist, 1467 FeatureFullFP16, FeatureFP16FML, FeatureSHA3, 1468 FeatureAltFPCmp]; 1469 list<SubtargetFeature> AppleA15 = [HasV8_6aOps, FeatureCrypto, FeatureFPARMv8, 1470 FeatureNEON, FeaturePerfMon, FeatureSHA3, 1471 FeatureFullFP16, FeatureFP16FML]; 1472 list<SubtargetFeature> AppleA16 = [HasV8_6aOps, FeatureCrypto, FeatureFPARMv8, 1473 FeatureNEON, FeaturePerfMon, FeatureSHA3, 1474 FeatureFullFP16, FeatureFP16FML, 1475 FeatureHCX]; 1476 list<SubtargetFeature> AppleA17 = [HasV8_6aOps, FeatureCrypto, FeatureFPARMv8, 1477 FeatureNEON, FeaturePerfMon, FeatureSHA3, 1478 FeatureFullFP16, FeatureFP16FML, 1479 FeatureHCX]; 1480 list<SubtargetFeature> ExynosM3 = [HasV8_0aOps, FeatureCRC, FeatureCrypto, 1481 FeaturePerfMon]; 1482 list<SubtargetFeature> ExynosM4 = [HasV8_2aOps, FeatureCrypto, FeatureDotProd, 1483 FeatureFullFP16, FeaturePerfMon]; 1484 list<SubtargetFeature> Falkor = [HasV8_0aOps, FeatureCRC, FeatureCrypto, 1485 FeatureFPARMv8, FeatureNEON, FeaturePerfMon, 1486 FeatureRDM]; 1487 list<SubtargetFeature> NeoverseE1 = [HasV8_2aOps, FeatureCrypto, FeatureDotProd, 1488 FeatureFPARMv8, FeatureFullFP16, FeatureNEON, 1489 FeatureRCPC, FeatureSSBS, FeaturePerfMon]; 1490 list<SubtargetFeature> NeoverseN1 = [HasV8_2aOps, FeatureCrypto, FeatureDotProd, 1491 FeatureFPARMv8, FeatureFullFP16, FeatureNEON, 1492 FeatureRCPC, FeatureSPE, FeatureSSBS, 1493 FeaturePerfMon]; 1494 list<SubtargetFeature> NeoverseN2 = [HasV9_0aOps, FeatureBF16, FeatureETE, 1495 FeatureMatMulInt8, FeatureMTE, FeatureSVE2, 1496 FeatureSVE2BitPerm, FeatureTRBE, 1497 FeaturePerfMon]; 1498 list<SubtargetFeature> Neoverse512TVB = [HasV8_4aOps, FeatureBF16, FeatureCacheDeepPersist, 1499 FeatureCrypto, FeatureFPARMv8, FeatureFP16FML, 1500 FeatureFullFP16, FeatureMatMulInt8, FeatureNEON, 1501 FeaturePerfMon, FeatureRandGen, FeatureSPE, 1502 FeatureSSBS, FeatureSVE]; 1503 list<SubtargetFeature> NeoverseV1 = [HasV8_4aOps, FeatureBF16, FeatureCacheDeepPersist, 1504 FeatureCrypto, FeatureFPARMv8, FeatureFP16FML, 1505 FeatureFullFP16, FeatureMatMulInt8, FeatureNEON, 1506 FeaturePerfMon, FeatureRandGen, FeatureSPE, 1507 FeatureSSBS, FeatureSVE]; 1508 list<SubtargetFeature> NeoverseV2 = [HasV9_0aOps, FeatureBF16, FeatureSPE, 1509 FeaturePerfMon, FeatureETE, FeatureMatMulInt8, 1510 FeatureNEON, FeatureSVE2BitPerm, FeatureFP16FML, 1511 FeatureMTE, FeatureRandGen]; 1512 list<SubtargetFeature> Saphira = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8, 1513 FeatureNEON, FeatureSPE, FeaturePerfMon]; 1514 list<SubtargetFeature> ThunderX = [HasV8_0aOps, FeatureCRC, FeatureCrypto, 1515 FeatureFPARMv8, FeaturePerfMon, FeatureNEON]; 1516 list<SubtargetFeature> ThunderX2T99 = [HasV8_1aOps, FeatureCRC, FeatureCrypto, 1517 FeatureFPARMv8, FeatureNEON, FeatureLSE]; 1518 list<SubtargetFeature> ThunderX3T110 = [HasV8_3aOps, FeatureCRC, FeatureCrypto, 1519 FeatureFPARMv8, FeatureNEON, FeatureLSE, 1520 FeaturePAuth, FeaturePerfMon]; 1521 list<SubtargetFeature> TSV110 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1522 FeatureNEON, FeaturePerfMon, FeatureSPE, 1523 FeatureFullFP16, FeatureFP16FML, FeatureDotProd]; 1524 list<SubtargetFeature> Ampere1 = [HasV8_6aOps, FeatureNEON, FeaturePerfMon, 1525 FeatureSSBS, FeatureRandGen, FeatureSB, 1526 FeatureSHA2, FeatureSHA3, FeatureAES]; 1527 list<SubtargetFeature> Ampere1A = [HasV8_6aOps, FeatureNEON, FeaturePerfMon, 1528 FeatureMTE, FeatureSSBS, FeatureRandGen, 1529 FeatureSB, FeatureSM4, FeatureSHA2, 1530 FeatureSHA3, FeatureAES]; 1531 1532 // ETE and TRBE are future architecture extensions. We temporarily enable them 1533 // by default for users targeting generic AArch64. The extensions do not 1534 // affect code generated by the compiler and can be used only by explicitly 1535 // mentioning the new system register names in assembly. 1536 list<SubtargetFeature> Generic = [FeatureFPARMv8, FeatureNEON, FeatureETE]; 1537} 1538 1539// FeatureFuseAdrpAdd is enabled under Generic to allow linker merging 1540// optimizations. 1541def : ProcessorModel<"generic", CortexA510Model, ProcessorFeatures.Generic, 1542 [FeatureFuseAES, FeatureFuseAdrpAdd, FeaturePostRAScheduler, 1543 FeatureEnableSelectOptimize]>; 1544def : ProcessorModel<"cortex-a35", CortexA53Model, ProcessorFeatures.A53, 1545 [TuneA35]>; 1546def : ProcessorModel<"cortex-a34", CortexA53Model, ProcessorFeatures.A53, 1547 [TuneA35]>; 1548def : ProcessorModel<"cortex-a53", CortexA53Model, ProcessorFeatures.A53, 1549 [TuneA53]>; 1550def : ProcessorModel<"cortex-a55", CortexA55Model, ProcessorFeatures.A55, 1551 [TuneA55]>; 1552def : ProcessorModel<"cortex-a510", CortexA510Model, ProcessorFeatures.A510, 1553 [TuneA510]>; 1554def : ProcessorModel<"cortex-a520", CortexA510Model, ProcessorFeatures.A520, 1555 [TuneA520]>; 1556def : ProcessorModel<"cortex-a57", CortexA57Model, ProcessorFeatures.A53, 1557 [TuneA57]>; 1558def : ProcessorModel<"cortex-a65", CortexA53Model, ProcessorFeatures.A65, 1559 [TuneA65]>; 1560def : ProcessorModel<"cortex-a65ae", CortexA53Model, ProcessorFeatures.A65, 1561 [TuneA65]>; 1562def : ProcessorModel<"cortex-a72", CortexA57Model, ProcessorFeatures.A53, 1563 [TuneA72]>; 1564def : ProcessorModel<"cortex-a73", CortexA57Model, ProcessorFeatures.A53, 1565 [TuneA73]>; 1566def : ProcessorModel<"cortex-a75", CortexA57Model, ProcessorFeatures.A55, 1567 [TuneA75]>; 1568def : ProcessorModel<"cortex-a76", CortexA57Model, ProcessorFeatures.A76, 1569 [TuneA76]>; 1570def : ProcessorModel<"cortex-a76ae", CortexA57Model, ProcessorFeatures.A76, 1571 [TuneA76]>; 1572def : ProcessorModel<"cortex-a77", CortexA57Model, ProcessorFeatures.A77, 1573 [TuneA77]>; 1574def : ProcessorModel<"cortex-a78", CortexA57Model, ProcessorFeatures.A78, 1575 [TuneA78]>; 1576def : ProcessorModel<"cortex-a78c", CortexA57Model, ProcessorFeatures.A78C, 1577 [TuneA78C]>; 1578def : ProcessorModel<"cortex-a710", NeoverseN2Model, ProcessorFeatures.A710, 1579 [TuneA710]>; 1580def : ProcessorModel<"cortex-a715", NeoverseN2Model, ProcessorFeatures.A715, 1581 [TuneA715]>; 1582def : ProcessorModel<"cortex-a720", NeoverseN2Model, ProcessorFeatures.A720, 1583 [TuneA720]>; 1584def : ProcessorModel<"cortex-r82", CortexA55Model, ProcessorFeatures.R82, 1585 [TuneR82]>; 1586def : ProcessorModel<"cortex-x1", CortexA57Model, ProcessorFeatures.X1, 1587 [TuneX1]>; 1588def : ProcessorModel<"cortex-x1c", CortexA57Model, ProcessorFeatures.X1C, 1589 [TuneX1]>; 1590def : ProcessorModel<"cortex-x2", NeoverseN2Model, ProcessorFeatures.X2, 1591 [TuneX2]>; 1592def : ProcessorModel<"cortex-x3", NeoverseN2Model, ProcessorFeatures.X3, 1593 [TuneX3]>; 1594def : ProcessorModel<"cortex-x4", NeoverseN2Model, ProcessorFeatures.X4, 1595 [TuneX4]>; 1596def : ProcessorModel<"neoverse-e1", CortexA53Model, 1597 ProcessorFeatures.NeoverseE1, [TuneNeoverseE1]>; 1598def : ProcessorModel<"neoverse-n1", NeoverseN1Model, 1599 ProcessorFeatures.NeoverseN1, [TuneNeoverseN1]>; 1600def : ProcessorModel<"neoverse-n2", NeoverseN2Model, 1601 ProcessorFeatures.NeoverseN2, [TuneNeoverseN2]>; 1602def : ProcessorModel<"neoverse-512tvb", NeoverseV1Model, 1603 ProcessorFeatures.Neoverse512TVB, [TuneNeoverse512TVB]>; 1604def : ProcessorModel<"neoverse-v1", NeoverseV1Model, 1605 ProcessorFeatures.NeoverseV1, [TuneNeoverseV1]>; 1606def : ProcessorModel<"neoverse-v2", NeoverseV2Model, 1607 ProcessorFeatures.NeoverseV2, [TuneNeoverseV2]>; 1608def : ProcessorModel<"exynos-m3", ExynosM3Model, ProcessorFeatures.ExynosM3, 1609 [TuneExynosM3]>; 1610def : ProcessorModel<"exynos-m4", ExynosM4Model, ProcessorFeatures.ExynosM4, 1611 [TuneExynosM4]>; 1612def : ProcessorModel<"exynos-m5", ExynosM5Model, ProcessorFeatures.ExynosM4, 1613 [TuneExynosM4]>; 1614def : ProcessorModel<"falkor", FalkorModel, ProcessorFeatures.Falkor, 1615 [TuneFalkor]>; 1616def : ProcessorModel<"saphira", FalkorModel, ProcessorFeatures.Saphira, 1617 [TuneSaphira]>; 1618def : ProcessorModel<"kryo", KryoModel, ProcessorFeatures.A53, [TuneKryo]>; 1619 1620// Cavium ThunderX/ThunderX T8X Processors 1621def : ProcessorModel<"thunderx", ThunderXT8XModel, ProcessorFeatures.ThunderX, 1622 [TuneThunderX]>; 1623def : ProcessorModel<"thunderxt88", ThunderXT8XModel, 1624 ProcessorFeatures.ThunderX, [TuneThunderXT88]>; 1625def : ProcessorModel<"thunderxt81", ThunderXT8XModel, 1626 ProcessorFeatures.ThunderX, [TuneThunderXT81]>; 1627def : ProcessorModel<"thunderxt83", ThunderXT8XModel, 1628 ProcessorFeatures.ThunderX, [TuneThunderXT83]>; 1629// Cavium ThunderX2T9X Processors. Formerly Broadcom Vulcan. 1630def : ProcessorModel<"thunderx2t99", ThunderX2T99Model, 1631 ProcessorFeatures.ThunderX2T99, [TuneThunderX2T99]>; 1632// Marvell ThunderX3T110 Processors. 1633def : ProcessorModel<"thunderx3t110", ThunderX3T110Model, 1634 ProcessorFeatures.ThunderX3T110, [TuneThunderX3T110]>; 1635def : ProcessorModel<"tsv110", TSV110Model, ProcessorFeatures.TSV110, 1636 [TuneTSV110]>; 1637 1638// Support cyclone as an alias for apple-a7 so we can still LTO old bitcode. 1639def : ProcessorModel<"cyclone", CycloneModel, ProcessorFeatures.AppleA7, 1640 [TuneAppleA7]>; 1641 1642// iPhone and iPad CPUs 1643def : ProcessorModel<"apple-a7", CycloneModel, ProcessorFeatures.AppleA7, 1644 [TuneAppleA7]>; 1645def : ProcessorModel<"apple-a8", CycloneModel, ProcessorFeatures.AppleA7, 1646 [TuneAppleA7]>; 1647def : ProcessorModel<"apple-a9", CycloneModel, ProcessorFeatures.AppleA7, 1648 [TuneAppleA7]>; 1649def : ProcessorModel<"apple-a10", CycloneModel, ProcessorFeatures.AppleA10, 1650 [TuneAppleA10]>; 1651def : ProcessorModel<"apple-a11", CycloneModel, ProcessorFeatures.AppleA11, 1652 [TuneAppleA11]>; 1653def : ProcessorModel<"apple-a12", CycloneModel, ProcessorFeatures.AppleA12, 1654 [TuneAppleA12]>; 1655def : ProcessorModel<"apple-a13", CycloneModel, ProcessorFeatures.AppleA13, 1656 [TuneAppleA13]>; 1657def : ProcessorModel<"apple-a14", CycloneModel, ProcessorFeatures.AppleA14, 1658 [TuneAppleA14]>; 1659def : ProcessorModel<"apple-a15", CycloneModel, ProcessorFeatures.AppleA15, 1660 [TuneAppleA15]>; 1661def : ProcessorModel<"apple-a16", CycloneModel, ProcessorFeatures.AppleA16, 1662 [TuneAppleA16]>; 1663def : ProcessorModel<"apple-a17", CycloneModel, ProcessorFeatures.AppleA17, 1664 [TuneAppleA17]>; 1665// Mac CPUs 1666def : ProcessorModel<"apple-m1", CycloneModel, ProcessorFeatures.AppleA14, 1667 [TuneAppleA14]>; 1668def : ProcessorModel<"apple-m2", CycloneModel, ProcessorFeatures.AppleA15, 1669 [TuneAppleA15]>; 1670def : ProcessorModel<"apple-m3", CycloneModel, ProcessorFeatures.AppleA16, 1671 [TuneAppleA16]>; 1672 1673// watch CPUs. 1674def : ProcessorModel<"apple-s4", CycloneModel, ProcessorFeatures.AppleA12, 1675 [TuneAppleA12]>; 1676def : ProcessorModel<"apple-s5", CycloneModel, ProcessorFeatures.AppleA12, 1677 [TuneAppleA12]>; 1678 1679// Alias for the latest Apple processor model supported by LLVM. 1680def : ProcessorModel<"apple-latest", CycloneModel, ProcessorFeatures.AppleA16, 1681 [TuneAppleA16]>; 1682 1683// Fujitsu A64FX 1684def : ProcessorModel<"a64fx", A64FXModel, ProcessorFeatures.A64FX, 1685 [TuneA64FX]>; 1686 1687// Nvidia Carmel 1688def : ProcessorModel<"carmel", NoSchedModel, ProcessorFeatures.Carmel, 1689 [TuneCarmel]>; 1690 1691// Ampere Computing 1692def : ProcessorModel<"ampere1", Ampere1Model, ProcessorFeatures.Ampere1, 1693 [TuneAmpere1]>; 1694 1695def : ProcessorModel<"ampere1a", Ampere1Model, ProcessorFeatures.Ampere1A, 1696 [TuneAmpere1A]>; 1697 1698//===----------------------------------------------------------------------===// 1699// Assembly parser 1700//===----------------------------------------------------------------------===// 1701 1702def GenericAsmParserVariant : AsmParserVariant { 1703 int Variant = 0; 1704 string Name = "generic"; 1705 string BreakCharacters = "."; 1706 string TokenizingCharacters = "[]*!/"; 1707} 1708 1709def AppleAsmParserVariant : AsmParserVariant { 1710 int Variant = 1; 1711 string Name = "apple-neon"; 1712 string BreakCharacters = "."; 1713 string TokenizingCharacters = "[]*!/"; 1714} 1715 1716//===----------------------------------------------------------------------===// 1717// Assembly printer 1718//===----------------------------------------------------------------------===// 1719// AArch64 Uses the MC printer for asm output, so make sure the TableGen 1720// AsmWriter bits get associated with the correct class. 1721def GenericAsmWriter : AsmWriter { 1722 string AsmWriterClassName = "InstPrinter"; 1723 int PassSubtarget = 1; 1724 int Variant = 0; 1725 bit isMCAsmWriter = 1; 1726} 1727 1728def AppleAsmWriter : AsmWriter { 1729 let AsmWriterClassName = "AppleInstPrinter"; 1730 int PassSubtarget = 1; 1731 int Variant = 1; 1732 int isMCAsmWriter = 1; 1733} 1734 1735//===----------------------------------------------------------------------===// 1736// Target Declaration 1737//===----------------------------------------------------------------------===// 1738 1739def AArch64 : Target { 1740 let InstructionSet = AArch64InstrInfo; 1741 let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant]; 1742 let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter]; 1743 let AllowRegisterRenaming = 1; 1744} 1745 1746//===----------------------------------------------------------------------===// 1747// Pfm Counters 1748//===----------------------------------------------------------------------===// 1749 1750include "AArch64PfmCounters.td" 1751