xref: /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AArch64.td (revision 0d8fe2373503aeac48492f28073049a8bfa4feb5)
1//=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//
10//===----------------------------------------------------------------------===//
11
12//===----------------------------------------------------------------------===//
13// Target-independent interfaces which we are implementing.
14//===----------------------------------------------------------------------===//
15
16include "llvm/Target/Target.td"
17
18//===----------------------------------------------------------------------===//
19// AArch64 Subtarget features.
20//
21
22def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
23                                       "Enable ARMv8 FP">;
24
25def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
26  "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
27
28def FeatureSM4 : SubtargetFeature<
29    "sm4", "HasSM4", "true",
30    "Enable SM3 and SM4 support", [FeatureNEON]>;
31
32def FeatureSHA2 : SubtargetFeature<
33    "sha2", "HasSHA2", "true",
34    "Enable SHA1 and SHA256 support", [FeatureNEON]>;
35
36def FeatureSHA3 : SubtargetFeature<
37    "sha3", "HasSHA3", "true",
38    "Enable SHA512 and SHA3 support", [FeatureNEON, FeatureSHA2]>;
39
40def FeatureAES : SubtargetFeature<
41    "aes", "HasAES", "true",
42    "Enable AES support", [FeatureNEON]>;
43
44// Crypto has been split up and any combination is now valid (see the
45// crypto definitions above). Also, crypto is now context sensitive:
46// it has a different meaning for e.g. Armv8.4 than it has for Armv8.2.
47// Therefore, we rely on Clang, the user interacing tool, to pass on the
48// appropriate crypto options. But here in the backend, crypto has very little
49// meaning anymore. We kept the Crypto definition here for backward
50// compatibility, and now imply features SHA2 and AES, which was the
51// "traditional" meaning of Crypto.
52def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
53  "Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>;
54
55def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
56  "Enable ARMv8 CRC-32 checksum instructions">;
57
58def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
59  "Enable ARMv8 Reliability, Availability and Serviceability Extensions">;
60
61def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true",
62  "Enable ARMv8.1 Large System Extension (LSE) atomic instructions">;
63
64def FeatureOutlineAtomics : SubtargetFeature<"outline-atomics", "OutlineAtomics", "true",
65  "Enable out of line atomics to support LSE instructions">;
66
67def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true",
68  "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions">;
69
70def FeaturePAN : SubtargetFeature<
71    "pan", "HasPAN", "true",
72    "Enables ARM v8.1 Privileged Access-Never extension">;
73
74def FeatureLOR : SubtargetFeature<
75    "lor", "HasLOR", "true",
76    "Enables ARM v8.1 Limited Ordering Regions extension">;
77
78def FeatureCONTEXTIDREL2 : SubtargetFeature<"CONTEXTIDREL2", "HasCONTEXTIDREL2",
79    "true", "Enable RW operand CONTEXTIDR_EL2" >;
80
81def FeatureVH : SubtargetFeature<"vh", "HasVH", "true",
82    "Enables ARM v8.1 Virtual Host extension", [FeatureCONTEXTIDREL2] >;
83
84def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
85  "Enable ARMv8 PMUv3 Performance Monitors extension">;
86
87def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
88  "Full FP16", [FeatureFPARMv8]>;
89
90def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true",
91  "Enable FP16 FML instructions", [FeatureFullFP16]>;
92
93def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true",
94  "Enable Statistical Profiling extension">;
95
96def FeaturePAN_RWV : SubtargetFeature<
97    "pan-rwv", "HasPAN_RWV", "true",
98    "Enable v8.2 PAN s1e1R and s1e1W Variants",
99    [FeaturePAN]>;
100
101// UAO PState
102def FeaturePsUAO : SubtargetFeature< "uaops", "HasPsUAO", "true",
103    "Enable v8.2 UAO PState">;
104
105def FeatureCCPP : SubtargetFeature<"ccpp", "HasCCPP",
106    "true", "Enable v8.2 data Cache Clean to Point of Persistence" >;
107
108def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true",
109  "Enable Scalable Vector Extension (SVE) instructions", [FeatureFullFP16]>;
110
111// This flag is currently still labeled as Experimental, but when fully
112// implemented this should tell the compiler to use the zeroing pseudos to
113// benefit from the reverse instructions (e.g. SUB vs SUBR) if the inactive
114// lanes are known to be zero. The pseudos will then be expanded using the
115// MOVPRFX instruction to zero the inactive lanes. This feature should only be
116// enabled if MOVPRFX instructions are known to merge with the destructive
117// operations they prefix.
118//
119// This feature could similarly be extended to support cheap merging of _any_
120// value into the inactive lanes using the MOVPRFX instruction that uses
121// merging-predication.
122def FeatureExperimentalZeroingPseudos
123    : SubtargetFeature<"use-experimental-zeroing-pseudos",
124                       "UseExperimentalZeroingPseudos", "true",
125                       "Hint to the compiler that the MOVPRFX instruction is "
126                       "merged with destructive operations",
127                       []>;
128
129def FeatureSVE2 : SubtargetFeature<"sve2", "HasSVE2", "true",
130  "Enable Scalable Vector Extension 2 (SVE2) instructions", [FeatureSVE]>;
131
132def FeatureSVE2AES : SubtargetFeature<"sve2-aes", "HasSVE2AES", "true",
133  "Enable AES SVE2 instructions", [FeatureSVE2, FeatureAES]>;
134
135def FeatureSVE2SM4 : SubtargetFeature<"sve2-sm4", "HasSVE2SM4", "true",
136  "Enable SM4 SVE2 instructions", [FeatureSVE2, FeatureSM4]>;
137
138def FeatureSVE2SHA3 : SubtargetFeature<"sve2-sha3", "HasSVE2SHA3", "true",
139  "Enable SHA3 SVE2 instructions", [FeatureSVE2, FeatureSHA3]>;
140
141def FeatureSVE2BitPerm : SubtargetFeature<"sve2-bitperm", "HasSVE2BitPerm", "true",
142  "Enable bit permutation SVE2 instructions", [FeatureSVE2]>;
143
144def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
145                                        "Has zero-cycle register moves">;
146
147def FeatureZCZeroingGP : SubtargetFeature<"zcz-gp", "HasZeroCycleZeroingGP", "true",
148                                        "Has zero-cycle zeroing instructions for generic registers">;
149
150def FeatureZCZeroingFP : SubtargetFeature<"zcz-fp", "HasZeroCycleZeroingFP", "true",
151                                        "Has zero-cycle zeroing instructions for FP registers">;
152
153def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
154                                        "Has zero-cycle zeroing instructions",
155                                        [FeatureZCZeroingGP, FeatureZCZeroingFP]>;
156
157/// ... but the floating-point version doesn't quite work in rare cases on older
158/// CPUs.
159def FeatureZCZeroingFPWorkaround : SubtargetFeature<"zcz-fp-workaround",
160    "HasZeroCycleZeroingFPWorkaround", "true",
161    "The zero-cycle floating-point zeroing instruction has a bug">;
162
163def FeatureStrictAlign : SubtargetFeature<"strict-align",
164                                          "StrictAlign", "true",
165                                          "Disallow all unaligned memory "
166                                          "access">;
167
168foreach i = {1-7,9-15,18,20-28,30} in
169    def FeatureReserveX#i : SubtargetFeature<"reserve-x"#i, "ReserveXRegister["#i#"]", "true",
170                                             "Reserve X"#i#", making it unavailable "
171                                             "as a GPR">;
172
173foreach i = {8-15,18} in
174    def FeatureCallSavedX#i : SubtargetFeature<"call-saved-x"#i,
175         "CustomCallSavedXRegs["#i#"]", "true", "Make X"#i#" callee saved.">;
176
177def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
178                                    "Use alias analysis during codegen">;
179
180def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps",
181    "true",
182    "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">;
183
184def FeaturePredictableSelectIsExpensive : SubtargetFeature<
185    "predictable-select-expensive", "PredictableSelectIsExpensive", "true",
186    "Prefer likely predicted branches over selects">;
187
188def FeatureCustomCheapAsMoveHandling : SubtargetFeature<"custom-cheap-as-move",
189    "CustomAsCheapAsMove", "true",
190    "Use custom handling of cheap instructions">;
191
192def FeatureExynosCheapAsMoveHandling : SubtargetFeature<"exynos-cheap-as-move",
193    "ExynosAsCheapAsMove", "true",
194    "Use Exynos specific handling of cheap instructions",
195    [FeatureCustomCheapAsMoveHandling]>;
196
197def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
198    "UsePostRAScheduler", "true", "Schedule again after register allocation">;
199
200def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store",
201    "Misaligned128StoreIsSlow", "true", "Misaligned 128 bit stores are slow">;
202
203def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128",
204    "Paired128IsSlow", "true", "Paired 128 bit loads and stores are slow">;
205
206def FeatureSlowSTRQro : SubtargetFeature<"slow-strqro-store", "STRQroIsSlow",
207    "true", "STR of Q register with register offset is slow">;
208
209def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature<
210    "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern",
211    "true", "Use alternative pattern for sextload convert to f32">;
212
213def FeatureArithmeticBccFusion : SubtargetFeature<
214    "arith-bcc-fusion", "HasArithmeticBccFusion", "true",
215    "CPU fuses arithmetic+bcc operations">;
216
217def FeatureArithmeticCbzFusion : SubtargetFeature<
218    "arith-cbz-fusion", "HasArithmeticCbzFusion", "true",
219    "CPU fuses arithmetic + cbz/cbnz operations">;
220
221def FeatureCmpBccFusion : SubtargetFeature<
222    "cmp-bcc-fusion", "HasCmpBccFusion", "true",
223    "CPU fuses cmp+bcc operations">;
224
225def FeatureFuseAddress : SubtargetFeature<
226    "fuse-address", "HasFuseAddress", "true",
227    "CPU fuses address generation and memory operations">;
228
229def FeatureFuseAES : SubtargetFeature<
230    "fuse-aes", "HasFuseAES", "true",
231    "CPU fuses AES crypto operations">;
232
233def FeatureFuseArithmeticLogic : SubtargetFeature<
234    "fuse-arith-logic", "HasFuseArithmeticLogic", "true",
235    "CPU fuses arithmetic and logic operations">;
236
237def FeatureFuseCCSelect : SubtargetFeature<
238    "fuse-csel", "HasFuseCCSelect", "true",
239    "CPU fuses conditional select operations">;
240
241def FeatureFuseCryptoEOR : SubtargetFeature<
242    "fuse-crypto-eor", "HasFuseCryptoEOR", "true",
243    "CPU fuses AES/PMULL and EOR operations">;
244
245def FeatureFuseLiterals : SubtargetFeature<
246    "fuse-literals", "HasFuseLiterals", "true",
247    "CPU fuses literal generation operations">;
248
249def FeatureDisableLatencySchedHeuristic : SubtargetFeature<
250    "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
251    "Disable latency scheduling heuristic">;
252
253def FeatureForce32BitJumpTables
254   : SubtargetFeature<"force-32bit-jump-tables", "Force32BitJumpTables", "true",
255                      "Force jump table entries to be 32-bits wide except at MinSize">;
256
257def FeatureRCPC : SubtargetFeature<"rcpc", "HasRCPC", "true",
258                                   "Enable support for RCPC extension">;
259
260def FeatureUseRSqrt : SubtargetFeature<
261    "use-reciprocal-square-root", "UseRSqrt", "true",
262    "Use the reciprocal square root approximation">;
263
264def FeatureDotProd : SubtargetFeature<
265    "dotprod", "HasDotProd", "true",
266    "Enable dot product support">;
267
268def FeaturePAuth : SubtargetFeature<
269    "pauth", "HasPAuth", "true",
270    "Enable v8.3-A Pointer Authentication extension">;
271
272def FeatureJS : SubtargetFeature<
273    "jsconv", "HasJS", "true",
274    "Enable v8.3-A JavaScript FP conversion instructions",
275    [FeatureFPARMv8]>;
276
277def FeatureCCIDX : SubtargetFeature<
278    "ccidx", "HasCCIDX", "true",
279    "Enable v8.3-A Extend of the CCSIDR number of sets">;
280
281def FeatureComplxNum : SubtargetFeature<
282    "complxnum", "HasComplxNum", "true",
283    "Enable v8.3-A Floating-point complex number support",
284    [FeatureNEON]>;
285
286def FeatureNV : SubtargetFeature<
287    "nv", "HasNV", "true",
288    "Enable v8.4-A Nested Virtualization Enchancement">;
289
290def FeatureMPAM : SubtargetFeature<
291    "mpam", "HasMPAM", "true",
292    "Enable v8.4-A Memory system Partitioning and Monitoring extension">;
293
294def FeatureDIT : SubtargetFeature<
295    "dit", "HasDIT", "true",
296    "Enable v8.4-A Data Independent Timing instructions">;
297
298def FeatureTRACEV8_4 : SubtargetFeature<
299    "tracev8.4", "HasTRACEV8_4", "true",
300    "Enable v8.4-A Trace extension">;
301
302def FeatureAM : SubtargetFeature<
303    "am", "HasAM", "true",
304    "Enable v8.4-A Activity Monitors extension">;
305
306def FeatureAMVS : SubtargetFeature<
307    "amvs", "HasAMVS", "true",
308    "Enable v8.6-A Activity Monitors Virtualization support",
309    [FeatureAM]>;
310
311def FeatureSEL2 : SubtargetFeature<
312    "sel2", "HasSEL2", "true",
313    "Enable v8.4-A Secure Exception Level 2 extension">;
314
315def FeaturePMU : SubtargetFeature<
316    "pmu", "HasPMU", "true",
317    "Enable v8.4-A PMU extension">;
318
319def FeatureTLB_RMI : SubtargetFeature<
320    "tlb-rmi", "HasTLB_RMI", "true",
321    "Enable v8.4-A TLB Range and Maintenance Instructions">;
322
323def FeatureFlagM : SubtargetFeature<
324    "flagm", "HasFlagM", "true",
325    "Enable v8.4-A Flag Manipulation Instructions">;
326
327// 8.4 RCPC enchancements: LDAPR & STLR instructions with Immediate Offset
328def FeatureRCPC_IMMO : SubtargetFeature<"rcpc-immo", "HasRCPC_IMMO", "true",
329    "Enable v8.4-A RCPC instructions with Immediate Offsets",
330    [FeatureRCPC]>;
331
332def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates",
333                                        "NegativeImmediates", "false",
334                                        "Convert immediates and instructions "
335                                        "to their negated or complemented "
336                                        "equivalent when the immediate does "
337                                        "not fit in the encoding.">;
338
339def FeatureLSLFast : SubtargetFeature<
340    "lsl-fast", "HasLSLFast", "true",
341    "CPU has a fastpath logical shift of up to 3 places">;
342
343def FeatureAggressiveFMA :
344  SubtargetFeature<"aggressive-fma",
345                   "HasAggressiveFMA",
346                   "true",
347                   "Enable Aggressive FMA for floating-point.">;
348
349def FeatureAltFPCmp : SubtargetFeature<"altnzcv", "HasAlternativeNZCV", "true",
350  "Enable alternative NZCV format for floating point comparisons">;
351
352def FeatureFRInt3264 : SubtargetFeature<"fptoint", "HasFRInt3264", "true",
353  "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to "
354  "an integer (in FP format) forcing it to fit into a 32- or 64-bit int" >;
355
356def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict",
357  "true", "Enable architectural speculation restriction" >;
358
359def FeatureSB : SubtargetFeature<"sb", "HasSB",
360  "true", "Enable v8.5 Speculation Barrier" >;
361
362def FeatureSSBS : SubtargetFeature<"ssbs", "HasSSBS",
363  "true", "Enable Speculative Store Bypass Safe bit" >;
364
365def FeaturePredRes : SubtargetFeature<"predres", "HasPredRes", "true",
366  "Enable v8.5a execution and data prediction invalidation instructions" >;
367
368def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP",
369    "true", "Enable v8.5 Cache Clean to Point of Deep Persistence" >;
370
371def FeatureBranchTargetId : SubtargetFeature<"bti", "HasBTI",
372    "true", "Enable Branch Target Identification" >;
373
374def FeatureRandGen : SubtargetFeature<"rand", "HasRandGen",
375    "true", "Enable Random Number generation instructions" >;
376
377def FeatureMTE : SubtargetFeature<"mte", "HasMTE",
378    "true", "Enable Memory Tagging Extension" >;
379
380def FeatureTRBE : SubtargetFeature<"trbe", "HasTRBE",
381    "true", "Enable Trace Buffer Extension">;
382
383def FeatureETE : SubtargetFeature<"ete", "HasETE",
384    "true", "Enable Embedded Trace Extension",
385    [FeatureTRBE]>;
386
387def FeatureTME : SubtargetFeature<"tme", "HasTME",
388    "true", "Enable Transactional Memory Extension" >;
389
390def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
391    "AllowTaggedGlobals",
392    "true", "Use an instruction sequence for taking the address of a global "
393    "that allows a memory tag in the upper address bits">;
394
395def FeatureBF16 : SubtargetFeature<"bf16", "HasBF16",
396    "true", "Enable BFloat16 Extension" >;
397
398def FeatureMatMulInt8 : SubtargetFeature<"i8mm", "HasMatMulInt8",
399    "true", "Enable Matrix Multiply Int8 Extension">;
400
401def FeatureMatMulFP32 : SubtargetFeature<"f32mm", "HasMatMulFP32",
402    "true", "Enable Matrix Multiply FP32 Extension", [FeatureSVE]>;
403
404def FeatureMatMulFP64 : SubtargetFeature<"f64mm", "HasMatMulFP64",
405    "true", "Enable Matrix Multiply FP64 Extension", [FeatureSVE]>;
406
407def FeatureXS : SubtargetFeature<"xs", "HasXS",
408    "true", "Enable Armv8.7-A limited-TLB-maintenance instruction">;
409
410def FeatureWFxT : SubtargetFeature<"wfxt", "HasWFxT",
411    "true", "Enable Armv8.7-A WFET and WFIT instruction">;
412
413def FeatureHCX : SubtargetFeature<
414    "hcx", "HasHCX", "true", "Enable Armv8.7-A HCRX_EL2 system register">;
415
416def FeatureLS64 : SubtargetFeature<"ls64", "HasLS64",
417    "true", "Enable Armv8.7-A LD64B/ST64B Accelerator Extension">;
418
419def FeatureBRBE : SubtargetFeature<"brbe", "HasBRBE",
420    "true", "Enable Branch Record Buffer Extension">;
421
422def FeatureSPE_EEF : SubtargetFeature<"spe-eef", "HasSPE_EEF",
423    "true", "Enable extra register in the Statistical Profiling Extension">;
424
425def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps",
426    "true", "Enable fine grained virtualization traps extension">;
427
428def FeatureEnhancedCounterVirtualization :
429      SubtargetFeature<"ecv", "HasEnhancedCounterVirtualization",
430      "true", "Enable enhanced counter virtualization extension">;
431
432//===----------------------------------------------------------------------===//
433// Architectures.
434//
435
436def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
437  "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM,
438  FeaturePAN, FeatureLOR, FeatureVH]>;
439
440def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
441  "Support ARM v8.2a instructions", [HasV8_1aOps, FeaturePsUAO,
442  FeaturePAN_RWV, FeatureRAS, FeatureCCPP]>;
443
444def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
445  "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC, FeaturePAuth,
446  FeatureJS, FeatureCCIDX, FeatureComplxNum]>;
447
448def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
449  "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd,
450  FeatureNV, FeatureMPAM, FeatureDIT,
451  FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeaturePMU, FeatureTLB_RMI,
452  FeatureFlagM, FeatureRCPC_IMMO]>;
453
454def HasV8_5aOps : SubtargetFeature<
455  "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",
456  [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict,
457   FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist,
458   FeatureBranchTargetId]>;
459
460def HasV8_6aOps : SubtargetFeature<
461  "v8.6a", "HasV8_6aOps", "true", "Support ARM v8.6a instructions",
462  [HasV8_5aOps, FeatureAMVS, FeatureBF16, FeatureFineGrainedTraps,
463   FeatureEnhancedCounterVirtualization, FeatureMatMulInt8]>;
464
465def HasV8_7aOps : SubtargetFeature<
466  "v8.7a", "HasV8_7aOps", "true", "Support ARM v8.7a instructions",
467  [HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX]>;
468
469def HasV8_0rOps : SubtargetFeature<
470  "v8r", "HasV8_0rOps", "true", "Support ARM v8r instructions",
471  [//v8.1
472  FeatureCRC, FeaturePAN, FeatureRDM, FeatureLSE, FeatureCONTEXTIDREL2,
473  //v8.2
474  FeaturePerfMon, FeatureRAS, FeaturePsUAO, FeatureSM4,
475  FeatureSHA3, FeatureCCPP, FeatureFullFP16, FeaturePAN_RWV,
476  //v8.3
477  FeatureComplxNum, FeatureCCIDX, FeatureJS,
478  FeaturePAuth, FeatureRCPC,
479  //v8.4
480  FeatureDotProd, FeatureFP16FML, FeatureTRACEV8_4,
481  FeatureTLB_RMI, FeatureFlagM, FeatureDIT, FeatureSEL2, FeatureRCPC_IMMO,
482  //v8.5
483  FeatureSSBS, FeaturePredRes, FeatureSB, FeatureSpecRestrict]>;
484
485//===----------------------------------------------------------------------===//
486// Register File Description
487//===----------------------------------------------------------------------===//
488
489include "AArch64RegisterInfo.td"
490include "AArch64RegisterBanks.td"
491include "AArch64CallingConvention.td"
492
493//===----------------------------------------------------------------------===//
494// Instruction Descriptions
495//===----------------------------------------------------------------------===//
496
497include "AArch64Schedule.td"
498include "AArch64InstrInfo.td"
499include "AArch64SchedPredicates.td"
500include "AArch64SchedPredExynos.td"
501include "AArch64Combine.td"
502
503def AArch64InstrInfo : InstrInfo;
504
505//===----------------------------------------------------------------------===//
506// Named operands for MRS/MSR/TLBI/...
507//===----------------------------------------------------------------------===//
508
509include "AArch64SystemOperands.td"
510
511//===----------------------------------------------------------------------===//
512// Access to privileged registers
513//===----------------------------------------------------------------------===//
514
515foreach i = 1-3 in
516def FeatureUseEL#i#ForTP : SubtargetFeature<"tpidr-el"#i, "UseEL"#i#"ForTP",
517  "true", "Permit use of TPIDR_EL"#i#" for the TLS base">;
518
519//===----------------------------------------------------------------------===//
520// Control codegen mitigation against Straight Line Speculation vulnerability.
521//===----------------------------------------------------------------------===//
522
523def FeatureHardenSlsRetBr : SubtargetFeature<"harden-sls-retbr",
524  "HardenSlsRetBr", "true",
525  "Harden against straight line speculation across RET and BR instructions">;
526def FeatureHardenSlsBlr : SubtargetFeature<"harden-sls-blr",
527  "HardenSlsBlr", "true",
528  "Harden against straight line speculation across BLR instructions">;
529
530//===----------------------------------------------------------------------===//
531// AArch64 Processors supported.
532//
533
534//===----------------------------------------------------------------------===//
535// Unsupported features to disable for scheduling models
536//===----------------------------------------------------------------------===//
537
538class AArch64Unsupported { list<Predicate> F; }
539
540def SVEUnsupported : AArch64Unsupported {
541  let F = [HasSVE, HasSVE2, HasSVE2AES, HasSVE2SM4, HasSVE2SHA3,
542           HasSVE2BitPerm];
543}
544
545def PAUnsupported : AArch64Unsupported {
546  let F = [HasPAuth];
547}
548
549include "AArch64SchedA53.td"
550include "AArch64SchedA55.td"
551include "AArch64SchedA57.td"
552include "AArch64SchedCyclone.td"
553include "AArch64SchedFalkor.td"
554include "AArch64SchedKryo.td"
555include "AArch64SchedExynosM3.td"
556include "AArch64SchedExynosM4.td"
557include "AArch64SchedExynosM5.td"
558include "AArch64SchedThunderX.td"
559include "AArch64SchedThunderX2T99.td"
560include "AArch64SchedA64FX.td"
561include "AArch64SchedThunderX3T110.td"
562include "AArch64SchedTSV110.td"
563
564def ProcA35     : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
565                                   "Cortex-A35 ARM processors", [
566                                   FeatureCRC,
567                                   FeatureCrypto,
568                                   FeatureFPARMv8,
569                                   FeatureNEON,
570                                   FeaturePerfMon
571                                   ]>;
572
573def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
574                                   "Cortex-A53 ARM processors", [
575                                   FeatureBalanceFPOps,
576                                   FeatureCRC,
577                                   FeatureCrypto,
578                                   FeatureCustomCheapAsMoveHandling,
579                                   FeatureFPARMv8,
580                                   FeatureFuseAES,
581                                   FeatureNEON,
582                                   FeaturePerfMon,
583                                   FeaturePostRAScheduler,
584                                   FeatureUseAA
585                                   ]>;
586
587def ProcA55     : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55",
588                                   "Cortex-A55 ARM processors", [
589                                   HasV8_2aOps,
590                                   FeatureCrypto,
591                                   FeatureFPARMv8,
592                                   FeatureFuseAES,
593                                   FeatureNEON,
594                                   FeatureFullFP16,
595                                   FeatureDotProd,
596                                   FeatureRCPC,
597                                   FeaturePerfMon
598                                   ]>;
599
600def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
601                                   "Cortex-A57 ARM processors", [
602                                   FeatureBalanceFPOps,
603                                   FeatureCRC,
604                                   FeatureCrypto,
605                                   FeatureCustomCheapAsMoveHandling,
606                                   FeatureFPARMv8,
607                                   FeatureFuseAES,
608                                   FeatureFuseLiterals,
609                                   FeatureNEON,
610                                   FeaturePerfMon,
611                                   FeaturePostRAScheduler,
612                                   FeaturePredictableSelectIsExpensive
613                                   ]>;
614
615def ProcA65     : SubtargetFeature<"a65", "ARMProcFamily", "CortexA65",
616                                   "Cortex-A65 ARM processors", [
617                                   HasV8_2aOps,
618                                   FeatureCrypto,
619                                   FeatureDotProd,
620                                   FeatureFPARMv8,
621                                   FeatureFullFP16,
622                                   FeatureFuseAddress,
623                                   FeatureFuseAES,
624                                   FeatureFuseLiterals,
625                                   FeatureNEON,
626                                   FeatureRAS,
627                                   FeatureRCPC,
628                                   FeatureSSBS,
629                                   ]>;
630
631def ProcA72     : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
632                                   "Cortex-A72 ARM processors", [
633                                   FeatureCRC,
634                                   FeatureCrypto,
635                                   FeatureFPARMv8,
636                                   FeatureFuseAES,
637                                   FeatureFuseLiterals,
638                                   FeatureNEON,
639                                   FeaturePerfMon
640                                   ]>;
641
642def ProcA73     : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
643                                   "Cortex-A73 ARM processors", [
644                                   FeatureCRC,
645                                   FeatureCrypto,
646                                   FeatureFPARMv8,
647                                   FeatureFuseAES,
648                                   FeatureNEON,
649                                   FeaturePerfMon
650                                   ]>;
651
652def ProcA75     : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75",
653                                   "Cortex-A75 ARM processors", [
654                                   HasV8_2aOps,
655                                   FeatureCrypto,
656                                   FeatureFPARMv8,
657                                   FeatureFuseAES,
658                                   FeatureNEON,
659                                   FeatureFullFP16,
660                                   FeatureDotProd,
661                                   FeatureRCPC,
662                                   FeaturePerfMon
663                                   ]>;
664
665def ProcA76     : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76",
666                                   "Cortex-A76 ARM processors", [
667                                    HasV8_2aOps,
668                                    FeatureFPARMv8,
669                                    FeatureFuseAES,
670                                    FeatureNEON,
671                                    FeatureRCPC,
672                                    FeatureCrypto,
673                                    FeatureFullFP16,
674                                    FeatureDotProd,
675                                    FeatureSSBS
676                                    ]>;
677
678def ProcA77     : SubtargetFeature<"a77", "ARMProcFamily", "CortexA77",
679                                   "Cortex-A77 ARM processors", [
680                                    HasV8_2aOps,
681                                    FeatureCmpBccFusion,
682                                    FeatureFPARMv8,
683                                    FeatureFuseAES,
684                                    FeatureNEON, FeatureRCPC,
685                                    FeatureCrypto,
686                                    FeatureFullFP16,
687                                    FeatureDotProd
688                                    ]>;
689
690def ProcA78 : SubtargetFeature<"cortex-a78", "ARMProcFamily",
691                               "CortexA78",
692                               "Cortex-A78 ARM processors", [
693                               HasV8_2aOps,
694                               FeatureCmpBccFusion,
695                               FeatureCrypto,
696                               FeatureFPARMv8,
697                               FeatureFuseAES,
698                               FeatureNEON,
699                               FeatureRCPC,
700                               FeaturePerfMon,
701                               FeaturePostRAScheduler,
702                               FeatureSPE,
703                               FeatureFullFP16,
704                               FeatureSSBS,
705                               FeatureDotProd]>;
706
707def ProcA78C : SubtargetFeature<"cortex-a78c", "ARMProcFamily",
708                                "CortexA78C",
709                                "Cortex-A78C ARM processors", [
710                                HasV8_2aOps,
711                                FeatureCmpBccFusion,
712                                FeatureCrypto,
713                                FeatureDotProd,
714                                FeatureFlagM,
715                                FeatureFP16FML,
716                                FeatureFPARMv8,
717                                FeatureFullFP16,
718                                FeatureFuseAES,
719                                FeatureNEON,
720                                FeaturePAuth,
721                                FeaturePerfMon,
722                                FeaturePostRAScheduler,
723                                FeatureRCPC,
724                                FeatureSPE,
725                                FeatureSSBS]>;
726
727def ProcR82 : SubtargetFeature<"cortex-r82", "ARMProcFamily",
728                               "CortexR82",
729                               "Cortex-R82 ARM Processors", [
730                               FeaturePostRAScheduler,
731                               // TODO: crypto and FuseAES
732                               // All other features are implied by v8_0r ops:
733                               HasV8_0rOps,
734                               ]>;
735
736def ProcX1 : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1",
737                                  "Cortex-X1 ARM processors", [
738                                  HasV8_2aOps,
739                                  FeatureCmpBccFusion,
740                                  FeatureCrypto,
741                                  FeatureFPARMv8,
742                                  FeatureFuseAES,
743                                  FeatureNEON,
744                                  FeatureRCPC,
745                                  FeaturePerfMon,
746                                  FeaturePostRAScheduler,
747                                  FeatureSPE,
748                                  FeatureFullFP16,
749                                  FeatureDotProd]>;
750
751def ProcA64FX : SubtargetFeature<"a64fx", "ARMProcFamily", "A64FX",
752                                 "Fujitsu A64FX processors", [
753                                  HasV8_2aOps,
754                                  FeatureFPARMv8,
755                                  FeatureNEON,
756                                  FeatureSHA2,
757                                  FeaturePerfMon,
758                                  FeatureFullFP16,
759                                  FeatureSVE,
760                                  FeaturePostRAScheduler,
761                                  FeatureComplxNum,
762                                  FeatureAggressiveFMA,
763                                  FeatureArithmeticBccFusion,
764                                  FeaturePredictableSelectIsExpensive
765                                  ]>;
766
767def ProcCarmel : SubtargetFeature<"carmel", "ARMProcFamily", "Carmel",
768                                  "Nvidia Carmel processors", [
769                                   HasV8_2aOps,
770                                   FeatureNEON,
771                                   FeatureCrypto,
772                                   FeatureFullFP16
773                                   ]>;
774
775// Note that cyclone does not fuse AES instructions, but newer apple chips do
776// perform the fusion and cyclone is used by default when targetting apple OSes.
777def ProcAppleA7 : SubtargetFeature<"apple-a7", "ARMProcFamily", "AppleA7",
778                                   "Apple A7 (the CPU formerly known as Cyclone)", [
779                                   FeatureAlternateSExtLoadCVTF32Pattern,
780                                   FeatureArithmeticBccFusion,
781                                   FeatureArithmeticCbzFusion,
782                                   FeatureCrypto,
783                                   FeatureDisableLatencySchedHeuristic,
784                                   FeatureFPARMv8,
785                                   FeatureFuseAES,
786                                   FeatureFuseCryptoEOR,
787                                   FeatureNEON,
788                                   FeaturePerfMon,
789                                   FeatureZCRegMove,
790                                   FeatureZCZeroing,
791                                   FeatureZCZeroingFPWorkaround
792                                   ]>;
793
794def ProcAppleA10 : SubtargetFeature<"apple-a10", "ARMProcFamily", "AppleA10",
795                                    "Apple A10", [
796                                    FeatureAlternateSExtLoadCVTF32Pattern,
797                                    FeatureArithmeticBccFusion,
798                                    FeatureArithmeticCbzFusion,
799                                    FeatureCrypto,
800                                    FeatureDisableLatencySchedHeuristic,
801                                    FeatureFPARMv8,
802                                    FeatureFuseAES,
803                                    FeatureFuseCryptoEOR,
804                                    FeatureNEON,
805                                    FeaturePerfMon,
806                                    FeatureZCRegMove,
807                                    FeatureZCZeroing,
808                                    FeatureCRC,
809                                    FeatureRDM,
810                                    FeaturePAN,
811                                    FeatureLOR,
812                                    FeatureVH,
813                                    ]>;
814
815def ProcAppleA11 : SubtargetFeature<"apple-a11", "ARMProcFamily", "AppleA11",
816                                    "Apple A11", [
817                                    FeatureAlternateSExtLoadCVTF32Pattern,
818                                    FeatureArithmeticBccFusion,
819                                    FeatureArithmeticCbzFusion,
820                                    FeatureCrypto,
821                                    FeatureDisableLatencySchedHeuristic,
822                                    FeatureFPARMv8,
823                                    FeatureFuseAES,
824                                    FeatureFuseCryptoEOR,
825                                    FeatureNEON,
826                                    FeaturePerfMon,
827                                    FeatureZCRegMove,
828                                    FeatureZCZeroing,
829                                    FeatureFullFP16,
830                                    HasV8_2aOps
831                                    ]>;
832
833def ProcAppleA12 : SubtargetFeature<"apple-a12", "ARMProcFamily", "AppleA12",
834                                    "Apple A12", [
835                                    FeatureAlternateSExtLoadCVTF32Pattern,
836                                    FeatureArithmeticBccFusion,
837                                    FeatureArithmeticCbzFusion,
838                                    FeatureCrypto,
839                                    FeatureDisableLatencySchedHeuristic,
840                                    FeatureFPARMv8,
841                                    FeatureFuseAES,
842                                    FeatureFuseCryptoEOR,
843                                    FeatureNEON,
844                                    FeaturePerfMon,
845                                    FeatureZCRegMove,
846                                    FeatureZCZeroing,
847                                    FeatureFullFP16,
848                                    HasV8_3aOps
849                                    ]>;
850
851def ProcAppleA13 : SubtargetFeature<"apple-a13", "ARMProcFamily", "AppleA13",
852                                     "Apple A13", [
853                                     FeatureAlternateSExtLoadCVTF32Pattern,
854                                     FeatureArithmeticBccFusion,
855                                     FeatureArithmeticCbzFusion,
856                                     FeatureCrypto,
857                                     FeatureDisableLatencySchedHeuristic,
858                                     FeatureFPARMv8,
859                                     FeatureFuseAES,
860                                     FeatureFuseCryptoEOR,
861                                     FeatureNEON,
862                                     FeaturePerfMon,
863                                     FeatureZCRegMove,
864                                     FeatureZCZeroing,
865                                     FeatureFullFP16,
866                                     FeatureFP16FML,
867                                     FeatureSHA3,
868                                     HasV8_4aOps
869                                     ]>;
870
871def ProcAppleA14 : SubtargetFeature<"apple-a14", "ARMProcFamily", "AppleA14",
872                                     "Apple A14", [
873                                     FeatureAggressiveFMA,
874                                     FeatureAlternateSExtLoadCVTF32Pattern,
875                                     FeatureAltFPCmp,
876                                     FeatureArithmeticBccFusion,
877                                     FeatureArithmeticCbzFusion,
878                                     FeatureCrypto,
879                                     FeatureDisableLatencySchedHeuristic,
880                                     FeatureFPARMv8,
881                                     FeatureFRInt3264,
882                                     FeatureFuseAddress,
883                                     FeatureFuseAES,
884                                     FeatureFuseArithmeticLogic,
885                                     FeatureFuseCCSelect,
886                                     FeatureFuseCryptoEOR,
887                                     FeatureFuseLiterals,
888                                     FeatureNEON,
889                                     FeaturePerfMon,
890                                     FeatureSpecRestrict,
891                                     FeatureSSBS,
892                                     FeatureSB,
893                                     FeaturePredRes,
894                                     FeatureCacheDeepPersist,
895                                     FeatureZCRegMove,
896                                     FeatureZCZeroing,
897                                     FeatureFullFP16,
898                                     FeatureFP16FML,
899                                     FeatureSHA3,
900                                     HasV8_4aOps
901                                     ]>;
902
903def ProcExynosM3 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3",
904                                    "Samsung Exynos-M3 processors",
905                                    [FeatureCRC,
906                                     FeatureCrypto,
907                                     FeatureExynosCheapAsMoveHandling,
908                                     FeatureForce32BitJumpTables,
909                                     FeatureFuseAddress,
910                                     FeatureFuseAES,
911                                     FeatureFuseCCSelect,
912                                     FeatureFuseLiterals,
913                                     FeatureLSLFast,
914                                     FeaturePerfMon,
915                                     FeaturePostRAScheduler,
916                                     FeaturePredictableSelectIsExpensive,
917                                     FeatureZCZeroingFP]>;
918
919def ProcExynosM4 : SubtargetFeature<"exynosm4", "ARMProcFamily", "ExynosM3",
920                                    "Samsung Exynos-M4 processors",
921                                    [HasV8_2aOps,
922                                     FeatureArithmeticBccFusion,
923                                     FeatureArithmeticCbzFusion,
924                                     FeatureCrypto,
925                                     FeatureDotProd,
926                                     FeatureExynosCheapAsMoveHandling,
927                                     FeatureForce32BitJumpTables,
928                                     FeatureFullFP16,
929                                     FeatureFuseAddress,
930                                     FeatureFuseAES,
931                                     FeatureFuseArithmeticLogic,
932                                     FeatureFuseCCSelect,
933                                     FeatureFuseLiterals,
934                                     FeatureLSLFast,
935                                     FeaturePerfMon,
936                                     FeaturePostRAScheduler,
937                                     FeatureZCZeroing]>;
938
939def ProcKryo    : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
940                                   "Qualcomm Kryo processors", [
941                                   FeatureCRC,
942                                   FeatureCrypto,
943                                   FeatureCustomCheapAsMoveHandling,
944                                   FeatureFPARMv8,
945                                   FeatureNEON,
946                                   FeaturePerfMon,
947                                   FeaturePostRAScheduler,
948                                   FeaturePredictableSelectIsExpensive,
949                                   FeatureZCZeroing,
950                                   FeatureLSLFast
951                                   ]>;
952
953def ProcFalkor  : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor",
954                                   "Qualcomm Falkor processors", [
955                                   FeatureCRC,
956                                   FeatureCrypto,
957                                   FeatureCustomCheapAsMoveHandling,
958                                   FeatureFPARMv8,
959                                   FeatureNEON,
960                                   FeaturePerfMon,
961                                   FeaturePostRAScheduler,
962                                   FeaturePredictableSelectIsExpensive,
963                                   FeatureRDM,
964                                   FeatureZCZeroing,
965                                   FeatureLSLFast,
966                                   FeatureSlowSTRQro
967                                   ]>;
968
969def ProcNeoverseE1 : SubtargetFeature<"neoversee1", "ARMProcFamily",
970                                      "NeoverseE1",
971                                      "Neoverse E1 ARM processors", [
972                                      HasV8_2aOps,
973                                      FeatureCrypto,
974                                      FeatureDotProd,
975                                      FeatureFPARMv8,
976                                      FeatureFullFP16,
977                                      FeatureNEON,
978                                      FeatureRCPC,
979                                      FeatureSSBS,
980                                      ]>;
981
982def ProcNeoverseN1 : SubtargetFeature<"neoversen1", "ARMProcFamily",
983                                      "NeoverseN1",
984                                      "Neoverse N1 ARM processors", [
985                                      HasV8_2aOps,
986                                      FeatureCrypto,
987                                      FeatureDotProd,
988                                      FeatureFPARMv8,
989                                      FeatureFullFP16,
990                                      FeatureNEON,
991                                      FeatureRCPC,
992                                      FeatureSPE,
993                                      FeatureSSBS,
994                                      ]>;
995
996def ProcNeoverseN2 : SubtargetFeature<"neoversen2", "ARMProcFamily",
997                                      "NeoverseN2",
998                                      "Neoverse N2 ARM processors", [
999                                      HasV8_5aOps,
1000                                      FeatureBF16,
1001                                      FeatureETE,
1002                                      FeatureMatMulInt8,
1003                                      FeatureMTE,
1004                                      FeatureSVE2,
1005                                      FeatureSVE2BitPerm,
1006                                      FeatureTRBE]>;
1007
1008def ProcNeoverseV1 : SubtargetFeature<"neoversev1", "ARMProcFamily",
1009                                      "NeoverseV1",
1010                                      "Neoverse V1 ARM processors", [
1011                                      HasV8_4aOps,
1012                                      FeatureBF16,
1013                                      FeatureCacheDeepPersist,
1014                                      FeatureCrypto,
1015                                      FeatureFPARMv8,
1016                                      FeatureFP16FML,
1017                                      FeatureFullFP16,
1018                                      FeatureFuseAES,
1019                                      FeatureMatMulInt8,
1020                                      FeatureNEON,
1021                                      FeaturePerfMon,
1022                                      FeaturePostRAScheduler,
1023                                      FeatureRandGen,
1024                                      FeatureSPE,
1025                                      FeatureSSBS,
1026                                      FeatureSVE]>;
1027
1028def ProcSaphira  : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira",
1029                                   "Qualcomm Saphira processors", [
1030                                   FeatureCrypto,
1031                                   FeatureCustomCheapAsMoveHandling,
1032                                   FeatureFPARMv8,
1033                                   FeatureNEON,
1034                                   FeatureSPE,
1035                                   FeaturePerfMon,
1036                                   FeaturePostRAScheduler,
1037                                   FeaturePredictableSelectIsExpensive,
1038                                   FeatureZCZeroing,
1039                                   FeatureLSLFast,
1040                                   HasV8_4aOps]>;
1041
1042def ProcThunderX2T99  : SubtargetFeature<"thunderx2t99", "ARMProcFamily",
1043                                         "ThunderX2T99",
1044                                         "Cavium ThunderX2 processors", [
1045                                          FeatureAggressiveFMA,
1046                                          FeatureCRC,
1047                                          FeatureCrypto,
1048                                          FeatureFPARMv8,
1049                                          FeatureArithmeticBccFusion,
1050                                          FeatureNEON,
1051                                          FeaturePostRAScheduler,
1052                                          FeaturePredictableSelectIsExpensive,
1053                                          FeatureLSE,
1054                                          HasV8_1aOps]>;
1055
1056def ProcThunderX3T110  : SubtargetFeature<"thunderx3t110", "ARMProcFamily",
1057                                         "ThunderX3T110",
1058                                         "Marvell ThunderX3 processors", [
1059                                          FeatureAggressiveFMA,
1060                                          FeatureCRC,
1061                                          FeatureCrypto,
1062                                          FeatureFPARMv8,
1063                                          FeatureArithmeticBccFusion,
1064                                          FeatureNEON,
1065                                          FeaturePostRAScheduler,
1066                                          FeaturePredictableSelectIsExpensive,
1067                                          FeatureLSE,
1068                                          FeaturePAuth,
1069                                          FeatureUseAA,
1070                                          FeatureBalanceFPOps,
1071                                          FeaturePerfMon,
1072                                          FeatureStrictAlign,
1073                                          HasV8_3aOps]>;
1074
1075def ProcThunderX : SubtargetFeature<"thunderx", "ARMProcFamily", "ThunderX",
1076                                    "Cavium ThunderX processors", [
1077                                    FeatureCRC,
1078                                    FeatureCrypto,
1079                                    FeatureFPARMv8,
1080                                    FeaturePerfMon,
1081                                    FeaturePostRAScheduler,
1082                                    FeaturePredictableSelectIsExpensive,
1083                                    FeatureNEON]>;
1084
1085def ProcThunderXT88 : SubtargetFeature<"thunderxt88", "ARMProcFamily",
1086                                       "ThunderXT88",
1087                                       "Cavium ThunderX processors", [
1088                                       FeatureCRC,
1089                                       FeatureCrypto,
1090                                       FeatureFPARMv8,
1091                                       FeaturePerfMon,
1092                                       FeaturePostRAScheduler,
1093                                       FeaturePredictableSelectIsExpensive,
1094                                       FeatureNEON]>;
1095
1096def ProcThunderXT81 : SubtargetFeature<"thunderxt81", "ARMProcFamily",
1097                                       "ThunderXT81",
1098                                       "Cavium ThunderX processors", [
1099                                       FeatureCRC,
1100                                       FeatureCrypto,
1101                                       FeatureFPARMv8,
1102                                       FeaturePerfMon,
1103                                       FeaturePostRAScheduler,
1104                                       FeaturePredictableSelectIsExpensive,
1105                                       FeatureNEON]>;
1106
1107def ProcThunderXT83 : SubtargetFeature<"thunderxt83", "ARMProcFamily",
1108                                       "ThunderXT83",
1109                                       "Cavium ThunderX processors", [
1110                                       FeatureCRC,
1111                                       FeatureCrypto,
1112                                       FeatureFPARMv8,
1113                                       FeaturePerfMon,
1114                                       FeaturePostRAScheduler,
1115                                       FeaturePredictableSelectIsExpensive,
1116                                       FeatureNEON]>;
1117
1118def ProcTSV110 : SubtargetFeature<"tsv110", "ARMProcFamily", "TSV110",
1119                                  "HiSilicon TS-V110 processors", [
1120                                  HasV8_2aOps,
1121                                  FeatureCrypto,
1122                                  FeatureCustomCheapAsMoveHandling,
1123                                  FeatureFPARMv8,
1124                                  FeatureFuseAES,
1125                                  FeatureNEON,
1126                                  FeaturePerfMon,
1127                                  FeaturePostRAScheduler,
1128                                  FeatureSPE,
1129                                  FeatureFullFP16,
1130                                  FeatureFP16FML,
1131                                  FeatureDotProd]>;
1132
1133def : ProcessorModel<"generic", NoSchedModel, [
1134                     FeatureFPARMv8,
1135                     FeatureFuseAES,
1136                     FeatureNEON,
1137                     FeaturePerfMon,
1138                     FeaturePostRAScheduler,
1139// ETE and TRBE are future architecture extensions. We temporarily enable them
1140// by default for users targeting generic AArch64, until it is decided in which
1141// armv8.x-a architecture revision they will end up. The extensions do not
1142// affect code generated by the compiler and can be used only by explicitly
1143// mentioning the new system register names in assembly.
1144                     FeatureETE
1145                     ]>;
1146
1147def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>;
1148def : ProcessorModel<"cortex-a34", CortexA53Model, [ProcA35]>;
1149def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
1150def : ProcessorModel<"cortex-a55", CortexA55Model, [ProcA55]>;
1151def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
1152def : ProcessorModel<"cortex-a65", CortexA53Model, [ProcA65]>;
1153def : ProcessorModel<"cortex-a65ae", CortexA53Model, [ProcA65]>;
1154def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA72]>;
1155def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA73]>;
1156def : ProcessorModel<"cortex-a75", CortexA57Model, [ProcA75]>;
1157def : ProcessorModel<"cortex-a76", CortexA57Model, [ProcA76]>;
1158def : ProcessorModel<"cortex-a76ae", CortexA57Model, [ProcA76]>;
1159def : ProcessorModel<"cortex-a77", CortexA57Model, [ProcA77]>;
1160def : ProcessorModel<"cortex-a78", CortexA57Model, [ProcA78]>;
1161def : ProcessorModel<"cortex-a78c", CortexA57Model, [ProcA78C]>;
1162def : ProcessorModel<"cortex-r82", CortexA55Model, [ProcR82]>;
1163def : ProcessorModel<"cortex-x1", CortexA57Model, [ProcX1]>;
1164def : ProcessorModel<"neoverse-e1", CortexA53Model, [ProcNeoverseE1]>;
1165def : ProcessorModel<"neoverse-n1", CortexA57Model, [ProcNeoverseN1]>;
1166def : ProcessorModel<"neoverse-n2", CortexA57Model, [ProcNeoverseN2]>;
1167def : ProcessorModel<"neoverse-v1", CortexA57Model, [ProcNeoverseV1]>;
1168def : ProcessorModel<"exynos-m3", ExynosM3Model, [ProcExynosM3]>;
1169def : ProcessorModel<"exynos-m4", ExynosM4Model, [ProcExynosM4]>;
1170def : ProcessorModel<"exynos-m5", ExynosM5Model, [ProcExynosM4]>;
1171def : ProcessorModel<"falkor", FalkorModel, [ProcFalkor]>;
1172def : ProcessorModel<"saphira", FalkorModel, [ProcSaphira]>;
1173def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>;
1174// Cavium ThunderX/ThunderX T8X  Processors
1175def : ProcessorModel<"thunderx", ThunderXT8XModel,  [ProcThunderX]>;
1176def : ProcessorModel<"thunderxt88", ThunderXT8XModel,  [ProcThunderXT88]>;
1177def : ProcessorModel<"thunderxt81", ThunderXT8XModel,  [ProcThunderXT81]>;
1178def : ProcessorModel<"thunderxt83", ThunderXT8XModel,  [ProcThunderXT83]>;
1179// Cavium ThunderX2T9X  Processors. Formerly Broadcom Vulcan.
1180def : ProcessorModel<"thunderx2t99", ThunderX2T99Model, [ProcThunderX2T99]>;
1181// Marvell ThunderX3T110 Processors.
1182def : ProcessorModel<"thunderx3t110", ThunderX3T110Model, [ProcThunderX3T110]>;
1183def : ProcessorModel<"tsv110", TSV110Model, [ProcTSV110]>;
1184
1185// Support cyclone as an alias for apple-a7 so we can still LTO old bitcode.
1186def : ProcessorModel<"cyclone", CycloneModel, [ProcAppleA7]>;
1187
1188// iPhone and iPad CPUs
1189def : ProcessorModel<"apple-a7", CycloneModel, [ProcAppleA7]>;
1190def : ProcessorModel<"apple-a8", CycloneModel, [ProcAppleA7]>;
1191def : ProcessorModel<"apple-a9", CycloneModel, [ProcAppleA7]>;
1192def : ProcessorModel<"apple-a10", CycloneModel, [ProcAppleA10]>;
1193def : ProcessorModel<"apple-a11", CycloneModel, [ProcAppleA11]>;
1194def : ProcessorModel<"apple-a12", CycloneModel, [ProcAppleA12]>;
1195def : ProcessorModel<"apple-a13", CycloneModel, [ProcAppleA13]>;
1196def : ProcessorModel<"apple-a14", CycloneModel, [ProcAppleA14]>;
1197
1198// watch CPUs.
1199def : ProcessorModel<"apple-s4", CycloneModel, [ProcAppleA12]>;
1200def : ProcessorModel<"apple-s5", CycloneModel, [ProcAppleA12]>;
1201
1202// Alias for the latest Apple processor model supported by LLVM.
1203def : ProcessorModel<"apple-latest", CycloneModel, [ProcAppleA13]>;
1204
1205// Fujitsu A64FX
1206def : ProcessorModel<"a64fx", A64FXModel, [ProcA64FX]>;
1207
1208// Nvidia Carmel
1209def : ProcessorModel<"carmel", NoSchedModel, [ProcCarmel]>;
1210
1211//===----------------------------------------------------------------------===//
1212// Assembly parser
1213//===----------------------------------------------------------------------===//
1214
1215def GenericAsmParserVariant : AsmParserVariant {
1216  int Variant = 0;
1217  string Name = "generic";
1218  string BreakCharacters = ".";
1219  string TokenizingCharacters = "[]*!/";
1220}
1221
1222def AppleAsmParserVariant : AsmParserVariant {
1223  int Variant = 1;
1224  string Name = "apple-neon";
1225  string BreakCharacters = ".";
1226  string TokenizingCharacters = "[]*!/";
1227}
1228
1229//===----------------------------------------------------------------------===//
1230// Assembly printer
1231//===----------------------------------------------------------------------===//
1232// AArch64 Uses the MC printer for asm output, so make sure the TableGen
1233// AsmWriter bits get associated with the correct class.
1234def GenericAsmWriter : AsmWriter {
1235  string AsmWriterClassName  = "InstPrinter";
1236  int PassSubtarget = 1;
1237  int Variant = 0;
1238  bit isMCAsmWriter = 1;
1239}
1240
1241def AppleAsmWriter : AsmWriter {
1242  let AsmWriterClassName = "AppleInstPrinter";
1243  int PassSubtarget = 1;
1244  int Variant = 1;
1245  int isMCAsmWriter = 1;
1246}
1247
1248//===----------------------------------------------------------------------===//
1249// Target Declaration
1250//===----------------------------------------------------------------------===//
1251
1252def AArch64 : Target {
1253  let InstructionSet = AArch64InstrInfo;
1254  let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
1255  let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];
1256  let AllowRegisterRenaming = 1;
1257}
1258
1259//===----------------------------------------------------------------------===//
1260// Pfm Counters
1261//===----------------------------------------------------------------------===//
1262
1263include "AArch64PfmCounters.td"
1264