1//=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// 10//===----------------------------------------------------------------------===// 11 12//===----------------------------------------------------------------------===// 13// Target-independent interfaces which we are implementing. 14//===----------------------------------------------------------------------===// 15 16include "llvm/Target/Target.td" 17 18//===----------------------------------------------------------------------===// 19// AArch64 Subtarget features. 20// 21 22// Each SubtargetFeature which corresponds to an Arm Architecture feature should 23// be annotated with the respective FEAT_ feature name from the Architecture 24// Reference Manual. If a SubtargetFeature enables instructions from multiple 25// Arm Architecture Features, it should list all the relevant features. Not all 26// FEAT_ features have a corresponding SubtargetFeature. 27 28def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true", 29 "Enable ARMv8 FP (FEAT_FP)">; 30 31def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", 32 "Enable Advanced SIMD instructions (FEAT_AdvSIMD)", [FeatureFPARMv8]>; 33 34def FeatureSM4 : SubtargetFeature< 35 "sm4", "HasSM4", "true", 36 "Enable SM3 and SM4 support (FEAT_SM4, FEAT_SM3)", [FeatureNEON]>; 37 38def FeatureSHA2 : SubtargetFeature< 39 "sha2", "HasSHA2", "true", 40 "Enable SHA1 and SHA256 support (FEAT_SHA1, FEAT_SHA256)", [FeatureNEON]>; 41 42def FeatureSHA3 : SubtargetFeature< 43 "sha3", "HasSHA3", "true", 44 "Enable SHA512 and SHA3 support (FEAT_SHA3, FEAT_SHA512)", [FeatureNEON, FeatureSHA2]>; 45 46def FeatureAES : SubtargetFeature< 47 "aes", "HasAES", "true", 48 "Enable AES support (FEAT_AES, FEAT_PMULL)", [FeatureNEON]>; 49 50// Crypto has been split up and any combination is now valid (see the 51// crypto definitions above). Also, crypto is now context sensitive: 52// it has a different meaning for e.g. Armv8.4 than it has for Armv8.2. 53// Therefore, we rely on Clang, the user interfacing tool, to pass on the 54// appropriate crypto options. But here in the backend, crypto has very little 55// meaning anymore. We kept the Crypto definition here for backward 56// compatibility, and now imply features SHA2 and AES, which was the 57// "traditional" meaning of Crypto. 58def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", 59 "Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>; 60 61def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", 62 "Enable ARMv8 CRC-32 checksum instructions (FEAT_CRC32)">; 63 64def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true", 65 "Enable ARMv8 Reliability, Availability and Serviceability Extensions (FEAT_RAS, FEAT_RASv1p1)">; 66 67def FeatureRASv2 : SubtargetFeature<"rasv2", "HasRASv2", "true", 68 "Enable ARMv8.9-A Reliability, Availability and Serviceability Extensions (FEAT_RASv2)", 69 [FeatureRAS]>; 70 71def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true", 72 "Enable ARMv8.1 Large System Extension (LSE) atomic instructions (FEAT_LSE)">; 73 74def FeatureLSE2 : SubtargetFeature<"lse2", "HasLSE2", "true", 75 "Enable ARMv8.4 Large System Extension 2 (LSE2) atomicity rules (FEAT_LSE2)">; 76 77def FeatureOutlineAtomics : SubtargetFeature<"outline-atomics", "OutlineAtomics", "true", 78 "Enable out of line atomics to support LSE instructions">; 79 80def FeatureFMV : SubtargetFeature<"fmv", "HasFMV", "true", 81 "Enable Function Multi Versioning support.">; 82 83def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true", 84 "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions (FEAT_RDM)">; 85 86def FeaturePAN : SubtargetFeature< 87 "pan", "HasPAN", "true", 88 "Enables ARM v8.1 Privileged Access-Never extension (FEAT_PAN)">; 89 90def FeatureLOR : SubtargetFeature< 91 "lor", "HasLOR", "true", 92 "Enables ARM v8.1 Limited Ordering Regions extension (FEAT_LOR)">; 93 94def FeatureCONTEXTIDREL2 : SubtargetFeature<"CONTEXTIDREL2", "HasCONTEXTIDREL2", 95 "true", "Enable RW operand CONTEXTIDR_EL2" >; 96 97def FeatureVH : SubtargetFeature<"vh", "HasVH", "true", 98 "Enables ARM v8.1 Virtual Host extension (FEAT_VHE)", [FeatureCONTEXTIDREL2] >; 99 100// This SubtargetFeature is special. It controls only whether codegen will turn 101// `llvm.readcyclecounter()` into an access to a PMUv3 System Register. The 102// `FEAT_PMUv3*` system registers are always available for assembly/disassembly. 103def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", 104 "Enable Code Generation for ARMv8 PMUv3 Performance Monitors extension (FEAT_PMUv3)">; 105 106def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true", 107 "Full FP16 (FEAT_FP16)", [FeatureFPARMv8]>; 108 109def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true", 110 "Enable FP16 FML instructions (FEAT_FHM)", [FeatureFullFP16]>; 111 112def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true", 113 "Enable Statistical Profiling extension (FEAT_SPE)">; 114 115def FeaturePAN_RWV : SubtargetFeature< 116 "pan-rwv", "HasPAN_RWV", "true", 117 "Enable v8.2 PAN s1e1R and s1e1W Variants (FEAT_PAN2)", 118 [FeaturePAN]>; 119 120// UAO PState 121def FeaturePsUAO : SubtargetFeature< "uaops", "HasPsUAO", "true", 122 "Enable v8.2 UAO PState (FEAT_UAO)">; 123 124def FeatureCCPP : SubtargetFeature<"ccpp", "HasCCPP", 125 "true", "Enable v8.2 data Cache Clean to Point of Persistence (FEAT_DPB)" >; 126 127def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true", 128 "Enable Scalable Vector Extension (SVE) instructions (FEAT_SVE)", [FeatureFullFP16]>; 129 130// This flag is currently still labeled as Experimental, but when fully 131// implemented this should tell the compiler to use the zeroing pseudos to 132// benefit from the reverse instructions (e.g. SUB vs SUBR) if the inactive 133// lanes are known to be zero. The pseudos will then be expanded using the 134// MOVPRFX instruction to zero the inactive lanes. This feature should only be 135// enabled if MOVPRFX instructions are known to merge with the destructive 136// operations they prefix. 137// 138// This feature could similarly be extended to support cheap merging of _any_ 139// value into the inactive lanes using the MOVPRFX instruction that uses 140// merging-predication. 141def FeatureExperimentalZeroingPseudos 142 : SubtargetFeature<"use-experimental-zeroing-pseudos", 143 "UseExperimentalZeroingPseudos", "true", 144 "Hint to the compiler that the MOVPRFX instruction is " 145 "merged with destructive operations", 146 []>; 147 148def FeatureUseScalarIncVL : SubtargetFeature<"use-scalar-inc-vl", 149 "UseScalarIncVL", "true", "Prefer inc/dec over add+cnt">; 150 151def FeatureSVE2 : SubtargetFeature<"sve2", "HasSVE2", "true", 152 "Enable Scalable Vector Extension 2 (SVE2) instructions (FEAT_SVE2)", 153 [FeatureSVE, FeatureUseScalarIncVL]>; 154 155def FeatureSVE2AES : SubtargetFeature<"sve2-aes", "HasSVE2AES", "true", 156 "Enable AES SVE2 instructions (FEAT_SVE_AES, FEAT_SVE_PMULL128)", 157 [FeatureSVE2, FeatureAES]>; 158 159def FeatureSVE2SM4 : SubtargetFeature<"sve2-sm4", "HasSVE2SM4", "true", 160 "Enable SM4 SVE2 instructions (FEAT_SVE_SM4)", [FeatureSVE2, FeatureSM4]>; 161 162def FeatureSVE2SHA3 : SubtargetFeature<"sve2-sha3", "HasSVE2SHA3", "true", 163 "Enable SHA3 SVE2 instructions (FEAT_SVE_SHA3)", [FeatureSVE2, FeatureSHA3]>; 164 165def FeatureSVE2BitPerm : SubtargetFeature<"sve2-bitperm", "HasSVE2BitPerm", "true", 166 "Enable bit permutation SVE2 instructions (FEAT_SVE_BitPerm)", [FeatureSVE2]>; 167 168def FeatureSVE2p1: SubtargetFeature<"sve2p1", "HasSVE2p1", "true", 169 "Enable Scalable Vector Extension 2.1 instructions", [FeatureSVE2]>; 170 171def FeatureB16B16 : SubtargetFeature<"b16b16", "HasB16B16", "true", 172 "Enable SVE2.1 or SME2.1 non-widening BFloat16 to BFloat16 instructions (FEAT_B16B16)", []>; 173 174def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true", 175 "Has zero-cycle register moves">; 176 177def FeatureZCZeroingGP : SubtargetFeature<"zcz-gp", "HasZeroCycleZeroingGP", "true", 178 "Has zero-cycle zeroing instructions for generic registers">; 179 180// It is generally beneficial to rewrite "fmov s0, wzr" to "movi d0, #0". 181// as movi is more efficient across all cores. Newer cores can eliminate 182// fmovs early and there is no difference with movi, but this not true for 183// all implementations. 184def FeatureNoZCZeroingFP : SubtargetFeature<"no-zcz-fp", "HasZeroCycleZeroingFP", "false", 185 "Has no zero-cycle zeroing instructions for FP registers">; 186 187def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true", 188 "Has zero-cycle zeroing instructions", 189 [FeatureZCZeroingGP]>; 190 191/// ... but the floating-point version doesn't quite work in rare cases on older 192/// CPUs. 193def FeatureZCZeroingFPWorkaround : SubtargetFeature<"zcz-fp-workaround", 194 "HasZeroCycleZeroingFPWorkaround", "true", 195 "The zero-cycle floating-point zeroing instruction has a bug">; 196 197def FeatureStrictAlign : SubtargetFeature<"strict-align", 198 "RequiresStrictAlign", "true", 199 "Disallow all unaligned memory " 200 "access">; 201 202foreach i = {1-7,9-15,18,20-28,30} in 203 def FeatureReserveX#i : SubtargetFeature<"reserve-x"#i, "ReserveXRegister["#i#"]", "true", 204 "Reserve X"#i#", making it unavailable " 205 "as a GPR">; 206 207foreach i = {8-15,18} in 208 def FeatureCallSavedX#i : SubtargetFeature<"call-saved-x"#i, 209 "CustomCallSavedXRegs["#i#"]", "true", "Make X"#i#" callee saved.">; 210 211def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps", 212 "true", 213 "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">; 214 215def FeaturePredictableSelectIsExpensive : SubtargetFeature< 216 "predictable-select-expensive", "PredictableSelectIsExpensive", "true", 217 "Prefer likely predicted branches over selects">; 218 219def FeatureEnableSelectOptimize : SubtargetFeature< 220 "enable-select-opt", "EnableSelectOptimize", "true", 221 "Enable the select optimize pass for select loop heuristics">; 222 223def FeatureCustomCheapAsMoveHandling : SubtargetFeature<"custom-cheap-as-move", 224 "HasCustomCheapAsMoveHandling", "true", 225 "Use custom handling of cheap instructions">; 226 227def FeatureExynosCheapAsMoveHandling : SubtargetFeature<"exynos-cheap-as-move", 228 "HasExynosCheapAsMoveHandling", "true", 229 "Use Exynos specific handling of cheap instructions", 230 [FeatureCustomCheapAsMoveHandling]>; 231 232def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler", 233 "UsePostRAScheduler", "true", "Schedule again after register allocation">; 234 235def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store", 236 "IsMisaligned128StoreSlow", "true", "Misaligned 128 bit stores are slow">; 237 238def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128", 239 "IsPaired128Slow", "true", "Paired 128 bit loads and stores are slow">; 240 241def FeatureAscendStoreAddress : SubtargetFeature<"ascend-store-address", 242 "IsStoreAddressAscend", "true", 243 "Schedule vector stores by ascending address">; 244 245def FeatureSlowSTRQro : SubtargetFeature<"slow-strqro-store", "IsSTRQroSlow", 246 "true", "STR of Q register with register offset is slow">; 247 248def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature< 249 "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern", 250 "true", "Use alternative pattern for sextload convert to f32">; 251 252def FeatureArithmeticBccFusion : SubtargetFeature< 253 "arith-bcc-fusion", "HasArithmeticBccFusion", "true", 254 "CPU fuses arithmetic+bcc operations">; 255 256def FeatureArithmeticCbzFusion : SubtargetFeature< 257 "arith-cbz-fusion", "HasArithmeticCbzFusion", "true", 258 "CPU fuses arithmetic + cbz/cbnz operations">; 259 260def FeatureCmpBccFusion : SubtargetFeature< 261 "cmp-bcc-fusion", "HasCmpBccFusion", "true", 262 "CPU fuses cmp+bcc operations">; 263 264def FeatureFuseAddress : SubtargetFeature< 265 "fuse-address", "HasFuseAddress", "true", 266 "CPU fuses address generation and memory operations">; 267 268def FeatureFuseAES : SubtargetFeature< 269 "fuse-aes", "HasFuseAES", "true", 270 "CPU fuses AES crypto operations">; 271 272def FeatureFuseArithmeticLogic : SubtargetFeature< 273 "fuse-arith-logic", "HasFuseArithmeticLogic", "true", 274 "CPU fuses arithmetic and logic operations">; 275 276def FeatureFuseCCSelect : SubtargetFeature< 277 "fuse-csel", "HasFuseCCSelect", "true", 278 "CPU fuses conditional select operations">; 279 280def FeatureFuseCryptoEOR : SubtargetFeature< 281 "fuse-crypto-eor", "HasFuseCryptoEOR", "true", 282 "CPU fuses AES/PMULL and EOR operations">; 283 284def FeatureFuseAdrpAdd : SubtargetFeature< 285 "fuse-adrp-add", "HasFuseAdrpAdd", "true", 286 "CPU fuses adrp+add operations">; 287 288def FeatureFuseLiterals : SubtargetFeature< 289 "fuse-literals", "HasFuseLiterals", "true", 290 "CPU fuses literal generation operations">; 291 292def FeatureFuseAddSub2RegAndConstOne : SubtargetFeature< 293 "fuse-addsub-2reg-const1", "HasFuseAddSub2RegAndConstOne", "true", 294 "CPU fuses (a + b + 1) and (a - b - 1)">; 295 296def FeatureDisableLatencySchedHeuristic : SubtargetFeature< 297 "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true", 298 "Disable latency scheduling heuristic">; 299 300def FeatureForce32BitJumpTables 301 : SubtargetFeature<"force-32bit-jump-tables", "Force32BitJumpTables", "true", 302 "Force jump table entries to be 32-bits wide except at MinSize">; 303 304def FeatureRCPC : SubtargetFeature<"rcpc", "HasRCPC", "true", 305 "Enable support for RCPC extension (FEAT_LRCPC)">; 306 307def FeatureUseRSqrt : SubtargetFeature< 308 "use-reciprocal-square-root", "UseRSqrt", "true", 309 "Use the reciprocal square root approximation">; 310 311def FeatureDotProd : SubtargetFeature< 312 "dotprod", "HasDotProd", "true", 313 "Enable dot product support (FEAT_DotProd)">; 314 315def FeaturePAuth : SubtargetFeature< 316 "pauth", "HasPAuth", "true", 317 "Enable v8.3-A Pointer Authentication extension (FEAT_PAuth)">; 318 319def FeatureJS : SubtargetFeature< 320 "jsconv", "HasJS", "true", 321 "Enable v8.3-A JavaScript FP conversion instructions (FEAT_JSCVT)", 322 [FeatureFPARMv8]>; 323 324def FeatureCCIDX : SubtargetFeature< 325 "ccidx", "HasCCIDX", "true", 326 "Enable v8.3-A Extend of the CCSIDR number of sets (FEAT_CCIDX)">; 327 328def FeatureComplxNum : SubtargetFeature< 329 "complxnum", "HasComplxNum", "true", 330 "Enable v8.3-A Floating-point complex number support (FEAT_FCMA)", 331 [FeatureNEON]>; 332 333def FeatureNV : SubtargetFeature< 334 "nv", "HasNV", "true", 335 "Enable v8.4-A Nested Virtualization Enchancement (FEAT_NV, FEAT_NV2)">; 336 337def FeatureMPAM : SubtargetFeature< 338 "mpam", "HasMPAM", "true", 339 "Enable v8.4-A Memory system Partitioning and Monitoring extension (FEAT_MPAM)">; 340 341def FeatureDIT : SubtargetFeature< 342 "dit", "HasDIT", "true", 343 "Enable v8.4-A Data Independent Timing instructions (FEAT_DIT)">; 344 345def FeatureTRACEV8_4 : SubtargetFeature< 346 "tracev8.4", "HasTRACEV8_4", "true", 347 "Enable v8.4-A Trace extension (FEAT_TRF)">; 348 349def FeatureAM : SubtargetFeature< 350 "am", "HasAM", "true", 351 "Enable v8.4-A Activity Monitors extension (FEAT_AMUv1)">; 352 353def FeatureAMVS : SubtargetFeature< 354 "amvs", "HasAMVS", "true", 355 "Enable v8.6-A Activity Monitors Virtualization support (FEAT_AMUv1p1)", 356 [FeatureAM]>; 357 358def FeatureSEL2 : SubtargetFeature< 359 "sel2", "HasSEL2", "true", 360 "Enable v8.4-A Secure Exception Level 2 extension (FEAT_SEL2)">; 361 362def FeatureTLB_RMI : SubtargetFeature< 363 "tlb-rmi", "HasTLB_RMI", "true", 364 "Enable v8.4-A TLB Range and Maintenance Instructions (FEAT_TLBIOS, FEAT_TLBIRANGE)">; 365 366def FeatureFlagM : SubtargetFeature< 367 "flagm", "HasFlagM", "true", 368 "Enable v8.4-A Flag Manipulation Instructions (FEAT_FlagM)">; 369 370// 8.4 RCPC enchancements: LDAPR & STLR instructions with Immediate Offset 371def FeatureRCPC_IMMO : SubtargetFeature<"rcpc-immo", "HasRCPC_IMMO", "true", 372 "Enable v8.4-A RCPC instructions with Immediate Offsets (FEAT_LRCPC2)", 373 [FeatureRCPC]>; 374 375def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates", 376 "NegativeImmediates", "false", 377 "Convert immediates and instructions " 378 "to their negated or complemented " 379 "equivalent when the immediate does " 380 "not fit in the encoding.">; 381 382def FeatureLSLFast : SubtargetFeature< 383 "lsl-fast", "HasLSLFast", "true", 384 "CPU has a fastpath logical shift of up to 3 places">; 385 386def FeatureAggressiveFMA : 387 SubtargetFeature<"aggressive-fma", 388 "HasAggressiveFMA", 389 "true", 390 "Enable Aggressive FMA for floating-point.">; 391 392def FeatureAltFPCmp : SubtargetFeature<"altnzcv", "HasAlternativeNZCV", "true", 393 "Enable alternative NZCV format for floating point comparisons (FEAT_FlagM2)">; 394 395def FeatureFRInt3264 : SubtargetFeature<"fptoint", "HasFRInt3264", "true", 396 "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to " 397 "an integer (in FP format) forcing it to fit into a 32- or 64-bit int (FEAT_FRINTTS)" >; 398 399def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict", 400 "true", "Enable architectural speculation restriction (FEAT_CSV2_2)">; 401 402def FeatureSB : SubtargetFeature<"sb", "HasSB", 403 "true", "Enable v8.5 Speculation Barrier (FEAT_SB)" >; 404 405def FeatureSSBS : SubtargetFeature<"ssbs", "HasSSBS", 406 "true", "Enable Speculative Store Bypass Safe bit (FEAT_SSBS, FEAT_SSBS2)" >; 407 408def FeaturePredRes : SubtargetFeature<"predres", "HasPredRes", "true", 409 "Enable v8.5a execution and data prediction invalidation instructions (FEAT_SPECRES)" >; 410 411def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP", 412 "true", "Enable v8.5 Cache Clean to Point of Deep Persistence (FEAT_DPB2)" >; 413 414def FeatureBranchTargetId : SubtargetFeature<"bti", "HasBTI", 415 "true", "Enable Branch Target Identification (FEAT_BTI)" >; 416 417def FeatureRandGen : SubtargetFeature<"rand", "HasRandGen", 418 "true", "Enable Random Number generation instructions (FEAT_RNG)" >; 419 420def FeatureMTE : SubtargetFeature<"mte", "HasMTE", 421 "true", "Enable Memory Tagging Extension (FEAT_MTE, FEAT_MTE2)" >; 422 423def FeatureTRBE : SubtargetFeature<"trbe", "HasTRBE", 424 "true", "Enable Trace Buffer Extension (FEAT_TRBE)">; 425 426def FeatureETE : SubtargetFeature<"ete", "HasETE", 427 "true", "Enable Embedded Trace Extension (FEAT_ETE)", 428 [FeatureTRBE]>; 429 430def FeatureTME : SubtargetFeature<"tme", "HasTME", 431 "true", "Enable Transactional Memory Extension (FEAT_TME)" >; 432 433def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals", 434 "AllowTaggedGlobals", 435 "true", "Use an instruction sequence for taking the address of a global " 436 "that allows a memory tag in the upper address bits">; 437 438def FeatureBF16 : SubtargetFeature<"bf16", "HasBF16", 439 "true", "Enable BFloat16 Extension (FEAT_BF16)" >; 440 441def FeatureMatMulInt8 : SubtargetFeature<"i8mm", "HasMatMulInt8", 442 "true", "Enable Matrix Multiply Int8 Extension (FEAT_I8MM)">; 443 444def FeatureMatMulFP32 : SubtargetFeature<"f32mm", "HasMatMulFP32", 445 "true", "Enable Matrix Multiply FP32 Extension (FEAT_F32MM)", [FeatureSVE]>; 446 447def FeatureMatMulFP64 : SubtargetFeature<"f64mm", "HasMatMulFP64", 448 "true", "Enable Matrix Multiply FP64 Extension (FEAT_F64MM)", [FeatureSVE]>; 449 450def FeatureXS : SubtargetFeature<"xs", "HasXS", 451 "true", "Enable Armv8.7-A limited-TLB-maintenance instruction (FEAT_XS)">; 452 453def FeatureWFxT : SubtargetFeature<"wfxt", "HasWFxT", 454 "true", "Enable Armv8.7-A WFET and WFIT instruction (FEAT_WFxT)">; 455 456def FeatureHCX : SubtargetFeature< 457 "hcx", "HasHCX", "true", "Enable Armv8.7-A HCRX_EL2 system register (FEAT_HCX)">; 458 459def FeatureLS64 : SubtargetFeature<"ls64", "HasLS64", 460 "true", "Enable Armv8.7-A LD64B/ST64B Accelerator Extension (FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA)">; 461 462def FeatureHBC : SubtargetFeature<"hbc", "HasHBC", 463 "true", "Enable Armv8.8-A Hinted Conditional Branches Extension (FEAT_HBC)">; 464 465def FeatureMOPS : SubtargetFeature<"mops", "HasMOPS", 466 "true", "Enable Armv8.8-A memcpy and memset acceleration instructions (FEAT_MOPS)">; 467 468def FeatureNMI : SubtargetFeature<"nmi", "HasNMI", 469 "true", "Enable Armv8.8-A Non-maskable Interrupts (FEAT_NMI, FEAT_GICv3_NMI)">; 470 471def FeatureBRBE : SubtargetFeature<"brbe", "HasBRBE", 472 "true", "Enable Branch Record Buffer Extension (FEAT_BRBE)">; 473 474def FeatureSPE_EEF : SubtargetFeature<"spe-eef", "HasSPE_EEF", 475 "true", "Enable extra register in the Statistical Profiling Extension (FEAT_SPEv1p2)">; 476 477def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps", 478 "true", "Enable fine grained virtualization traps extension (FEAT_FGT)">; 479 480def FeatureEnhancedCounterVirtualization : 481 SubtargetFeature<"ecv", "HasEnhancedCounterVirtualization", 482 "true", "Enable enhanced counter virtualization extension (FEAT_ECV)">; 483 484def FeatureRME : SubtargetFeature<"rme", "HasRME", 485 "true", "Enable Realm Management Extension (FEAT_RME)">; 486 487def FeatureSME : SubtargetFeature<"sme", "HasSME", "true", 488 "Enable Scalable Matrix Extension (SME) (FEAT_SME)", [FeatureBF16, FeatureUseScalarIncVL]>; 489 490def FeatureSMEF64F64 : SubtargetFeature<"sme-f64f64", "HasSMEF64F64", "true", 491 "Enable Scalable Matrix Extension (SME) F64F64 instructions (FEAT_SME_F64F64)", [FeatureSME]>; 492 493def FeatureSMEI16I64 : SubtargetFeature<"sme-i16i64", "HasSMEI16I64", "true", 494 "Enable Scalable Matrix Extension (SME) I16I64 instructions (FEAT_SME_I16I64)", [FeatureSME]>; 495 496def FeatureSMEF16F16 : SubtargetFeature<"sme-f16f16", "HasSMEF16F16", "true", 497 "Enable SME2.1 non-widening Float16 instructions (FEAT_SME_F16F16)", []>; 498 499def FeatureSME2 : SubtargetFeature<"sme2", "HasSME2", "true", 500 "Enable Scalable Matrix Extension 2 (SME2) instructions", [FeatureSME]>; 501 502def FeatureSME2p1 : SubtargetFeature<"sme2p1", "HasSME2p1", "true", 503 "Enable Scalable Matrix Extension 2.1 (FEAT_SME2p1) instructions", [FeatureSME2]>; 504 505def FeatureAppleA7SysReg : SubtargetFeature<"apple-a7-sysreg", "HasAppleA7SysReg", "true", 506 "Apple A7 (the CPU formerly known as Cyclone)">; 507 508def FeatureEL2VMSA : SubtargetFeature<"el2vmsa", "HasEL2VMSA", "true", 509 "Enable Exception Level 2 Virtual Memory System Architecture">; 510 511def FeatureEL3 : SubtargetFeature<"el3", "HasEL3", "true", 512 "Enable Exception Level 3">; 513 514def FeatureCSSC : SubtargetFeature<"cssc", "HasCSSC", "true", 515 "Enable Common Short Sequence Compression (CSSC) instructions (FEAT_CSSC)">; 516 517def FeatureFixCortexA53_835769 : SubtargetFeature<"fix-cortex-a53-835769", 518 "FixCortexA53_835769", "true", "Mitigate Cortex-A53 Erratum 835769">; 519 520def FeatureNoBTIAtReturnTwice : SubtargetFeature<"no-bti-at-return-twice", 521 "NoBTIAtReturnTwice", "true", 522 "Don't place a BTI instruction " 523 "after a return-twice">; 524 525def FeatureCHK : SubtargetFeature<"chk", "HasCHK", 526 "true", "Enable Armv8.0-A Check Feature Status Extension (FEAT_CHK)">; 527 528def FeatureGCS : SubtargetFeature<"gcs", "HasGCS", 529 "true", "Enable Armv9.4-A Guarded Call Stack Extension", [FeatureCHK]>; 530 531def FeatureCLRBHB : SubtargetFeature<"clrbhb", "HasCLRBHB", 532 "true", "Enable Clear BHB instruction (FEAT_CLRBHB)">; 533 534def FeaturePRFM_SLC : SubtargetFeature<"prfm-slc-target", "HasPRFM_SLC", 535 "true", "Enable SLC target for PRFM instruction">; 536 537def FeatureSPECRES2 : SubtargetFeature<"specres2", "HasSPECRES2", 538 "true", "Enable Speculation Restriction Instruction (FEAT_SPECRES2)", 539 [FeaturePredRes]>; 540 541def FeatureMEC : SubtargetFeature<"mec", "HasMEC", 542 "true", "Enable Memory Encryption Contexts Extension", [FeatureRME]>; 543 544def FeatureITE : SubtargetFeature<"ite", "HasITE", 545 "true", "Enable Armv9.4-A Instrumentation Extension FEAT_ITE", [FeatureETE, 546 FeatureTRBE]>; 547 548def FeatureRCPC3 : SubtargetFeature<"rcpc3", "HasRCPC3", 549 "true", "Enable Armv8.9-A RCPC instructions for A64 and Advanced SIMD and floating-point instruction set (FEAT_LRCPC3)", 550 [FeatureRCPC_IMMO]>; 551 552def FeatureTHE : SubtargetFeature<"the", "HasTHE", 553 "true", "Enable Armv8.9-A Translation Hardening Extension (FEAT_THE)">; 554 555def FeatureLSE128 : SubtargetFeature<"lse128", "HasLSE128", 556 "true", "Enable Armv9.4-A 128-bit Atomic Instructions (FEAT_LSE128)", 557 [FeatureLSE]>; 558 559// FEAT_D128, FEAT_LVA3, FEAT_SYSREG128, and FEAT_SYSINSTR128 are mutually implicit. 560// Therefore group them all under a single feature flag, d128: 561def FeatureD128 : SubtargetFeature<"d128", "HasD128", 562 "true", "Enable Armv9.4-A 128-bit Page Table Descriptors, System Registers " 563 "and Instructions (FEAT_D128, FEAT_LVA3, FEAT_SYSREG128, FEAT_SYSINSTR128)", 564 [FeatureLSE128]>; 565 566//===----------------------------------------------------------------------===// 567// Architectures. 568// 569def HasV8_0aOps : SubtargetFeature<"v8a", "HasV8_0aOps", "true", 570 "Support ARM v8.0a instructions", [FeatureEL2VMSA, FeatureEL3]>; 571 572def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", 573 "Support ARM v8.1a instructions", [HasV8_0aOps, FeatureCRC, FeatureLSE, 574 FeatureRDM, FeaturePAN, FeatureLOR, FeatureVH]>; 575 576def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true", 577 "Support ARM v8.2a instructions", [HasV8_1aOps, FeaturePsUAO, 578 FeaturePAN_RWV, FeatureRAS, FeatureCCPP]>; 579 580def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true", 581 "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC, FeaturePAuth, 582 FeatureJS, FeatureCCIDX, FeatureComplxNum]>; 583 584def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", 585 "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd, 586 FeatureNV, FeatureMPAM, FeatureDIT, 587 FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeatureTLB_RMI, 588 FeatureFlagM, FeatureRCPC_IMMO, FeatureLSE2]>; 589 590def HasV8_5aOps : SubtargetFeature< 591 "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions", 592 [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict, 593 FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist, 594 FeatureBranchTargetId]>; 595 596def HasV8_6aOps : SubtargetFeature< 597 "v8.6a", "HasV8_6aOps", "true", "Support ARM v8.6a instructions", 598 [HasV8_5aOps, FeatureAMVS, FeatureBF16, FeatureFineGrainedTraps, 599 FeatureEnhancedCounterVirtualization, FeatureMatMulInt8]>; 600 601def HasV8_7aOps : SubtargetFeature< 602 "v8.7a", "HasV8_7aOps", "true", "Support ARM v8.7a instructions", 603 [HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX]>; 604 605def HasV8_8aOps : SubtargetFeature< 606 "v8.8a", "HasV8_8aOps", "true", "Support ARM v8.8a instructions", 607 [HasV8_7aOps, FeatureHBC, FeatureMOPS, FeatureNMI]>; 608 609def HasV8_9aOps : SubtargetFeature< 610 "v8.9a", "HasV8_9aOps", "true", "Support ARM v8.9a instructions", 611 [HasV8_8aOps, FeatureCLRBHB, FeaturePRFM_SLC, FeatureSPECRES2, 612 FeatureCSSC, FeatureRASv2, FeatureCHK]>; 613 614def HasV9_0aOps : SubtargetFeature< 615 "v9a", "HasV9_0aOps", "true", "Support ARM v9a instructions", 616 [HasV8_5aOps, FeatureMEC, FeatureSVE2]>; 617 618def HasV9_1aOps : SubtargetFeature< 619 "v9.1a", "HasV9_1aOps", "true", "Support ARM v9.1a instructions", 620 [HasV8_6aOps, HasV9_0aOps]>; 621 622def HasV9_2aOps : SubtargetFeature< 623 "v9.2a", "HasV9_2aOps", "true", "Support ARM v9.2a instructions", 624 [HasV8_7aOps, HasV9_1aOps]>; 625 626def HasV9_3aOps : SubtargetFeature< 627 "v9.3a", "HasV9_3aOps", "true", "Support ARM v9.3a instructions", 628 [HasV8_8aOps, HasV9_2aOps]>; 629 630def HasV9_4aOps : SubtargetFeature< 631 "v9.4a", "HasV9_4aOps", "true", "Support ARM v9.4a instructions", 632 [HasV8_9aOps, HasV9_3aOps]>; 633 634def HasV8_0rOps : SubtargetFeature< 635 "v8r", "HasV8_0rOps", "true", "Support ARM v8r instructions", 636 [//v8.1 637 FeatureCRC, FeaturePAN, FeatureRDM, FeatureLSE, FeatureCONTEXTIDREL2, 638 //v8.2 639 FeatureRAS, FeaturePsUAO, FeatureCCPP, FeaturePAN_RWV, 640 //v8.3 641 FeatureComplxNum, FeatureCCIDX, FeatureJS, 642 FeaturePAuth, FeatureRCPC, 643 //v8.4 644 FeatureDotProd, FeatureTRACEV8_4, FeatureTLB_RMI, 645 FeatureFlagM, FeatureDIT, FeatureSEL2, FeatureRCPC_IMMO, 646 // Not mandatory in v8.0-R, but included here on the grounds that it 647 // only enables names of system registers 648 FeatureSpecRestrict 649 ]>; 650 651// Only intended to be used by disassemblers. 652def FeatureAll 653 : SubtargetFeature<"all", "IsAll", "true", "Enable all instructions", []>; 654 655class AssemblerPredicateWithAll<dag cond, string name=""> 656 : AssemblerPredicate<(any_of FeatureAll, cond), name>; 657 658//===----------------------------------------------------------------------===// 659// Register File Description 660//===----------------------------------------------------------------------===// 661 662include "AArch64RegisterInfo.td" 663include "AArch64RegisterBanks.td" 664include "AArch64CallingConvention.td" 665 666//===----------------------------------------------------------------------===// 667// Instruction Descriptions 668//===----------------------------------------------------------------------===// 669 670include "AArch64Schedule.td" 671include "AArch64InstrInfo.td" 672include "AArch64SchedPredicates.td" 673include "AArch64SchedPredExynos.td" 674include "AArch64SchedPredNeoverse.td" 675include "AArch64Combine.td" 676 677def AArch64InstrInfo : InstrInfo; 678 679//===----------------------------------------------------------------------===// 680// Named operands for MRS/MSR/TLBI/... 681//===----------------------------------------------------------------------===// 682 683include "AArch64SystemOperands.td" 684 685//===----------------------------------------------------------------------===// 686// Access to privileged registers 687//===----------------------------------------------------------------------===// 688 689foreach i = 1-3 in 690def FeatureUseEL#i#ForTP : SubtargetFeature<"tpidr-el"#i, "UseEL"#i#"ForTP", 691 "true", "Permit use of TPIDR_EL"#i#" for the TLS base">; 692def FeatureUseROEL0ForTP : SubtargetFeature<"tpidrro-el0", "UseROEL0ForTP", 693 "true", "Permit use of TPIDRRO_EL0 for the TLS base">; 694 695//===----------------------------------------------------------------------===// 696// Control codegen mitigation against Straight Line Speculation vulnerability. 697//===----------------------------------------------------------------------===// 698 699def FeatureHardenSlsRetBr : SubtargetFeature<"harden-sls-retbr", 700 "HardenSlsRetBr", "true", 701 "Harden against straight line speculation across RET and BR instructions">; 702def FeatureHardenSlsBlr : SubtargetFeature<"harden-sls-blr", 703 "HardenSlsBlr", "true", 704 "Harden against straight line speculation across BLR instructions">; 705def FeatureHardenSlsNoComdat : SubtargetFeature<"harden-sls-nocomdat", 706 "HardenSlsNoComdat", "true", 707 "Generate thunk code for SLS mitigation in the normal text section">; 708 709//===----------------------------------------------------------------------===// 710// AArch64 Processors supported. 711// 712 713//===----------------------------------------------------------------------===// 714// Unsupported features to disable for scheduling models 715//===----------------------------------------------------------------------===// 716 717class AArch64Unsupported { list<Predicate> F; } 718 719let F = [HasSVE2p1, HasSVE2p1_or_HasSME2, HasSVE2p1_or_HasSME2p1] in 720def SVE2p1Unsupported : AArch64Unsupported; 721 722def SVE2Unsupported : AArch64Unsupported { 723 let F = !listconcat([HasSVE2, HasSVE2orSME, 724 HasSVE2AES, HasSVE2SHA3, HasSVE2SM4, HasSVE2BitPerm], 725 SVE2p1Unsupported.F); 726} 727 728def SVEUnsupported : AArch64Unsupported { 729 let F = !listconcat([HasSVE, HasSVEorSME], 730 SVE2Unsupported.F); 731} 732 733let F = [HasSME2p1, HasSVE2p1_or_HasSME2p1] in 734def SME2p1Unsupported : AArch64Unsupported; 735 736def SME2Unsupported : AArch64Unsupported { 737 let F = !listconcat([HasSME2, HasSVE2p1_or_HasSME2], 738 SME2p1Unsupported.F); 739} 740 741def SMEUnsupported : AArch64Unsupported { 742 let F = !listconcat([HasSME, HasSMEI16I64, HasSMEF16F16, HasSMEF64F64], 743 SME2Unsupported.F); 744} 745 746let F = [HasPAuth] in 747def PAUnsupported : AArch64Unsupported; 748 749include "AArch64SchedA53.td" 750include "AArch64SchedA55.td" 751include "AArch64SchedA510.td" 752include "AArch64SchedA57.td" 753include "AArch64SchedCyclone.td" 754include "AArch64SchedFalkor.td" 755include "AArch64SchedKryo.td" 756include "AArch64SchedExynosM3.td" 757include "AArch64SchedExynosM4.td" 758include "AArch64SchedExynosM5.td" 759include "AArch64SchedThunderX.td" 760include "AArch64SchedThunderX2T99.td" 761include "AArch64SchedA64FX.td" 762include "AArch64SchedThunderX3T110.td" 763include "AArch64SchedTSV110.td" 764include "AArch64SchedAmpere1.td" 765include "AArch64SchedNeoverseN1.td" 766include "AArch64SchedNeoverseN2.td" 767include "AArch64SchedNeoverseV1.td" 768include "AArch64SchedNeoverseV2.td" 769 770def TuneA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35", 771 "Cortex-A35 ARM processors">; 772 773def TuneA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", 774 "Cortex-A53 ARM processors", [ 775 FeatureFuseAES, 776 FeatureFuseAdrpAdd, 777 FeatureBalanceFPOps, 778 FeatureCustomCheapAsMoveHandling, 779 FeaturePostRAScheduler]>; 780 781def TuneA55 : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55", 782 "Cortex-A55 ARM processors", [ 783 FeatureFuseAES, 784 FeatureFuseAdrpAdd, 785 FeaturePostRAScheduler, 786 FeatureFuseAddress]>; 787 788def TuneA510 : SubtargetFeature<"a510", "ARMProcFamily", "CortexA510", 789 "Cortex-A510 ARM processors", [ 790 FeatureFuseAES, 791 FeatureFuseAdrpAdd, 792 FeaturePostRAScheduler 793 ]>; 794 795def TuneA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", 796 "Cortex-A57 ARM processors", [ 797 FeatureFuseAES, 798 FeatureBalanceFPOps, 799 FeatureCustomCheapAsMoveHandling, 800 FeatureFuseAdrpAdd, 801 FeatureFuseLiterals, 802 FeaturePostRAScheduler, 803 FeatureEnableSelectOptimize, 804 FeaturePredictableSelectIsExpensive]>; 805 806def TuneA65 : SubtargetFeature<"a65", "ARMProcFamily", "CortexA65", 807 "Cortex-A65 ARM processors", [ 808 FeatureFuseAES, 809 FeatureFuseAddress, 810 FeatureFuseAdrpAdd, 811 FeatureFuseLiterals, 812 FeatureEnableSelectOptimize, 813 FeaturePredictableSelectIsExpensive]>; 814 815def TuneA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72", 816 "Cortex-A72 ARM processors", [ 817 FeatureFuseAES, 818 FeatureFuseAdrpAdd, 819 FeatureFuseLiterals, 820 FeatureEnableSelectOptimize, 821 FeaturePredictableSelectIsExpensive]>; 822 823def TuneA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73", 824 "Cortex-A73 ARM processors", [ 825 FeatureFuseAES, 826 FeatureFuseAdrpAdd, 827 FeatureEnableSelectOptimize, 828 FeaturePredictableSelectIsExpensive]>; 829 830def TuneA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75", 831 "Cortex-A75 ARM processors", [ 832 FeatureFuseAES, 833 FeatureFuseAdrpAdd, 834 FeatureEnableSelectOptimize, 835 FeaturePredictableSelectIsExpensive]>; 836 837def TuneA76 : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76", 838 "Cortex-A76 ARM processors", [ 839 FeatureFuseAES, 840 FeatureFuseAdrpAdd, 841 FeatureLSLFast, 842 FeatureEnableSelectOptimize, 843 FeaturePredictableSelectIsExpensive]>; 844 845def TuneA77 : SubtargetFeature<"a77", "ARMProcFamily", "CortexA77", 846 "Cortex-A77 ARM processors", [ 847 FeatureCmpBccFusion, 848 FeatureFuseAES, 849 FeatureFuseAdrpAdd, 850 FeatureLSLFast, 851 FeatureEnableSelectOptimize, 852 FeaturePredictableSelectIsExpensive]>; 853 854def TuneA78 : SubtargetFeature<"a78", "ARMProcFamily", "CortexA78", 855 "Cortex-A78 ARM processors", [ 856 FeatureCmpBccFusion, 857 FeatureFuseAES, 858 FeatureFuseAdrpAdd, 859 FeatureLSLFast, 860 FeaturePostRAScheduler, 861 FeatureEnableSelectOptimize, 862 FeaturePredictableSelectIsExpensive]>; 863 864def TuneA78C : SubtargetFeature<"a78c", "ARMProcFamily", 865 "CortexA78C", 866 "Cortex-A78C ARM processors", [ 867 FeatureCmpBccFusion, 868 FeatureFuseAES, 869 FeatureFuseAdrpAdd, 870 FeatureLSLFast, 871 FeaturePostRAScheduler, 872 FeatureEnableSelectOptimize, 873 FeaturePredictableSelectIsExpensive]>; 874 875def TuneA710 : SubtargetFeature<"a710", "ARMProcFamily", "CortexA710", 876 "Cortex-A710 ARM processors", [ 877 FeatureCmpBccFusion, 878 FeatureFuseAES, 879 FeatureFuseAdrpAdd, 880 FeatureLSLFast, 881 FeaturePostRAScheduler, 882 FeatureEnableSelectOptimize, 883 FeaturePredictableSelectIsExpensive]>; 884 885def TuneA715 : SubtargetFeature<"a715", "ARMProcFamily", "CortexA715", 886 "Cortex-A715 ARM processors", [ 887 FeatureFuseAES, 888 FeaturePostRAScheduler, 889 FeatureCmpBccFusion, 890 FeatureLSLFast, 891 FeatureFuseAdrpAdd, 892 FeatureEnableSelectOptimize, 893 FeaturePredictableSelectIsExpensive]>; 894 895def TuneR82 : SubtargetFeature<"cortex-r82", "ARMProcFamily", 896 "CortexR82", 897 "Cortex-R82 ARM processors", [ 898 FeaturePostRAScheduler]>; 899 900def TuneX1 : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1", 901 "Cortex-X1 ARM processors", [ 902 FeatureCmpBccFusion, 903 FeatureFuseAES, 904 FeatureFuseAdrpAdd, 905 FeatureLSLFast, 906 FeaturePostRAScheduler, 907 FeatureEnableSelectOptimize, 908 FeaturePredictableSelectIsExpensive]>; 909 910def TuneX2 : SubtargetFeature<"cortex-x2", "ARMProcFamily", "CortexX2", 911 "Cortex-X2 ARM processors", [ 912 FeatureCmpBccFusion, 913 FeatureFuseAES, 914 FeatureFuseAdrpAdd, 915 FeatureLSLFast, 916 FeaturePostRAScheduler, 917 FeatureEnableSelectOptimize, 918 FeaturePredictableSelectIsExpensive]>; 919 920def TuneX3 : SubtargetFeature<"cortex-x3", "ARMProcFamily", "CortexX3", 921 "Cortex-X3 ARM processors", [ 922 FeatureLSLFast, 923 FeatureFuseAdrpAdd, 924 FeatureFuseAES, 925 FeaturePostRAScheduler, 926 FeatureEnableSelectOptimize, 927 FeaturePredictableSelectIsExpensive]>; 928 929def TuneA64FX : SubtargetFeature<"a64fx", "ARMProcFamily", "A64FX", 930 "Fujitsu A64FX processors", [ 931 FeaturePostRAScheduler, 932 FeatureAggressiveFMA, 933 FeatureArithmeticBccFusion, 934 FeaturePredictableSelectIsExpensive 935 ]>; 936 937def TuneCarmel : SubtargetFeature<"carmel", "ARMProcFamily", "Carmel", 938 "Nvidia Carmel processors">; 939 940// Note that cyclone does not fuse AES instructions, but newer apple chips do 941// perform the fusion and cyclone is used by default when targetting apple OSes. 942def TuneAppleA7 : SubtargetFeature<"apple-a7", "ARMProcFamily", "AppleA7", 943 "Apple A7 (the CPU formerly known as Cyclone)", [ 944 FeatureAlternateSExtLoadCVTF32Pattern, 945 FeatureArithmeticBccFusion, 946 FeatureArithmeticCbzFusion, 947 FeatureDisableLatencySchedHeuristic, 948 FeatureFuseAES, FeatureFuseCryptoEOR, 949 FeatureZCRegMove, 950 FeatureZCZeroing, 951 FeatureZCZeroingFPWorkaround] 952 >; 953 954def TuneAppleA10 : SubtargetFeature<"apple-a10", "ARMProcFamily", "AppleA10", 955 "Apple A10", [ 956 FeatureAlternateSExtLoadCVTF32Pattern, 957 FeatureArithmeticBccFusion, 958 FeatureArithmeticCbzFusion, 959 FeatureDisableLatencySchedHeuristic, 960 FeatureFuseAES, 961 FeatureFuseCryptoEOR, 962 FeatureZCRegMove, 963 FeatureZCZeroing] 964 >; 965 966def TuneAppleA11 : SubtargetFeature<"apple-a11", "ARMProcFamily", "AppleA11", 967 "Apple A11", [ 968 FeatureAlternateSExtLoadCVTF32Pattern, 969 FeatureArithmeticBccFusion, 970 FeatureArithmeticCbzFusion, 971 FeatureDisableLatencySchedHeuristic, 972 FeatureFuseAES, 973 FeatureFuseCryptoEOR, 974 FeatureZCRegMove, 975 FeatureZCZeroing] 976 >; 977 978def TuneAppleA12 : SubtargetFeature<"apple-a12", "ARMProcFamily", "AppleA12", 979 "Apple A12", [ 980 FeatureAlternateSExtLoadCVTF32Pattern, 981 FeatureArithmeticBccFusion, 982 FeatureArithmeticCbzFusion, 983 FeatureDisableLatencySchedHeuristic, 984 FeatureFuseAES, 985 FeatureFuseCryptoEOR, 986 FeatureZCRegMove, 987 FeatureZCZeroing] 988 >; 989 990def TuneAppleA13 : SubtargetFeature<"apple-a13", "ARMProcFamily", "AppleA13", 991 "Apple A13", [ 992 FeatureAlternateSExtLoadCVTF32Pattern, 993 FeatureArithmeticBccFusion, 994 FeatureArithmeticCbzFusion, 995 FeatureDisableLatencySchedHeuristic, 996 FeatureFuseAES, 997 FeatureFuseCryptoEOR, 998 FeatureZCRegMove, 999 FeatureZCZeroing] 1000 >; 1001 1002def TuneAppleA14 : SubtargetFeature<"apple-a14", "ARMProcFamily", "AppleA14", 1003 "Apple A14", [ 1004 FeatureAggressiveFMA, 1005 FeatureAlternateSExtLoadCVTF32Pattern, 1006 FeatureArithmeticBccFusion, 1007 FeatureArithmeticCbzFusion, 1008 FeatureDisableLatencySchedHeuristic, 1009 FeatureFuseAddress, 1010 FeatureFuseAES, 1011 FeatureFuseArithmeticLogic, 1012 FeatureFuseCCSelect, 1013 FeatureFuseCryptoEOR, 1014 FeatureFuseAdrpAdd, 1015 FeatureFuseLiterals, 1016 FeatureZCRegMove, 1017 FeatureZCZeroing]>; 1018 1019def TuneAppleA15 : SubtargetFeature<"apple-a15", "ARMProcFamily", "AppleA15", 1020 "Apple A15", [ 1021 FeatureAlternateSExtLoadCVTF32Pattern, 1022 FeatureArithmeticBccFusion, 1023 FeatureArithmeticCbzFusion, 1024 FeatureDisableLatencySchedHeuristic, 1025 FeatureFuseAddress, 1026 FeatureFuseAES, 1027 FeatureFuseArithmeticLogic, 1028 FeatureFuseCCSelect, 1029 FeatureFuseCryptoEOR, 1030 FeatureFuseLiterals, 1031 FeatureZCRegMove, 1032 FeatureZCZeroing 1033 ]>; 1034 1035def TuneAppleA16 : SubtargetFeature<"apple-a16", "ARMProcFamily", "AppleA16", 1036 "Apple A16", [ 1037 FeatureAlternateSExtLoadCVTF32Pattern, 1038 FeatureArithmeticBccFusion, 1039 FeatureArithmeticCbzFusion, 1040 FeatureDisableLatencySchedHeuristic, 1041 FeatureFuseAddress, 1042 FeatureFuseAES, 1043 FeatureFuseArithmeticLogic, 1044 FeatureFuseCCSelect, 1045 FeatureFuseCryptoEOR, 1046 FeatureFuseLiterals, 1047 FeatureZCRegMove, 1048 FeatureZCZeroing 1049 ]>; 1050 1051def TuneExynosM3 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3", 1052 "Samsung Exynos-M3 processors", 1053 [FeatureExynosCheapAsMoveHandling, 1054 FeatureForce32BitJumpTables, 1055 FeatureFuseAddress, 1056 FeatureFuseAES, 1057 FeatureFuseCCSelect, 1058 FeatureFuseAdrpAdd, 1059 FeatureFuseLiterals, 1060 FeatureLSLFast, 1061 FeaturePostRAScheduler, 1062 FeaturePredictableSelectIsExpensive]>; 1063 1064// Re-uses some scheduling and tunings from the ExynosM3 proc family. 1065def TuneExynosM4 : SubtargetFeature<"exynosm4", "ARMProcFamily", "ExynosM3", 1066 "Samsung Exynos-M4 processors", 1067 [FeatureArithmeticBccFusion, 1068 FeatureArithmeticCbzFusion, 1069 FeatureExynosCheapAsMoveHandling, 1070 FeatureForce32BitJumpTables, 1071 FeatureFuseAddress, 1072 FeatureFuseAES, 1073 FeatureFuseArithmeticLogic, 1074 FeatureFuseCCSelect, 1075 FeatureFuseAdrpAdd, 1076 FeatureFuseLiterals, 1077 FeatureLSLFast, 1078 FeaturePostRAScheduler, 1079 FeatureZCZeroing]>; 1080 1081def TuneKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo", 1082 "Qualcomm Kryo processors", [ 1083 FeatureCustomCheapAsMoveHandling, 1084 FeaturePostRAScheduler, 1085 FeaturePredictableSelectIsExpensive, 1086 FeatureZCZeroing, 1087 FeatureLSLFast] 1088 >; 1089 1090def TuneFalkor : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor", 1091 "Qualcomm Falkor processors", [ 1092 FeatureCustomCheapAsMoveHandling, 1093 FeaturePostRAScheduler, 1094 FeaturePredictableSelectIsExpensive, 1095 FeatureZCZeroing, 1096 FeatureLSLFast, 1097 FeatureSlowSTRQro 1098 ]>; 1099 1100def TuneNeoverseE1 : SubtargetFeature<"neoversee1", "ARMProcFamily", "NeoverseE1", 1101 "Neoverse E1 ARM processors", [ 1102 FeatureFuseAES, 1103 FeatureFuseAdrpAdd, 1104 FeaturePostRAScheduler]>; 1105 1106def TuneNeoverseN1 : SubtargetFeature<"neoversen1", "ARMProcFamily", "NeoverseN1", 1107 "Neoverse N1 ARM processors", [ 1108 FeatureFuseAES, 1109 FeatureFuseAdrpAdd, 1110 FeatureLSLFast, 1111 FeaturePostRAScheduler, 1112 FeatureEnableSelectOptimize, 1113 FeaturePredictableSelectIsExpensive]>; 1114 1115def TuneNeoverseN2 : SubtargetFeature<"neoversen2", "ARMProcFamily", "NeoverseN2", 1116 "Neoverse N2 ARM processors", [ 1117 FeatureFuseAES, 1118 FeatureFuseAdrpAdd, 1119 FeatureLSLFast, 1120 FeaturePostRAScheduler, 1121 FeatureEnableSelectOptimize, 1122 FeaturePredictableSelectIsExpensive]>; 1123 1124def TuneNeoverse512TVB : SubtargetFeature<"neoverse512tvb", "ARMProcFamily", "Neoverse512TVB", 1125 "Neoverse 512-TVB ARM processors", [ 1126 FeatureFuseAES, 1127 FeatureFuseAdrpAdd, 1128 FeatureLSLFast, 1129 FeaturePostRAScheduler, 1130 FeatureEnableSelectOptimize, 1131 FeaturePredictableSelectIsExpensive]>; 1132 1133def TuneNeoverseV1 : SubtargetFeature<"neoversev1", "ARMProcFamily", "NeoverseV1", 1134 "Neoverse V1 ARM processors", [ 1135 FeatureFuseAES, 1136 FeatureFuseAdrpAdd, 1137 FeatureLSLFast, 1138 FeaturePostRAScheduler, 1139 FeatureEnableSelectOptimize, 1140 FeaturePredictableSelectIsExpensive]>; 1141 1142def TuneNeoverseV2 : SubtargetFeature<"neoversev2", "ARMProcFamily", "NeoverseV2", 1143 "Neoverse V2 ARM processors", [ 1144 FeatureFuseAES, 1145 FeatureLSLFast, 1146 FeaturePostRAScheduler, 1147 FeatureEnableSelectOptimize, 1148 FeaturePredictableSelectIsExpensive]>; 1149 1150def TuneSaphira : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira", 1151 "Qualcomm Saphira processors", [ 1152 FeatureCustomCheapAsMoveHandling, 1153 FeaturePostRAScheduler, 1154 FeaturePredictableSelectIsExpensive, 1155 FeatureZCZeroing, 1156 FeatureLSLFast]>; 1157 1158def TuneThunderX2T99 : SubtargetFeature<"thunderx2t99", "ARMProcFamily", "ThunderX2T99", 1159 "Cavium ThunderX2 processors", [ 1160 FeatureAggressiveFMA, 1161 FeatureArithmeticBccFusion, 1162 FeaturePostRAScheduler, 1163 FeaturePredictableSelectIsExpensive]>; 1164 1165def TuneThunderX3T110 : SubtargetFeature<"thunderx3t110", "ARMProcFamily", 1166 "ThunderX3T110", 1167 "Marvell ThunderX3 processors", [ 1168 FeatureAggressiveFMA, 1169 FeatureArithmeticBccFusion, 1170 FeaturePostRAScheduler, 1171 FeaturePredictableSelectIsExpensive, 1172 FeatureBalanceFPOps, 1173 FeatureStrictAlign]>; 1174 1175def TuneThunderX : SubtargetFeature<"thunderx", "ARMProcFamily", "ThunderX", 1176 "Cavium ThunderX processors", [ 1177 FeaturePostRAScheduler, 1178 FeaturePredictableSelectIsExpensive]>; 1179 1180def TuneThunderXT88 : SubtargetFeature<"thunderxt88", "ARMProcFamily", 1181 "ThunderXT88", 1182 "Cavium ThunderX processors", [ 1183 FeaturePostRAScheduler, 1184 FeaturePredictableSelectIsExpensive]>; 1185 1186def TuneThunderXT81 : SubtargetFeature<"thunderxt81", "ARMProcFamily", 1187 "ThunderXT81", 1188 "Cavium ThunderX processors", [ 1189 FeaturePostRAScheduler, 1190 FeaturePredictableSelectIsExpensive]>; 1191 1192def TuneThunderXT83 : SubtargetFeature<"thunderxt83", "ARMProcFamily", 1193 "ThunderXT83", 1194 "Cavium ThunderX processors", [ 1195 FeaturePostRAScheduler, 1196 FeaturePredictableSelectIsExpensive]>; 1197 1198def TuneTSV110 : SubtargetFeature<"tsv110", "ARMProcFamily", "TSV110", 1199 "HiSilicon TS-V110 processors", [ 1200 FeatureCustomCheapAsMoveHandling, 1201 FeatureFuseAES, 1202 FeaturePostRAScheduler]>; 1203 1204def TuneAmpere1 : SubtargetFeature<"ampere1", "ARMProcFamily", "Ampere1", 1205 "Ampere Computing Ampere-1 processors", [ 1206 FeaturePostRAScheduler, 1207 FeatureFuseAES, 1208 FeatureLSLFast, 1209 FeatureAggressiveFMA, 1210 FeatureArithmeticBccFusion, 1211 FeatureCmpBccFusion, 1212 FeatureFuseAddress, 1213 FeatureFuseLiterals]>; 1214 1215def TuneAmpere1A : SubtargetFeature<"ampere1a", "ARMProcFamily", "Ampere1A", 1216 "Ampere Computing Ampere-1A processors", [ 1217 FeaturePostRAScheduler, 1218 FeatureFuseAES, 1219 FeatureLSLFast, 1220 FeatureAggressiveFMA, 1221 FeatureArithmeticBccFusion, 1222 FeatureCmpBccFusion, 1223 FeatureFuseAddress, 1224 FeatureFuseLiterals, 1225 FeatureFuseLiterals]>; 1226 1227def ProcessorFeatures { 1228 list<SubtargetFeature> A53 = [HasV8_0aOps, FeatureCRC, FeatureCrypto, 1229 FeatureFPARMv8, FeatureNEON, FeaturePerfMon]; 1230 list<SubtargetFeature> A55 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1231 FeatureNEON, FeatureFullFP16, FeatureDotProd, 1232 FeatureRCPC, FeaturePerfMon]; 1233 list<SubtargetFeature> A510 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon, 1234 FeatureMatMulInt8, FeatureBF16, FeatureAM, 1235 FeatureMTE, FeatureETE, FeatureSVE2BitPerm, 1236 FeatureFP16FML]; 1237 list<SubtargetFeature> A65 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1238 FeatureNEON, FeatureFullFP16, FeatureDotProd, 1239 FeatureRCPC, FeatureSSBS, FeatureRAS, 1240 FeaturePerfMon]; 1241 list<SubtargetFeature> A76 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1242 FeatureNEON, FeatureFullFP16, FeatureDotProd, 1243 FeatureRCPC, FeatureSSBS, FeaturePerfMon]; 1244 list<SubtargetFeature> A77 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1245 FeatureNEON, FeatureFullFP16, FeatureDotProd, 1246 FeatureRCPC, FeaturePerfMon, FeatureSSBS]; 1247 list<SubtargetFeature> A78 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1248 FeatureNEON, FeatureFullFP16, FeatureDotProd, 1249 FeatureRCPC, FeaturePerfMon, FeatureSPE, 1250 FeatureSSBS]; 1251 list<SubtargetFeature> A78C = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1252 FeatureNEON, FeatureFullFP16, FeatureDotProd, 1253 FeatureFlagM, FeatureFP16FML, FeaturePAuth, 1254 FeaturePerfMon, FeatureRCPC, FeatureSPE, 1255 FeatureSSBS]; 1256 list<SubtargetFeature> A710 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon, 1257 FeatureETE, FeatureMTE, FeatureFP16FML, 1258 FeatureSVE2BitPerm, FeatureBF16, FeatureMatMulInt8]; 1259 list<SubtargetFeature> A715 = [HasV9_0aOps, FeatureNEON, FeatureMTE, 1260 FeatureFP16FML, FeatureSVE, FeatureTRBE, 1261 FeatureSVE2BitPerm, FeatureBF16, FeatureETE, 1262 FeaturePerfMon, FeatureMatMulInt8, FeatureSPE]; 1263 list<SubtargetFeature> R82 = [HasV8_0rOps, FeaturePerfMon, FeatureFullFP16, 1264 FeatureFP16FML, FeatureSSBS, FeaturePredRes, 1265 FeatureSB]; 1266 list<SubtargetFeature> X1 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1267 FeatureNEON, FeatureRCPC, FeaturePerfMon, 1268 FeatureSPE, FeatureFullFP16, FeatureDotProd, 1269 FeatureSSBS]; 1270 list<SubtargetFeature> X1C = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1271 FeatureNEON, FeatureRCPC_IMMO, FeaturePerfMon, 1272 FeatureSPE, FeatureFullFP16, FeatureDotProd, 1273 FeaturePAuth, FeatureSSBS, FeatureFlagM, 1274 FeatureLSE2]; 1275 list<SubtargetFeature> X2 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon, 1276 FeatureMatMulInt8, FeatureBF16, FeatureAM, 1277 FeatureMTE, FeatureETE, FeatureSVE2BitPerm, 1278 FeatureFP16FML]; 1279 list<SubtargetFeature> X3 = [HasV9_0aOps, FeatureSVE, FeatureNEON, 1280 FeaturePerfMon, FeatureETE, FeatureTRBE, 1281 FeatureSPE, FeatureBF16, FeatureMatMulInt8, 1282 FeatureMTE, FeatureSVE2BitPerm, FeatureFullFP16, 1283 FeatureFP16FML]; 1284 list<SubtargetFeature> A64FX = [HasV8_2aOps, FeatureFPARMv8, FeatureNEON, 1285 FeatureSHA2, FeaturePerfMon, FeatureFullFP16, 1286 FeatureSVE, FeatureComplxNum]; 1287 list<SubtargetFeature> Carmel = [HasV8_2aOps, FeatureNEON, FeatureCrypto, 1288 FeatureFullFP16]; 1289 list<SubtargetFeature> AppleA7 = [HasV8_0aOps, FeatureCrypto, FeatureFPARMv8, 1290 FeatureNEON,FeaturePerfMon, FeatureAppleA7SysReg]; 1291 list<SubtargetFeature> AppleA10 = [HasV8_0aOps, FeatureCrypto, FeatureFPARMv8, 1292 FeatureNEON, FeaturePerfMon, FeatureCRC, 1293 FeatureRDM, FeaturePAN, FeatureLOR, FeatureVH]; 1294 list<SubtargetFeature> AppleA11 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1295 FeatureNEON, FeaturePerfMon, FeatureFullFP16]; 1296 list<SubtargetFeature> AppleA12 = [HasV8_3aOps, FeatureCrypto, FeatureFPARMv8, 1297 FeatureNEON, FeaturePerfMon, FeatureFullFP16]; 1298 list<SubtargetFeature> AppleA13 = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8, 1299 FeatureNEON, FeaturePerfMon, FeatureFullFP16, 1300 FeatureFP16FML, FeatureSHA3]; 1301 list<SubtargetFeature> AppleA14 = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8, 1302 FeatureNEON, FeaturePerfMon, FeatureFRInt3264, 1303 FeatureSpecRestrict, FeatureSSBS, FeatureSB, 1304 FeaturePredRes, FeatureCacheDeepPersist, 1305 FeatureFullFP16, FeatureFP16FML, FeatureSHA3, 1306 FeatureAltFPCmp]; 1307 list<SubtargetFeature> AppleA15 = [HasV8_6aOps, FeatureCrypto, FeatureFPARMv8, 1308 FeatureNEON, FeaturePerfMon, FeatureSHA3, 1309 FeatureFullFP16, FeatureFP16FML]; 1310 list<SubtargetFeature> AppleA16 = [HasV8_6aOps, FeatureCrypto, FeatureFPARMv8, 1311 FeatureNEON, FeaturePerfMon, FeatureSHA3, 1312 FeatureFullFP16, FeatureFP16FML, 1313 FeatureHCX]; 1314 list<SubtargetFeature> ExynosM3 = [HasV8_0aOps, FeatureCRC, FeatureCrypto, 1315 FeaturePerfMon]; 1316 list<SubtargetFeature> ExynosM4 = [HasV8_2aOps, FeatureCrypto, FeatureDotProd, 1317 FeatureFullFP16, FeaturePerfMon]; 1318 list<SubtargetFeature> Falkor = [HasV8_0aOps, FeatureCRC, FeatureCrypto, 1319 FeatureFPARMv8, FeatureNEON, FeaturePerfMon, 1320 FeatureRDM]; 1321 list<SubtargetFeature> NeoverseE1 = [HasV8_2aOps, FeatureCrypto, FeatureDotProd, 1322 FeatureFPARMv8, FeatureFullFP16, FeatureNEON, 1323 FeatureRCPC, FeatureSSBS, FeaturePerfMon]; 1324 list<SubtargetFeature> NeoverseN1 = [HasV8_2aOps, FeatureCrypto, FeatureDotProd, 1325 FeatureFPARMv8, FeatureFullFP16, FeatureNEON, 1326 FeatureRCPC, FeatureSPE, FeatureSSBS, 1327 FeaturePerfMon]; 1328 list<SubtargetFeature> NeoverseN2 = [HasV8_5aOps, FeatureBF16, FeatureETE, 1329 FeatureMatMulInt8, FeatureMTE, FeatureSVE2, 1330 FeatureSVE2BitPerm, FeatureTRBE, FeatureCrypto, 1331 FeaturePerfMon]; 1332 list<SubtargetFeature> Neoverse512TVB = [HasV8_4aOps, FeatureBF16, FeatureCacheDeepPersist, 1333 FeatureCrypto, FeatureFPARMv8, FeatureFP16FML, 1334 FeatureFullFP16, FeatureMatMulInt8, FeatureNEON, 1335 FeaturePerfMon, FeatureRandGen, FeatureSPE, 1336 FeatureSSBS, FeatureSVE]; 1337 list<SubtargetFeature> NeoverseV1 = [HasV8_4aOps, FeatureBF16, FeatureCacheDeepPersist, 1338 FeatureCrypto, FeatureFPARMv8, FeatureFP16FML, 1339 FeatureFullFP16, FeatureMatMulInt8, FeatureNEON, 1340 FeaturePerfMon, FeatureRandGen, FeatureSPE, 1341 FeatureSSBS, FeatureSVE]; 1342 list<SubtargetFeature> NeoverseV2 = [HasV9_0aOps, FeatureBF16, FeatureSPE, 1343 FeaturePerfMon, FeatureETE, FeatureMatMulInt8, 1344 FeatureNEON, FeatureSVE2BitPerm, FeatureFP16FML, 1345 FeatureMTE, FeatureRandGen]; 1346 list<SubtargetFeature> Saphira = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8, 1347 FeatureNEON, FeatureSPE, FeaturePerfMon]; 1348 list<SubtargetFeature> ThunderX = [HasV8_0aOps, FeatureCRC, FeatureCrypto, 1349 FeatureFPARMv8, FeaturePerfMon, FeatureNEON]; 1350 list<SubtargetFeature> ThunderX2T99 = [HasV8_1aOps, FeatureCRC, FeatureCrypto, 1351 FeatureFPARMv8, FeatureNEON, FeatureLSE]; 1352 list<SubtargetFeature> ThunderX3T110 = [HasV8_3aOps, FeatureCRC, FeatureCrypto, 1353 FeatureFPARMv8, FeatureNEON, FeatureLSE, 1354 FeaturePAuth, FeaturePerfMon]; 1355 list<SubtargetFeature> TSV110 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, 1356 FeatureNEON, FeaturePerfMon, FeatureSPE, 1357 FeatureFullFP16, FeatureFP16FML, FeatureDotProd]; 1358 list<SubtargetFeature> Ampere1 = [HasV8_6aOps, FeatureNEON, FeaturePerfMon, 1359 FeatureSSBS, FeatureRandGen, FeatureSB, 1360 FeatureSHA2, FeatureSHA3, FeatureAES]; 1361 list<SubtargetFeature> Ampere1A = [HasV8_6aOps, FeatureNEON, FeaturePerfMon, 1362 FeatureMTE, FeatureSSBS, FeatureRandGen, 1363 FeatureSB, FeatureSM4, FeatureSHA2, 1364 FeatureSHA3, FeatureAES]; 1365 1366 // ETE and TRBE are future architecture extensions. We temporarily enable them 1367 // by default for users targeting generic AArch64. The extensions do not 1368 // affect code generated by the compiler and can be used only by explicitly 1369 // mentioning the new system register names in assembly. 1370 list<SubtargetFeature> Generic = [FeatureFPARMv8, FeatureNEON, FeatureETE]; 1371} 1372 1373// FeatureFuseAdrpAdd is enabled under Generic to allow linker merging 1374// optimizations. 1375def : ProcessorModel<"generic", CortexA55Model, ProcessorFeatures.Generic, 1376 [FeatureFuseAES, FeatureFuseAdrpAdd, FeaturePostRAScheduler, 1377 FeatureEnableSelectOptimize]>; 1378def : ProcessorModel<"cortex-a35", CortexA53Model, ProcessorFeatures.A53, 1379 [TuneA35]>; 1380def : ProcessorModel<"cortex-a34", CortexA53Model, ProcessorFeatures.A53, 1381 [TuneA35]>; 1382def : ProcessorModel<"cortex-a53", CortexA53Model, ProcessorFeatures.A53, 1383 [TuneA53]>; 1384def : ProcessorModel<"cortex-a55", CortexA55Model, ProcessorFeatures.A55, 1385 [TuneA55]>; 1386def : ProcessorModel<"cortex-a510", CortexA510Model, ProcessorFeatures.A510, 1387 [TuneA510]>; 1388def : ProcessorModel<"cortex-a57", CortexA57Model, ProcessorFeatures.A53, 1389 [TuneA57]>; 1390def : ProcessorModel<"cortex-a65", CortexA53Model, ProcessorFeatures.A65, 1391 [TuneA65]>; 1392def : ProcessorModel<"cortex-a65ae", CortexA53Model, ProcessorFeatures.A65, 1393 [TuneA65]>; 1394def : ProcessorModel<"cortex-a72", CortexA57Model, ProcessorFeatures.A53, 1395 [TuneA72]>; 1396def : ProcessorModel<"cortex-a73", CortexA57Model, ProcessorFeatures.A53, 1397 [TuneA73]>; 1398def : ProcessorModel<"cortex-a75", CortexA57Model, ProcessorFeatures.A55, 1399 [TuneA75]>; 1400def : ProcessorModel<"cortex-a76", CortexA57Model, ProcessorFeatures.A76, 1401 [TuneA76]>; 1402def : ProcessorModel<"cortex-a76ae", CortexA57Model, ProcessorFeatures.A76, 1403 [TuneA76]>; 1404def : ProcessorModel<"cortex-a77", CortexA57Model, ProcessorFeatures.A77, 1405 [TuneA77]>; 1406def : ProcessorModel<"cortex-a78", CortexA57Model, ProcessorFeatures.A78, 1407 [TuneA78]>; 1408def : ProcessorModel<"cortex-a78c", CortexA57Model, ProcessorFeatures.A78C, 1409 [TuneA78C]>; 1410def : ProcessorModel<"cortex-a710", NeoverseN2Model, ProcessorFeatures.A710, 1411 [TuneA710]>; 1412def : ProcessorModel<"cortex-a715", NeoverseN2Model, ProcessorFeatures.A715, 1413 [TuneA715]>; 1414def : ProcessorModel<"cortex-r82", CortexA55Model, ProcessorFeatures.R82, 1415 [TuneR82]>; 1416def : ProcessorModel<"cortex-x1", CortexA57Model, ProcessorFeatures.X1, 1417 [TuneX1]>; 1418def : ProcessorModel<"cortex-x1c", CortexA57Model, ProcessorFeatures.X1C, 1419 [TuneX1]>; 1420def : ProcessorModel<"cortex-x2", NeoverseN2Model, ProcessorFeatures.X2, 1421 [TuneX2]>; 1422def : ProcessorModel<"cortex-x3", NeoverseN2Model, ProcessorFeatures.X3, 1423 [TuneX3]>; 1424def : ProcessorModel<"neoverse-e1", CortexA53Model, 1425 ProcessorFeatures.NeoverseE1, [TuneNeoverseE1]>; 1426def : ProcessorModel<"neoverse-n1", NeoverseN1Model, 1427 ProcessorFeatures.NeoverseN1, [TuneNeoverseN1]>; 1428def : ProcessorModel<"neoverse-n2", NeoverseN2Model, 1429 ProcessorFeatures.NeoverseN2, [TuneNeoverseN2]>; 1430def : ProcessorModel<"neoverse-512tvb", NeoverseV1Model, 1431 ProcessorFeatures.Neoverse512TVB, [TuneNeoverse512TVB]>; 1432def : ProcessorModel<"neoverse-v1", NeoverseV1Model, 1433 ProcessorFeatures.NeoverseV1, [TuneNeoverseV1]>; 1434def : ProcessorModel<"neoverse-v2", NeoverseV2Model, 1435 ProcessorFeatures.NeoverseV2, [TuneNeoverseV2]>; 1436def : ProcessorModel<"exynos-m3", ExynosM3Model, ProcessorFeatures.ExynosM3, 1437 [TuneExynosM3]>; 1438def : ProcessorModel<"exynos-m4", ExynosM4Model, ProcessorFeatures.ExynosM4, 1439 [TuneExynosM4]>; 1440def : ProcessorModel<"exynos-m5", ExynosM5Model, ProcessorFeatures.ExynosM4, 1441 [TuneExynosM4]>; 1442def : ProcessorModel<"falkor", FalkorModel, ProcessorFeatures.Falkor, 1443 [TuneFalkor]>; 1444def : ProcessorModel<"saphira", FalkorModel, ProcessorFeatures.Saphira, 1445 [TuneSaphira]>; 1446def : ProcessorModel<"kryo", KryoModel, ProcessorFeatures.A53, [TuneKryo]>; 1447 1448// Cavium ThunderX/ThunderX T8X Processors 1449def : ProcessorModel<"thunderx", ThunderXT8XModel, ProcessorFeatures.ThunderX, 1450 [TuneThunderX]>; 1451def : ProcessorModel<"thunderxt88", ThunderXT8XModel, 1452 ProcessorFeatures.ThunderX, [TuneThunderXT88]>; 1453def : ProcessorModel<"thunderxt81", ThunderXT8XModel, 1454 ProcessorFeatures.ThunderX, [TuneThunderXT81]>; 1455def : ProcessorModel<"thunderxt83", ThunderXT8XModel, 1456 ProcessorFeatures.ThunderX, [TuneThunderXT83]>; 1457// Cavium ThunderX2T9X Processors. Formerly Broadcom Vulcan. 1458def : ProcessorModel<"thunderx2t99", ThunderX2T99Model, 1459 ProcessorFeatures.ThunderX2T99, [TuneThunderX2T99]>; 1460// Marvell ThunderX3T110 Processors. 1461def : ProcessorModel<"thunderx3t110", ThunderX3T110Model, 1462 ProcessorFeatures.ThunderX3T110, [TuneThunderX3T110]>; 1463def : ProcessorModel<"tsv110", TSV110Model, ProcessorFeatures.TSV110, 1464 [TuneTSV110]>; 1465 1466// Support cyclone as an alias for apple-a7 so we can still LTO old bitcode. 1467def : ProcessorModel<"cyclone", CycloneModel, ProcessorFeatures.AppleA7, 1468 [TuneAppleA7]>; 1469 1470// iPhone and iPad CPUs 1471def : ProcessorModel<"apple-a7", CycloneModel, ProcessorFeatures.AppleA7, 1472 [TuneAppleA7]>; 1473def : ProcessorModel<"apple-a8", CycloneModel, ProcessorFeatures.AppleA7, 1474 [TuneAppleA7]>; 1475def : ProcessorModel<"apple-a9", CycloneModel, ProcessorFeatures.AppleA7, 1476 [TuneAppleA7]>; 1477def : ProcessorModel<"apple-a10", CycloneModel, ProcessorFeatures.AppleA10, 1478 [TuneAppleA10]>; 1479def : ProcessorModel<"apple-a11", CycloneModel, ProcessorFeatures.AppleA11, 1480 [TuneAppleA11]>; 1481def : ProcessorModel<"apple-a12", CycloneModel, ProcessorFeatures.AppleA12, 1482 [TuneAppleA12]>; 1483def : ProcessorModel<"apple-a13", CycloneModel, ProcessorFeatures.AppleA13, 1484 [TuneAppleA13]>; 1485def : ProcessorModel<"apple-a14", CycloneModel, ProcessorFeatures.AppleA14, 1486 [TuneAppleA14]>; 1487def : ProcessorModel<"apple-a15", CycloneModel, ProcessorFeatures.AppleA15, 1488 [TuneAppleA15]>; 1489def : ProcessorModel<"apple-a16", CycloneModel, ProcessorFeatures.AppleA16, 1490 [TuneAppleA16]>; 1491 1492// Mac CPUs 1493def : ProcessorModel<"apple-m1", CycloneModel, ProcessorFeatures.AppleA14, 1494 [TuneAppleA14]>; 1495def : ProcessorModel<"apple-m2", CycloneModel, ProcessorFeatures.AppleA15, 1496 [TuneAppleA15]>; 1497 1498// watch CPUs. 1499def : ProcessorModel<"apple-s4", CycloneModel, ProcessorFeatures.AppleA12, 1500 [TuneAppleA12]>; 1501def : ProcessorModel<"apple-s5", CycloneModel, ProcessorFeatures.AppleA12, 1502 [TuneAppleA12]>; 1503 1504// Alias for the latest Apple processor model supported by LLVM. 1505def : ProcessorModel<"apple-latest", CycloneModel, ProcessorFeatures.AppleA16, 1506 [TuneAppleA16]>; 1507 1508// Fujitsu A64FX 1509def : ProcessorModel<"a64fx", A64FXModel, ProcessorFeatures.A64FX, 1510 [TuneA64FX]>; 1511 1512// Nvidia Carmel 1513def : ProcessorModel<"carmel", NoSchedModel, ProcessorFeatures.Carmel, 1514 [TuneCarmel]>; 1515 1516// Ampere Computing 1517def : ProcessorModel<"ampere1", Ampere1Model, ProcessorFeatures.Ampere1, 1518 [TuneAmpere1]>; 1519 1520def : ProcessorModel<"ampere1a", Ampere1Model, ProcessorFeatures.Ampere1A, 1521 [TuneAmpere1A]>; 1522 1523//===----------------------------------------------------------------------===// 1524// Assembly parser 1525//===----------------------------------------------------------------------===// 1526 1527def GenericAsmParserVariant : AsmParserVariant { 1528 int Variant = 0; 1529 string Name = "generic"; 1530 string BreakCharacters = "."; 1531 string TokenizingCharacters = "[]*!/"; 1532} 1533 1534def AppleAsmParserVariant : AsmParserVariant { 1535 int Variant = 1; 1536 string Name = "apple-neon"; 1537 string BreakCharacters = "."; 1538 string TokenizingCharacters = "[]*!/"; 1539} 1540 1541//===----------------------------------------------------------------------===// 1542// Assembly printer 1543//===----------------------------------------------------------------------===// 1544// AArch64 Uses the MC printer for asm output, so make sure the TableGen 1545// AsmWriter bits get associated with the correct class. 1546def GenericAsmWriter : AsmWriter { 1547 string AsmWriterClassName = "InstPrinter"; 1548 int PassSubtarget = 1; 1549 int Variant = 0; 1550 bit isMCAsmWriter = 1; 1551} 1552 1553def AppleAsmWriter : AsmWriter { 1554 let AsmWriterClassName = "AppleInstPrinter"; 1555 int PassSubtarget = 1; 1556 int Variant = 1; 1557 int isMCAsmWriter = 1; 1558} 1559 1560//===----------------------------------------------------------------------===// 1561// Target Declaration 1562//===----------------------------------------------------------------------===// 1563 1564def AArch64 : Target { 1565 let InstructionSet = AArch64InstrInfo; 1566 let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant]; 1567 let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter]; 1568 let AllowRegisterRenaming = 1; 1569} 1570 1571//===----------------------------------------------------------------------===// 1572// Pfm Counters 1573//===----------------------------------------------------------------------===// 1574 1575include "AArch64PfmCounters.td" 1576