1 //===- MIPS.cpp -----------------------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "InputFiles.h" 10 #include "OutputSections.h" 11 #include "Symbols.h" 12 #include "SyntheticSections.h" 13 #include "Target.h" 14 #include "Thunks.h" 15 #include "lld/Common/ErrorHandler.h" 16 #include "llvm/Object/ELF.h" 17 #include "llvm/Support/Endian.h" 18 19 using namespace llvm; 20 using namespace llvm::object; 21 using namespace llvm::support::endian; 22 using namespace llvm::ELF; 23 using namespace lld; 24 using namespace lld::elf; 25 26 namespace { 27 template <class ELFT> class MIPS final : public TargetInfo { 28 public: 29 MIPS(); 30 uint32_t calcEFlags() const override; 31 RelExpr getRelExpr(RelType type, const Symbol &s, 32 const uint8_t *loc) const override; 33 int64_t getImplicitAddend(const uint8_t *buf, RelType type) const override; 34 RelType getDynRel(RelType type) const override; 35 void writeGotPlt(uint8_t *buf, const Symbol &s) const override; 36 void writePltHeader(uint8_t *buf) const override; 37 void writePlt(uint8_t *buf, uint64_t gotPltEntryAddr, uint64_t pltEntryAddr, 38 int32_t index, unsigned relOff) const override; 39 bool needsThunk(RelExpr expr, RelType type, const InputFile *file, 40 uint64_t branchAddr, const Symbol &s) const override; 41 void relocateOne(uint8_t *loc, RelType type, uint64_t val) const override; 42 bool usesOnlyLowPageBits(RelType type) const override; 43 }; 44 } // namespace 45 46 template <class ELFT> MIPS<ELFT>::MIPS() { 47 gotPltHeaderEntriesNum = 2; 48 defaultMaxPageSize = 65536; 49 gotBaseSymInGotPlt = false; 50 pltEntrySize = 16; 51 pltHeaderSize = 32; 52 copyRel = R_MIPS_COPY; 53 noneRel = R_MIPS_NONE; 54 pltRel = R_MIPS_JUMP_SLOT; 55 needsThunks = true; 56 57 // Set `sigrie 1` as a trap instruction. 58 write32(trapInstr.data(), 0x04170001); 59 60 if (ELFT::Is64Bits) { 61 relativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32; 62 symbolicRel = R_MIPS_64; 63 tlsGotRel = R_MIPS_TLS_TPREL64; 64 tlsModuleIndexRel = R_MIPS_TLS_DTPMOD64; 65 tlsOffsetRel = R_MIPS_TLS_DTPREL64; 66 } else { 67 relativeRel = R_MIPS_REL32; 68 symbolicRel = R_MIPS_32; 69 tlsGotRel = R_MIPS_TLS_TPREL32; 70 tlsModuleIndexRel = R_MIPS_TLS_DTPMOD32; 71 tlsOffsetRel = R_MIPS_TLS_DTPREL32; 72 } 73 } 74 75 template <class ELFT> uint32_t MIPS<ELFT>::calcEFlags() const { 76 return calcMipsEFlags<ELFT>(); 77 } 78 79 template <class ELFT> 80 RelExpr MIPS<ELFT>::getRelExpr(RelType type, const Symbol &s, 81 const uint8_t *loc) const { 82 // See comment in the calculateMipsRelChain. 83 if (ELFT::Is64Bits || config->mipsN32Abi) 84 type &= 0xff; 85 86 switch (type) { 87 case R_MIPS_JALR: 88 case R_MICROMIPS_JALR: 89 return R_HINT; 90 case R_MIPS_GPREL16: 91 case R_MIPS_GPREL32: 92 case R_MICROMIPS_GPREL16: 93 case R_MICROMIPS_GPREL7_S2: 94 return R_MIPS_GOTREL; 95 case R_MIPS_26: 96 case R_MICROMIPS_26_S1: 97 return R_PLT; 98 case R_MICROMIPS_PC26_S1: 99 return R_PLT_PC; 100 case R_MIPS_HI16: 101 case R_MIPS_LO16: 102 case R_MIPS_HIGHER: 103 case R_MIPS_HIGHEST: 104 case R_MICROMIPS_HI16: 105 case R_MICROMIPS_LO16: 106 // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate 107 // offset between start of function and 'gp' value which by default 108 // equal to the start of .got section. In that case we consider these 109 // relocations as relative. 110 if (&s == ElfSym::mipsGpDisp) 111 return R_MIPS_GOT_GP_PC; 112 if (&s == ElfSym::mipsLocalGp) 113 return R_MIPS_GOT_GP; 114 LLVM_FALLTHROUGH; 115 case R_MIPS_32: 116 case R_MIPS_64: 117 case R_MIPS_GOT_OFST: 118 case R_MIPS_SUB: 119 case R_MIPS_TLS_DTPREL_HI16: 120 case R_MIPS_TLS_DTPREL_LO16: 121 case R_MIPS_TLS_DTPREL32: 122 case R_MIPS_TLS_DTPREL64: 123 case R_MIPS_TLS_TPREL_HI16: 124 case R_MIPS_TLS_TPREL_LO16: 125 case R_MIPS_TLS_TPREL32: 126 case R_MIPS_TLS_TPREL64: 127 case R_MICROMIPS_TLS_DTPREL_HI16: 128 case R_MICROMIPS_TLS_DTPREL_LO16: 129 case R_MICROMIPS_TLS_TPREL_HI16: 130 case R_MICROMIPS_TLS_TPREL_LO16: 131 return R_ABS; 132 case R_MIPS_PC32: 133 case R_MIPS_PC16: 134 case R_MIPS_PC19_S2: 135 case R_MIPS_PC21_S2: 136 case R_MIPS_PC26_S2: 137 case R_MIPS_PCHI16: 138 case R_MIPS_PCLO16: 139 case R_MICROMIPS_PC7_S1: 140 case R_MICROMIPS_PC10_S1: 141 case R_MICROMIPS_PC16_S1: 142 case R_MICROMIPS_PC18_S3: 143 case R_MICROMIPS_PC19_S2: 144 case R_MICROMIPS_PC23_S2: 145 case R_MICROMIPS_PC21_S1: 146 return R_PC; 147 case R_MIPS_GOT16: 148 case R_MICROMIPS_GOT16: 149 if (s.isLocal()) 150 return R_MIPS_GOT_LOCAL_PAGE; 151 LLVM_FALLTHROUGH; 152 case R_MIPS_CALL16: 153 case R_MIPS_GOT_DISP: 154 case R_MIPS_TLS_GOTTPREL: 155 case R_MICROMIPS_CALL16: 156 case R_MICROMIPS_TLS_GOTTPREL: 157 return R_MIPS_GOT_OFF; 158 case R_MIPS_CALL_HI16: 159 case R_MIPS_CALL_LO16: 160 case R_MIPS_GOT_HI16: 161 case R_MIPS_GOT_LO16: 162 case R_MICROMIPS_CALL_HI16: 163 case R_MICROMIPS_CALL_LO16: 164 case R_MICROMIPS_GOT_HI16: 165 case R_MICROMIPS_GOT_LO16: 166 return R_MIPS_GOT_OFF32; 167 case R_MIPS_GOT_PAGE: 168 return R_MIPS_GOT_LOCAL_PAGE; 169 case R_MIPS_TLS_GD: 170 case R_MICROMIPS_TLS_GD: 171 return R_MIPS_TLSGD; 172 case R_MIPS_TLS_LDM: 173 case R_MICROMIPS_TLS_LDM: 174 return R_MIPS_TLSLD; 175 case R_MIPS_NONE: 176 return R_NONE; 177 default: 178 error(getErrorLocation(loc) + "unknown relocation (" + Twine(type) + 179 ") against symbol " + toString(s)); 180 return R_NONE; 181 } 182 } 183 184 template <class ELFT> RelType MIPS<ELFT>::getDynRel(RelType type) const { 185 if (type == symbolicRel) 186 return type; 187 return R_MIPS_NONE; 188 } 189 190 template <class ELFT> 191 void MIPS<ELFT>::writeGotPlt(uint8_t *buf, const Symbol &) const { 192 uint64_t va = in.plt->getVA(); 193 if (isMicroMips()) 194 va |= 1; 195 write32<ELFT::TargetEndianness>(buf, va); 196 } 197 198 template <endianness E> static uint32_t readShuffle(const uint8_t *loc) { 199 // The major opcode of a microMIPS instruction needs to appear 200 // in the first 16-bit word (lowest address) for efficient hardware 201 // decode so that it knows if the instruction is 16-bit or 32-bit 202 // as early as possible. To do so, little-endian binaries keep 16-bit 203 // words in a big-endian order. That is why we have to swap these 204 // words to get a correct value. 205 uint32_t v = read32<E>(loc); 206 if (E == support::little) 207 return (v << 16) | (v >> 16); 208 return v; 209 } 210 211 template <endianness E> 212 static void writeValue(uint8_t *loc, uint64_t v, uint8_t bitsSize, 213 uint8_t shift) { 214 uint32_t instr = read32<E>(loc); 215 uint32_t mask = 0xffffffff >> (32 - bitsSize); 216 uint32_t data = (instr & ~mask) | ((v >> shift) & mask); 217 write32<E>(loc, data); 218 } 219 220 template <endianness E> 221 static void writeShuffleValue(uint8_t *loc, uint64_t v, uint8_t bitsSize, 222 uint8_t shift) { 223 // See comments in readShuffle for purpose of this code. 224 uint16_t *words = (uint16_t *)loc; 225 if (E == support::little) 226 std::swap(words[0], words[1]); 227 228 writeValue<E>(loc, v, bitsSize, shift); 229 230 if (E == support::little) 231 std::swap(words[0], words[1]); 232 } 233 234 template <endianness E> 235 static void writeMicroRelocation16(uint8_t *loc, uint64_t v, uint8_t bitsSize, 236 uint8_t shift) { 237 uint16_t instr = read16<E>(loc); 238 uint16_t mask = 0xffff >> (16 - bitsSize); 239 uint16_t data = (instr & ~mask) | ((v >> shift) & mask); 240 write16<E>(loc, data); 241 } 242 243 template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *buf) const { 244 const endianness e = ELFT::TargetEndianness; 245 if (isMicroMips()) { 246 uint64_t gotPlt = in.gotPlt->getVA(); 247 uint64_t plt = in.plt->getVA(); 248 // Overwrite trap instructions written by Writer::writeTrapInstr. 249 memset(buf, 0, pltHeaderSize); 250 251 write16<e>(buf, isMipsR6() ? 0x7860 : 0x7980); // addiupc v1, (GOTPLT) - . 252 write16<e>(buf + 4, 0xff23); // lw $25, 0($3) 253 write16<e>(buf + 8, 0x0535); // subu16 $2, $2, $3 254 write16<e>(buf + 10, 0x2525); // srl16 $2, $2, 2 255 write16<e>(buf + 12, 0x3302); // addiu $24, $2, -2 256 write16<e>(buf + 14, 0xfffe); 257 write16<e>(buf + 16, 0x0dff); // move $15, $31 258 if (isMipsR6()) { 259 write16<e>(buf + 18, 0x0f83); // move $28, $3 260 write16<e>(buf + 20, 0x472b); // jalrc $25 261 write16<e>(buf + 22, 0x0c00); // nop 262 relocateOne(buf, R_MICROMIPS_PC19_S2, gotPlt - plt); 263 } else { 264 write16<e>(buf + 18, 0x45f9); // jalrc $25 265 write16<e>(buf + 20, 0x0f83); // move $28, $3 266 write16<e>(buf + 22, 0x0c00); // nop 267 relocateOne(buf, R_MICROMIPS_PC23_S2, gotPlt - plt); 268 } 269 return; 270 } 271 272 if (config->mipsN32Abi) { 273 write32<e>(buf, 0x3c0e0000); // lui $14, %hi(&GOTPLT[0]) 274 write32<e>(buf + 4, 0x8dd90000); // lw $25, %lo(&GOTPLT[0])($14) 275 write32<e>(buf + 8, 0x25ce0000); // addiu $14, $14, %lo(&GOTPLT[0]) 276 write32<e>(buf + 12, 0x030ec023); // subu $24, $24, $14 277 write32<e>(buf + 16, 0x03e07825); // move $15, $31 278 write32<e>(buf + 20, 0x0018c082); // srl $24, $24, 2 279 } else if (ELFT::Is64Bits) { 280 write32<e>(buf, 0x3c0e0000); // lui $14, %hi(&GOTPLT[0]) 281 write32<e>(buf + 4, 0xddd90000); // ld $25, %lo(&GOTPLT[0])($14) 282 write32<e>(buf + 8, 0x25ce0000); // addiu $14, $14, %lo(&GOTPLT[0]) 283 write32<e>(buf + 12, 0x030ec023); // subu $24, $24, $14 284 write32<e>(buf + 16, 0x03e07825); // move $15, $31 285 write32<e>(buf + 20, 0x0018c0c2); // srl $24, $24, 3 286 } else { 287 write32<e>(buf, 0x3c1c0000); // lui $28, %hi(&GOTPLT[0]) 288 write32<e>(buf + 4, 0x8f990000); // lw $25, %lo(&GOTPLT[0])($28) 289 write32<e>(buf + 8, 0x279c0000); // addiu $28, $28, %lo(&GOTPLT[0]) 290 write32<e>(buf + 12, 0x031cc023); // subu $24, $24, $28 291 write32<e>(buf + 16, 0x03e07825); // move $15, $31 292 write32<e>(buf + 20, 0x0018c082); // srl $24, $24, 2 293 } 294 295 uint32_t jalrInst = config->zHazardplt ? 0x0320fc09 : 0x0320f809; 296 write32<e>(buf + 24, jalrInst); // jalr.hb $25 or jalr $25 297 write32<e>(buf + 28, 0x2718fffe); // subu $24, $24, 2 298 299 uint64_t gotPlt = in.gotPlt->getVA(); 300 writeValue<e>(buf, gotPlt + 0x8000, 16, 16); 301 writeValue<e>(buf + 4, gotPlt, 16, 0); 302 writeValue<e>(buf + 8, gotPlt, 16, 0); 303 } 304 305 template <class ELFT> 306 void MIPS<ELFT>::writePlt(uint8_t *buf, uint64_t gotPltEntryAddr, 307 uint64_t pltEntryAddr, int32_t index, 308 unsigned relOff) const { 309 const endianness e = ELFT::TargetEndianness; 310 if (isMicroMips()) { 311 // Overwrite trap instructions written by Writer::writeTrapInstr. 312 memset(buf, 0, pltEntrySize); 313 314 if (isMipsR6()) { 315 write16<e>(buf, 0x7840); // addiupc $2, (GOTPLT) - . 316 write16<e>(buf + 4, 0xff22); // lw $25, 0($2) 317 write16<e>(buf + 8, 0x0f02); // move $24, $2 318 write16<e>(buf + 10, 0x4723); // jrc $25 / jr16 $25 319 relocateOne(buf, R_MICROMIPS_PC19_S2, gotPltEntryAddr - pltEntryAddr); 320 } else { 321 write16<e>(buf, 0x7900); // addiupc $2, (GOTPLT) - . 322 write16<e>(buf + 4, 0xff22); // lw $25, 0($2) 323 write16<e>(buf + 8, 0x4599); // jrc $25 / jr16 $25 324 write16<e>(buf + 10, 0x0f02); // move $24, $2 325 relocateOne(buf, R_MICROMIPS_PC23_S2, gotPltEntryAddr - pltEntryAddr); 326 } 327 return; 328 } 329 330 uint32_t loadInst = ELFT::Is64Bits ? 0xddf90000 : 0x8df90000; 331 uint32_t jrInst = isMipsR6() ? (config->zHazardplt ? 0x03200409 : 0x03200009) 332 : (config->zHazardplt ? 0x03200408 : 0x03200008); 333 uint32_t addInst = ELFT::Is64Bits ? 0x65f80000 : 0x25f80000; 334 335 write32<e>(buf, 0x3c0f0000); // lui $15, %hi(.got.plt entry) 336 write32<e>(buf + 4, loadInst); // l[wd] $25, %lo(.got.plt entry)($15) 337 write32<e>(buf + 8, jrInst); // jr $25 / jr.hb $25 338 write32<e>(buf + 12, addInst); // [d]addiu $24, $15, %lo(.got.plt entry) 339 writeValue<e>(buf, gotPltEntryAddr + 0x8000, 16, 16); 340 writeValue<e>(buf + 4, gotPltEntryAddr, 16, 0); 341 writeValue<e>(buf + 12, gotPltEntryAddr, 16, 0); 342 } 343 344 template <class ELFT> 345 bool MIPS<ELFT>::needsThunk(RelExpr expr, RelType type, const InputFile *file, 346 uint64_t branchAddr, const Symbol &s) const { 347 // Any MIPS PIC code function is invoked with its address in register $t9. 348 // So if we have a branch instruction from non-PIC code to the PIC one 349 // we cannot make the jump directly and need to create a small stubs 350 // to save the target function address. 351 // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf 352 if (type != R_MIPS_26 && type != R_MIPS_PC26_S2 && 353 type != R_MICROMIPS_26_S1 && type != R_MICROMIPS_PC26_S1) 354 return false; 355 auto *f = dyn_cast_or_null<ObjFile<ELFT>>(file); 356 if (!f) 357 return false; 358 // If current file has PIC code, LA25 stub is not required. 359 if (f->getObj().getHeader()->e_flags & EF_MIPS_PIC) 360 return false; 361 auto *d = dyn_cast<Defined>(&s); 362 // LA25 is required if target file has PIC code 363 // or target symbol is a PIC symbol. 364 return d && isMipsPIC<ELFT>(d); 365 } 366 367 template <class ELFT> 368 int64_t MIPS<ELFT>::getImplicitAddend(const uint8_t *buf, RelType type) const { 369 const endianness e = ELFT::TargetEndianness; 370 switch (type) { 371 case R_MIPS_32: 372 case R_MIPS_GPREL32: 373 case R_MIPS_TLS_DTPREL32: 374 case R_MIPS_TLS_TPREL32: 375 return SignExtend64<32>(read32<e>(buf)); 376 case R_MIPS_26: 377 // FIXME (simon): If the relocation target symbol is not a PLT entry 378 // we should use another expression for calculation: 379 // ((A << 2) | (P & 0xf0000000)) >> 2 380 return SignExtend64<28>(read32<e>(buf) << 2); 381 case R_MIPS_GOT16: 382 case R_MIPS_HI16: 383 case R_MIPS_PCHI16: 384 return SignExtend64<16>(read32<e>(buf)) << 16; 385 case R_MIPS_GPREL16: 386 case R_MIPS_LO16: 387 case R_MIPS_PCLO16: 388 case R_MIPS_TLS_DTPREL_HI16: 389 case R_MIPS_TLS_DTPREL_LO16: 390 case R_MIPS_TLS_TPREL_HI16: 391 case R_MIPS_TLS_TPREL_LO16: 392 return SignExtend64<16>(read32<e>(buf)); 393 case R_MICROMIPS_GOT16: 394 case R_MICROMIPS_HI16: 395 return SignExtend64<16>(readShuffle<e>(buf)) << 16; 396 case R_MICROMIPS_GPREL16: 397 case R_MICROMIPS_LO16: 398 case R_MICROMIPS_TLS_DTPREL_HI16: 399 case R_MICROMIPS_TLS_DTPREL_LO16: 400 case R_MICROMIPS_TLS_TPREL_HI16: 401 case R_MICROMIPS_TLS_TPREL_LO16: 402 return SignExtend64<16>(readShuffle<e>(buf)); 403 case R_MICROMIPS_GPREL7_S2: 404 return SignExtend64<9>(readShuffle<e>(buf) << 2); 405 case R_MIPS_PC16: 406 return SignExtend64<18>(read32<e>(buf) << 2); 407 case R_MIPS_PC19_S2: 408 return SignExtend64<21>(read32<e>(buf) << 2); 409 case R_MIPS_PC21_S2: 410 return SignExtend64<23>(read32<e>(buf) << 2); 411 case R_MIPS_PC26_S2: 412 return SignExtend64<28>(read32<e>(buf) << 2); 413 case R_MIPS_PC32: 414 return SignExtend64<32>(read32<e>(buf)); 415 case R_MICROMIPS_26_S1: 416 return SignExtend64<27>(readShuffle<e>(buf) << 1); 417 case R_MICROMIPS_PC7_S1: 418 return SignExtend64<8>(read16<e>(buf) << 1); 419 case R_MICROMIPS_PC10_S1: 420 return SignExtend64<11>(read16<e>(buf) << 1); 421 case R_MICROMIPS_PC16_S1: 422 return SignExtend64<17>(readShuffle<e>(buf) << 1); 423 case R_MICROMIPS_PC18_S3: 424 return SignExtend64<21>(readShuffle<e>(buf) << 3); 425 case R_MICROMIPS_PC19_S2: 426 return SignExtend64<21>(readShuffle<e>(buf) << 2); 427 case R_MICROMIPS_PC21_S1: 428 return SignExtend64<22>(readShuffle<e>(buf) << 1); 429 case R_MICROMIPS_PC23_S2: 430 return SignExtend64<25>(readShuffle<e>(buf) << 2); 431 case R_MICROMIPS_PC26_S1: 432 return SignExtend64<27>(readShuffle<e>(buf) << 1); 433 default: 434 return 0; 435 } 436 } 437 438 static std::pair<uint32_t, uint64_t> 439 calculateMipsRelChain(uint8_t *loc, RelType type, uint64_t val) { 440 // MIPS N64 ABI packs multiple relocations into the single relocation 441 // record. In general, all up to three relocations can have arbitrary 442 // types. In fact, Clang and GCC uses only a few combinations. For now, 443 // we support two of them. That is allow to pass at least all LLVM 444 // test suite cases. 445 // <any relocation> / R_MIPS_SUB / R_MIPS_HI16 | R_MIPS_LO16 446 // <any relocation> / R_MIPS_64 / R_MIPS_NONE 447 // The first relocation is a 'real' relocation which is calculated 448 // using the corresponding symbol's value. The second and the third 449 // relocations used to modify result of the first one: extend it to 450 // 64-bit, extract high or low part etc. For details, see part 2.9 Relocation 451 // at the https://dmz-portal.mips.com/mw/images/8/82/007-4658-001.pdf 452 RelType type2 = (type >> 8) & 0xff; 453 RelType type3 = (type >> 16) & 0xff; 454 if (type2 == R_MIPS_NONE && type3 == R_MIPS_NONE) 455 return std::make_pair(type, val); 456 if (type2 == R_MIPS_64 && type3 == R_MIPS_NONE) 457 return std::make_pair(type2, val); 458 if (type2 == R_MIPS_SUB && (type3 == R_MIPS_HI16 || type3 == R_MIPS_LO16)) 459 return std::make_pair(type3, -val); 460 error(getErrorLocation(loc) + "unsupported relocations combination " + 461 Twine(type)); 462 return std::make_pair(type & 0xff, val); 463 } 464 465 static bool isBranchReloc(RelType type) { 466 return type == R_MIPS_26 || type == R_MIPS_PC26_S2 || 467 type == R_MIPS_PC21_S2 || type == R_MIPS_PC16; 468 } 469 470 static bool isMicroBranchReloc(RelType type) { 471 return type == R_MICROMIPS_26_S1 || type == R_MICROMIPS_PC16_S1 || 472 type == R_MICROMIPS_PC10_S1 || type == R_MICROMIPS_PC7_S1; 473 } 474 475 template <class ELFT> 476 static uint64_t fixupCrossModeJump(uint8_t *loc, RelType type, uint64_t val) { 477 // Here we need to detect jump/branch from regular MIPS code 478 // to a microMIPS target and vice versa. In that cases jump 479 // instructions need to be replaced by their "cross-mode" 480 // equivalents. 481 const endianness e = ELFT::TargetEndianness; 482 bool isMicroTgt = val & 0x1; 483 bool isCrossJump = (isMicroTgt && isBranchReloc(type)) || 484 (!isMicroTgt && isMicroBranchReloc(type)); 485 if (!isCrossJump) 486 return val; 487 488 switch (type) { 489 case R_MIPS_26: { 490 uint32_t inst = read32<e>(loc) >> 26; 491 if (inst == 0x3 || inst == 0x1d) { // JAL or JALX 492 writeValue<e>(loc, 0x1d << 26, 32, 0); 493 return val; 494 } 495 break; 496 } 497 case R_MICROMIPS_26_S1: { 498 uint32_t inst = readShuffle<e>(loc) >> 26; 499 if (inst == 0x3d || inst == 0x3c) { // JAL32 or JALX32 500 val >>= 1; 501 writeShuffleValue<e>(loc, 0x3c << 26, 32, 0); 502 return val; 503 } 504 break; 505 } 506 case R_MIPS_PC26_S2: 507 case R_MIPS_PC21_S2: 508 case R_MIPS_PC16: 509 case R_MICROMIPS_PC16_S1: 510 case R_MICROMIPS_PC10_S1: 511 case R_MICROMIPS_PC7_S1: 512 // FIXME (simon): Support valid branch relocations. 513 break; 514 default: 515 llvm_unreachable("unexpected jump/branch relocation"); 516 } 517 518 error(getErrorLocation(loc) + 519 "unsupported jump/branch instruction between ISA modes referenced by " + 520 toString(type) + " relocation"); 521 return val; 522 } 523 524 template <class ELFT> 525 void MIPS<ELFT>::relocateOne(uint8_t *loc, RelType type, uint64_t val) const { 526 const endianness e = ELFT::TargetEndianness; 527 528 if (ELFT::Is64Bits || config->mipsN32Abi) 529 std::tie(type, val) = calculateMipsRelChain(loc, type, val); 530 531 // Detect cross-mode jump/branch and fix instruction. 532 val = fixupCrossModeJump<ELFT>(loc, type, val); 533 534 // Thread pointer and DRP offsets from the start of TLS data area. 535 // https://www.linux-mips.org/wiki/NPTL 536 if (type == R_MIPS_TLS_DTPREL_HI16 || type == R_MIPS_TLS_DTPREL_LO16 || 537 type == R_MIPS_TLS_DTPREL32 || type == R_MIPS_TLS_DTPREL64 || 538 type == R_MICROMIPS_TLS_DTPREL_HI16 || 539 type == R_MICROMIPS_TLS_DTPREL_LO16) { 540 val -= 0x8000; 541 } else if (type == R_MIPS_TLS_TPREL_HI16 || type == R_MIPS_TLS_TPREL_LO16 || 542 type == R_MIPS_TLS_TPREL32 || type == R_MIPS_TLS_TPREL64 || 543 type == R_MICROMIPS_TLS_TPREL_HI16 || 544 type == R_MICROMIPS_TLS_TPREL_LO16) { 545 val -= 0x7000; 546 } 547 548 switch (type) { 549 case R_MIPS_32: 550 case R_MIPS_GPREL32: 551 case R_MIPS_TLS_DTPREL32: 552 case R_MIPS_TLS_TPREL32: 553 write32<e>(loc, val); 554 break; 555 case R_MIPS_64: 556 case R_MIPS_TLS_DTPREL64: 557 case R_MIPS_TLS_TPREL64: 558 write64<e>(loc, val); 559 break; 560 case R_MIPS_26: 561 writeValue<e>(loc, val, 26, 2); 562 break; 563 case R_MIPS_GOT16: 564 // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode 565 // is updated addend (not a GOT index). In that case write high 16 bits 566 // to store a correct addend value. 567 if (config->relocatable) { 568 writeValue<e>(loc, val + 0x8000, 16, 16); 569 } else { 570 checkInt(loc, val, 16, type); 571 writeValue<e>(loc, val, 16, 0); 572 } 573 break; 574 case R_MICROMIPS_GOT16: 575 if (config->relocatable) { 576 writeShuffleValue<e>(loc, val + 0x8000, 16, 16); 577 } else { 578 checkInt(loc, val, 16, type); 579 writeShuffleValue<e>(loc, val, 16, 0); 580 } 581 break; 582 case R_MIPS_CALL16: 583 case R_MIPS_GOT_DISP: 584 case R_MIPS_GOT_PAGE: 585 case R_MIPS_GPREL16: 586 case R_MIPS_TLS_GD: 587 case R_MIPS_TLS_GOTTPREL: 588 case R_MIPS_TLS_LDM: 589 checkInt(loc, val, 16, type); 590 LLVM_FALLTHROUGH; 591 case R_MIPS_CALL_LO16: 592 case R_MIPS_GOT_LO16: 593 case R_MIPS_GOT_OFST: 594 case R_MIPS_LO16: 595 case R_MIPS_PCLO16: 596 case R_MIPS_TLS_DTPREL_LO16: 597 case R_MIPS_TLS_TPREL_LO16: 598 writeValue<e>(loc, val, 16, 0); 599 break; 600 case R_MICROMIPS_GPREL16: 601 case R_MICROMIPS_TLS_GD: 602 case R_MICROMIPS_TLS_LDM: 603 checkInt(loc, val, 16, type); 604 writeShuffleValue<e>(loc, val, 16, 0); 605 break; 606 case R_MICROMIPS_CALL16: 607 case R_MICROMIPS_CALL_LO16: 608 case R_MICROMIPS_LO16: 609 case R_MICROMIPS_TLS_DTPREL_LO16: 610 case R_MICROMIPS_TLS_GOTTPREL: 611 case R_MICROMIPS_TLS_TPREL_LO16: 612 writeShuffleValue<e>(loc, val, 16, 0); 613 break; 614 case R_MICROMIPS_GPREL7_S2: 615 checkInt(loc, val, 7, type); 616 writeShuffleValue<e>(loc, val, 7, 2); 617 break; 618 case R_MIPS_CALL_HI16: 619 case R_MIPS_GOT_HI16: 620 case R_MIPS_HI16: 621 case R_MIPS_PCHI16: 622 case R_MIPS_TLS_DTPREL_HI16: 623 case R_MIPS_TLS_TPREL_HI16: 624 writeValue<e>(loc, val + 0x8000, 16, 16); 625 break; 626 case R_MICROMIPS_CALL_HI16: 627 case R_MICROMIPS_GOT_HI16: 628 case R_MICROMIPS_HI16: 629 case R_MICROMIPS_TLS_DTPREL_HI16: 630 case R_MICROMIPS_TLS_TPREL_HI16: 631 writeShuffleValue<e>(loc, val + 0x8000, 16, 16); 632 break; 633 case R_MIPS_HIGHER: 634 writeValue<e>(loc, val + 0x80008000, 16, 32); 635 break; 636 case R_MIPS_HIGHEST: 637 writeValue<e>(loc, val + 0x800080008000, 16, 48); 638 break; 639 case R_MIPS_JALR: 640 case R_MICROMIPS_JALR: 641 // Ignore this optimization relocation for now 642 break; 643 case R_MIPS_PC16: 644 checkAlignment(loc, val, 4, type); 645 checkInt(loc, val, 18, type); 646 writeValue<e>(loc, val, 16, 2); 647 break; 648 case R_MIPS_PC19_S2: 649 checkAlignment(loc, val, 4, type); 650 checkInt(loc, val, 21, type); 651 writeValue<e>(loc, val, 19, 2); 652 break; 653 case R_MIPS_PC21_S2: 654 checkAlignment(loc, val, 4, type); 655 checkInt(loc, val, 23, type); 656 writeValue<e>(loc, val, 21, 2); 657 break; 658 case R_MIPS_PC26_S2: 659 checkAlignment(loc, val, 4, type); 660 checkInt(loc, val, 28, type); 661 writeValue<e>(loc, val, 26, 2); 662 break; 663 case R_MIPS_PC32: 664 writeValue<e>(loc, val, 32, 0); 665 break; 666 case R_MICROMIPS_26_S1: 667 case R_MICROMIPS_PC26_S1: 668 checkInt(loc, val, 27, type); 669 writeShuffleValue<e>(loc, val, 26, 1); 670 break; 671 case R_MICROMIPS_PC7_S1: 672 checkInt(loc, val, 8, type); 673 writeMicroRelocation16<e>(loc, val, 7, 1); 674 break; 675 case R_MICROMIPS_PC10_S1: 676 checkInt(loc, val, 11, type); 677 writeMicroRelocation16<e>(loc, val, 10, 1); 678 break; 679 case R_MICROMIPS_PC16_S1: 680 checkInt(loc, val, 17, type); 681 writeShuffleValue<e>(loc, val, 16, 1); 682 break; 683 case R_MICROMIPS_PC18_S3: 684 checkInt(loc, val, 21, type); 685 writeShuffleValue<e>(loc, val, 18, 3); 686 break; 687 case R_MICROMIPS_PC19_S2: 688 checkInt(loc, val, 21, type); 689 writeShuffleValue<e>(loc, val, 19, 2); 690 break; 691 case R_MICROMIPS_PC21_S1: 692 checkInt(loc, val, 22, type); 693 writeShuffleValue<e>(loc, val, 21, 1); 694 break; 695 case R_MICROMIPS_PC23_S2: 696 checkInt(loc, val, 25, type); 697 writeShuffleValue<e>(loc, val, 23, 2); 698 break; 699 default: 700 llvm_unreachable("unknown relocation"); 701 } 702 } 703 704 template <class ELFT> bool MIPS<ELFT>::usesOnlyLowPageBits(RelType type) const { 705 return type == R_MIPS_LO16 || type == R_MIPS_GOT_OFST || 706 type == R_MICROMIPS_LO16; 707 } 708 709 // Return true if the symbol is a PIC function. 710 template <class ELFT> bool elf::isMipsPIC(const Defined *sym) { 711 if (!sym->isFunc()) 712 return false; 713 714 if (sym->stOther & STO_MIPS_PIC) 715 return true; 716 717 if (!sym->section) 718 return false; 719 720 ObjFile<ELFT> *file = 721 cast<InputSectionBase>(sym->section)->template getFile<ELFT>(); 722 if (!file) 723 return false; 724 725 return file->getObj().getHeader()->e_flags & EF_MIPS_PIC; 726 } 727 728 template <class ELFT> TargetInfo *elf::getMipsTargetInfo() { 729 static MIPS<ELFT> target; 730 return ⌖ 731 } 732 733 template TargetInfo *elf::getMipsTargetInfo<ELF32LE>(); 734 template TargetInfo *elf::getMipsTargetInfo<ELF32BE>(); 735 template TargetInfo *elf::getMipsTargetInfo<ELF64LE>(); 736 template TargetInfo *elf::getMipsTargetInfo<ELF64BE>(); 737 738 template bool elf::isMipsPIC<ELF32LE>(const Defined *); 739 template bool elf::isMipsPIC<ELF32BE>(const Defined *); 740 template bool elf::isMipsPIC<ELF64LE>(const Defined *); 741 template bool elf::isMipsPIC<ELF64BE>(const Defined *); 742