1 //===-- Compile time cpu feature detection ----------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // This file lists target cpu features by introspecting compiler enabled 9 // preprocessor definitions. 10 //===----------------------------------------------------------------------===// 11 12 #ifndef LLVM_LIBC_SRC___SUPPORT_MACROS_PROPERTIES_CPU_FEATURES_H 13 #define LLVM_LIBC_SRC___SUPPORT_MACROS_PROPERTIES_CPU_FEATURES_H 14 15 #include "architectures.h" 16 17 #if defined(__ARM_FEATURE_FP16_SCALAR_ARITHMETIC) 18 #define LIBC_TARGET_CPU_HAS_FULLFP16 19 #endif 20 21 #if defined(__SSE2__) 22 #define LIBC_TARGET_CPU_HAS_SSE2 23 #define LIBC_TARGET_CPU_HAS_FPU_FLOAT 24 #define LIBC_TARGET_CPU_HAS_FPU_DOUBLE 25 #endif 26 27 #if defined(__SSE4_2__) 28 #define LIBC_TARGET_CPU_HAS_SSE4_2 29 #endif 30 31 #if defined(__AVX__) 32 #define LIBC_TARGET_CPU_HAS_AVX 33 #endif 34 35 #if defined(__AVX2__) 36 #define LIBC_TARGET_CPU_HAS_AVX2 37 #endif 38 39 #if defined(__AVX512F__) 40 #define LIBC_TARGET_CPU_HAS_AVX512F 41 #endif 42 43 #if defined(__AVX512BW__) 44 #define LIBC_TARGET_CPU_HAS_AVX512BW 45 #endif 46 47 #if defined(__ARM_FP) 48 #if (__ARM_FP & 0x2) 49 #define LIBC_TARGET_CPU_HAS_ARM_FPU_HALF 50 #define LIBC_TARGET_CPU_HAS_FPU_HALF 51 #endif // LIBC_TARGET_CPU_HAS_ARM_FPU_HALF 52 #if (__ARM_FP & 0x4) 53 #define LIBC_TARGET_CPU_HAS_ARM_FPU_FLOAT 54 #define LIBC_TARGET_CPU_HAS_FPU_FLOAT 55 #endif // LIBC_TARGET_CPU_HAS_ARM_FPU_FLOAT 56 #if (__ARM_FP & 0x8) 57 #define LIBC_TARGET_CPU_HAS_ARM_FPU_DOUBLE 58 #define LIBC_TARGET_CPU_HAS_FPU_DOUBLE 59 #endif // LIBC_TARGET_CPU_HAS_ARM_FPU_DOUBLE 60 #endif // __ARM_FP 61 62 #if defined(__riscv_flen) 63 // https://github.com/riscv-non-isa/riscv-c-api-doc/blob/main/src/c-api.adoc 64 #if defined(__riscv_zfhmin) 65 #define LIBC_TARGET_CPU_HAS_RISCV_FPU_HALF 66 #define LIBC_TARGET_CPU_HAS_FPU_HALF 67 #endif // LIBC_TARGET_CPU_HAS_RISCV_FPU_HALF 68 #if (__riscv_flen >= 32) 69 #define LIBC_TARGET_CPU_HAS_RISCV_FPU_FLOAT 70 #define LIBC_TARGET_CPU_HAS_FPU_FLOAT 71 #endif // LIBC_TARGET_CPU_HAS_RISCV_FPU_FLOAT 72 #if (__riscv_flen >= 64) 73 #define LIBC_TARGET_CPU_HAS_RISCV_FPU_DOUBLE 74 #define LIBC_TARGET_CPU_HAS_FPU_DOUBLE 75 #endif // LIBC_TARGET_CPU_HAS_RISCV_FPU_DOUBLE 76 #endif // __riscv_flen 77 78 #if defined(__NVPTX__) || defined(__AMDGPU__) 79 #define LIBC_TARGET_CPU_HAS_FPU_FLOAT 80 #define LIBC_TARGET_CPU_HAS_FPU_DOUBLE 81 #endif 82 83 #if defined(__ARM_FEATURE_FMA) || (defined(__AVX2__) && defined(__FMA__)) || \ 84 defined(__NVPTX__) || defined(__AMDGPU__) || defined(__LIBC_RISCV_USE_FMA) 85 #define LIBC_TARGET_CPU_HAS_FMA 86 // Provide a more fine-grained control of FMA instruction for ARM targets. 87 #if defined(LIBC_TARGET_CPU_HAS_FPU_HALF) 88 #define LIBC_TARGET_CPU_HAS_FMA_HALF 89 #endif // LIBC_TARGET_CPU_HAS_FMA_HALF 90 #if defined(LIBC_TARGET_CPU_HAS_FPU_FLOAT) 91 #define LIBC_TARGET_CPU_HAS_FMA_FLOAT 92 #endif // LIBC_TARGET_CPU_HAS_FMA_FLOAT 93 #if defined(LIBC_TARGET_CPU_HAS_FPU_DOUBLE) 94 #define LIBC_TARGET_CPU_HAS_FMA_DOUBLE 95 #endif // LIBC_TARGET_CPU_HAS_FMA_DOUBLE 96 #endif 97 98 #if defined(LIBC_TARGET_ARCH_IS_AARCH64) || \ 99 (defined(LIBC_TARGET_ARCH_IS_X86_64) && \ 100 defined(LIBC_TARGET_CPU_HAS_SSE4_2)) 101 #define LIBC_TARGET_CPU_HAS_NEAREST_INT 102 #endif 103 104 #if defined(LIBC_TARGET_ARCH_IS_AARCH64) || defined(LIBC_TARGET_ARCH_IS_GPU) 105 #define LIBC_TARGET_CPU_HAS_FAST_FLOAT16_OPS 106 #endif 107 108 #endif // LLVM_LIBC_SRC___SUPPORT_MACROS_PROPERTIES_CPU_FEATURES_H 109