1 /*
2 * Double-precision vector e^x function.
3 *
4 * Copyright (c) 2023-2025, Arm Limited.
5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
6 */
7
8 #include "sv_math.h"
9 #include "test_sig.h"
10 #include "test_defs.h"
11
12 static const struct data
13 {
14 double c0, c2;
15 double c1, c3;
16 double ln2_hi, ln2_lo, inv_ln2, shift, thres;
17
18 } data = {
19 .c0 = 0x1.fffffffffdbcdp-2,
20 .c1 = 0x1.555555555444cp-3,
21 .c2 = 0x1.555573c6a9f7dp-5,
22 .c3 = 0x1.1111266d28935p-7,
23 .ln2_hi = 0x1.62e42fefa3800p-1,
24 .ln2_lo = 0x1.ef35793c76730p-45,
25 /* 1/ln2. */
26 .inv_ln2 = 0x1.71547652b82fep+0,
27 /* 1.5*2^46+1023. This value is further explained below. */
28 .shift = 0x1.800000000ffc0p+46,
29 .thres = 704.0,
30 };
31
32 #define SpecialOffset 0x6000000000000000 /* 0x1p513. */
33 /* SpecialBias1 + SpecialBias1 = asuint(1.0). */
34 #define SpecialBias1 0x7000000000000000 /* 0x1p769. */
35 #define SpecialBias2 0x3010000000000000 /* 0x1p-254. */
36
37 /* Update of both special and non-special cases, if any special case is
38 detected. */
39 static inline svfloat64_t
special_case(svbool_t pg,svfloat64_t s,svfloat64_t y,svfloat64_t n)40 special_case (svbool_t pg, svfloat64_t s, svfloat64_t y, svfloat64_t n)
41 {
42 /* s=2^n may overflow, break it up into s=s1*s2,
43 such that exp = s + s*y can be computed as s1*(s2+s2*y)
44 and s1*s1 overflows only if n>0. */
45
46 /* If n<=0 then set b to 0x6, 0 otherwise. */
47 svbool_t p_sign = svcmple (pg, n, 0.0); /* n <= 0. */
48 svuint64_t b
49 = svdup_u64_z (p_sign, SpecialOffset); /* Inactive lanes set to 0. */
50
51 /* Set s1 to generate overflow depending on sign of exponent n,
52 ie. s1 = 0x70...0 - b. */
53 svfloat64_t s1 = svreinterpret_f64 (svsubr_x (pg, b, SpecialBias1));
54 /* Offset s to avoid overflow in final result if n is below threshold.
55 ie. s2 = as_u64 (s) - 0x3010...0 + b. */
56 svfloat64_t s2 = svreinterpret_f64 (
57 svadd_x (pg, svsub_x (pg, svreinterpret_u64 (s), SpecialBias2), b));
58
59 /* |n| > 1280 => 2^(n) overflows. */
60 svbool_t p_cmp = svacgt (pg, n, 1280.0);
61
62 svfloat64_t r1 = svmul_x (svptrue_b64 (), s1, s1);
63 svfloat64_t r2 = svmla_x (pg, s2, s2, y);
64 svfloat64_t r0 = svmul_x (svptrue_b64 (), r2, s1);
65
66 return svsel (p_cmp, r1, r0);
67 }
68
69 /* SVE exp algorithm. Maximum measured error is 1.01ulps:
70 SV_NAME_D1 (exp)(0x1.4619d7b04da41p+6) got 0x1.885d9acc41da7p+117
71 want 0x1.885d9acc41da6p+117. */
SV_NAME_D1(exp)72 svfloat64_t SV_NAME_D1 (exp) (svfloat64_t x, const svbool_t pg)
73 {
74 const struct data *d = ptr_barrier (&data);
75
76 svbool_t special = svacgt (pg, x, d->thres);
77
78 /* Use a modifed version of the shift used for flooring, such that x/ln2 is
79 rounded to a multiple of 2^-6=1/64, shift = 1.5 * 2^52 * 2^-6 = 1.5 *
80 2^46.
81
82 n is not an integer but can be written as n = m + i/64, with i and m
83 integer, 0 <= i < 64 and m <= n.
84
85 Bits 5:0 of z will be null every time x/ln2 reaches a new integer value
86 (n=m, i=0), and is incremented every time z (or n) is incremented by 1/64.
87 FEXPA expects i in bits 5:0 of the input so it can be used as index into
88 FEXPA hardwired table T[i] = 2^(i/64) for i = 0:63, that will in turn
89 populate the mantissa of the output. Therefore, we use u=asuint(z) as
90 input to FEXPA.
91
92 We add 1023 to the modified shift value in order to set bits 16:6 of u to
93 1, such that once these bits are moved to the exponent of the output of
94 FEXPA, we get the exponent of 2^n right, i.e. we get 2^m. */
95 svfloat64_t z = svmla_x (pg, sv_f64 (d->shift), x, d->inv_ln2);
96 svuint64_t u = svreinterpret_u64 (z);
97 svfloat64_t n = svsub_x (pg, z, d->shift);
98 svfloat64_t c13 = svld1rq (svptrue_b64 (), &d->c1);
99 /* r = x - n * ln2, r is in [-ln2/(2N), ln2/(2N)]. */
100 svfloat64_t ln2 = svld1rq (svptrue_b64 (), &d->ln2_hi);
101 svfloat64_t r = svmls_lane (x, n, ln2, 0);
102 r = svmls_lane (r, n, ln2, 1);
103
104 /* y = exp(r) - 1 ~= r + C0 r^2 + C1 r^3 + C2 r^4 + C3 r^5. */
105 svfloat64_t r2 = svmul_x (svptrue_b64 (), r, r);
106 svfloat64_t p01 = svmla_lane (sv_f64 (d->c0), r, c13, 0);
107 svfloat64_t p23 = svmla_lane (sv_f64 (d->c2), r, c13, 1);
108 svfloat64_t p04 = svmla_x (pg, p01, p23, r2);
109 svfloat64_t y = svmla_x (pg, r, p04, r2);
110
111 /* s = 2^n, computed using FEXPA. FEXPA does not propagate NaNs, so for
112 consistent NaN handling we have to manually propagate them. This comes at
113 significant performance cost. */
114 svfloat64_t s = svexpa (u);
115
116 /* Assemble result as exp(x) = 2^n * exp(r). If |x| > Thresh the
117 multiplication may overflow, so use special case routine. */
118
119 if (unlikely (svptest_any (pg, special)))
120 {
121 /* FEXPA zeroes the sign bit, however the sign is meaningful to the
122 special case function so needs to be copied.
123 e = sign bit of u << 46. */
124 svuint64_t e = svand_x (pg, svlsl_x (pg, u, 46), 0x8000000000000000);
125 /* Copy sign to s. */
126 s = svreinterpret_f64 (svadd_x (pg, e, svreinterpret_u64 (s)));
127 return special_case (pg, s, y, n);
128 }
129
130 /* No special case. */
131 return svmla_x (pg, s, s, y);
132 }
133
134 TEST_SIG (SV, D, 1, exp, -9.9, 9.9)
135 TEST_ULP (SV_NAME_D1 (exp), 1.46)
136 TEST_DISABLE_FENV (SV_NAME_D1 (exp))
137 TEST_SYM_INTERVAL (SV_NAME_D1 (exp), 0, 0x1p-23, 40000)
138 TEST_SYM_INTERVAL (SV_NAME_D1 (exp), 0x1p-23, 1, 50000)
139 TEST_SYM_INTERVAL (SV_NAME_D1 (exp), 1, 0x1p23, 50000)
140 TEST_SYM_INTERVAL (SV_NAME_D1 (exp), 0x1p23, inf, 50000)
141 CLOSE_SVE_ATTR
142