xref: /freebsd/contrib/arm-optimized-routines/math/aarch64/advsimd/cosf.c (revision f3087bef11543b42e0d69b708f367097a4118d24)
1 /*
2  * Single-precision vector cos function.
3  *
4  * Copyright (c) 2019-2024, Arm Limited.
5  * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
6  */
7 
8 #include "mathlib.h"
9 #include "v_math.h"
10 #include "test_defs.h"
11 #include "test_sig.h"
12 
13 static const struct data
14 {
15   float32x4_t poly[4];
16   float32x4_t range_val, inv_pi, pi_1, pi_2, pi_3;
17 } data = {
18   /* 1.886 ulp error.  */
19   .poly = { V4 (-0x1.555548p-3f), V4 (0x1.110df4p-7f), V4 (-0x1.9f42eap-13f),
20 	    V4 (0x1.5b2e76p-19f) },
21 
22   .pi_1 = V4 (0x1.921fb6p+1f),
23   .pi_2 = V4 (-0x1.777a5cp-24f),
24   .pi_3 = V4 (-0x1.ee59dap-49f),
25 
26   .inv_pi = V4 (0x1.45f306p-2f),
27   .range_val = V4 (0x1p20f)
28 };
29 
30 #define C(i) d->poly[i]
31 
32 static float32x4_t VPCS_ATTR NOINLINE
special_case(float32x4_t x,float32x4_t y,uint32x4_t odd,uint32x4_t cmp)33 special_case (float32x4_t x, float32x4_t y, uint32x4_t odd, uint32x4_t cmp)
34 {
35   /* Fall back to scalar code.  */
36   y = vreinterpretq_f32_u32 (veorq_u32 (vreinterpretq_u32_f32 (y), odd));
37   return v_call_f32 (cosf, x, y, cmp);
38 }
39 
V_NAME_F1(cos)40 float32x4_t VPCS_ATTR NOINLINE V_NAME_F1 (cos) (float32x4_t x)
41 {
42   const struct data *d = ptr_barrier (&data);
43   float32x4_t n, r, r2, r3, y;
44   uint32x4_t odd, cmp;
45 
46 #if WANT_SIMD_EXCEPT
47   r = vabsq_f32 (x);
48   cmp = vcgeq_u32 (vreinterpretq_u32_f32 (r),
49 		   vreinterpretq_u32_f32 (d->range_val));
50   if (unlikely (v_any_u32 (cmp)))
51     /* If fenv exceptions are to be triggered correctly, set any special lanes
52        to 1 (which is neutral w.r.t. fenv). These lanes will be fixed by
53        special-case handler later.  */
54     r = vbslq_f32 (cmp, v_f32 (1.0f), r);
55 #else
56   cmp = vcageq_f32 (x, d->range_val);
57   r = x;
58 #endif
59 
60   /* n = rint((|x|+pi/2)/pi) - 0.5.  */
61   n = vrndaq_f32 (vfmaq_f32 (v_f32 (0.5), r, d->inv_pi));
62   odd = vshlq_n_u32 (vreinterpretq_u32_s32 (vcvtq_s32_f32 (n)), 31);
63   n = vsubq_f32 (n, v_f32 (0.5f));
64 
65   /* r = |x| - n*pi  (range reduction into -pi/2 .. pi/2).  */
66   r = vfmsq_f32 (r, d->pi_1, n);
67   r = vfmsq_f32 (r, d->pi_2, n);
68   r = vfmsq_f32 (r, d->pi_3, n);
69 
70   /* y = sin(r).  */
71   r2 = vmulq_f32 (r, r);
72   r3 = vmulq_f32 (r2, r);
73   y = vfmaq_f32 (C (2), C (3), r2);
74   y = vfmaq_f32 (C (1), y, r2);
75   y = vfmaq_f32 (C (0), y, r2);
76   y = vfmaq_f32 (r, y, r3);
77 
78   if (unlikely (v_any_u32 (cmp)))
79     return special_case (x, y, odd, cmp);
80   return vreinterpretq_f32_u32 (veorq_u32 (vreinterpretq_u32_f32 (y), odd));
81 }
82 
83 HALF_WIDTH_ALIAS_F1 (cos)
84 
85 TEST_SIG (V, F, 1, cos, -3.1, 3.1)
86 TEST_ULP (V_NAME_F1 (cos), 1.4)
87 TEST_DISABLE_FENV_IF_NOT (V_NAME_F1 (cos), WANT_SIMD_EXCEPT)
88 TEST_SYM_INTERVAL (V_NAME_F1 (cos), 0, 0x1p20, 500000)
89 TEST_SYM_INTERVAL (V_NAME_F1 (cos), 0x1p20, inf, 10000)
90