1 /*
2 * Single-precision vector atanh(x) function.
3 *
4 * Copyright (c) 2022-2024, Arm Limited.
5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
6 */
7
8 #include "v_math.h"
9 #include "test_sig.h"
10 #include "test_defs.h"
11 #include "v_log1pf_inline.h"
12
13 const static struct data
14 {
15 struct v_log1pf_data log1pf_consts;
16 uint32x4_t one;
17 #if WANT_SIMD_EXCEPT
18 uint32x4_t tiny_bound;
19 #endif
20 } data = {
21 .log1pf_consts = V_LOG1PF_CONSTANTS_TABLE,
22 .one = V4 (0x3f800000),
23 #if WANT_SIMD_EXCEPT
24 /* 0x1p-12, below which atanhf(x) rounds to x. */
25 .tiny_bound = V4 (0x39800000),
26 #endif
27 };
28
29 #define AbsMask v_u32 (0x7fffffff)
30 #define Half v_u32 (0x3f000000)
31
32 static float32x4_t NOINLINE VPCS_ATTR
special_case(float32x4_t x,float32x4_t halfsign,float32x4_t y,uint32x4_t special)33 special_case (float32x4_t x, float32x4_t halfsign, float32x4_t y,
34 uint32x4_t special)
35 {
36 return v_call_f32 (atanhf, vbslq_f32 (AbsMask, x, halfsign),
37 vmulq_f32 (halfsign, y), special);
38 }
39
40 /* Approximation for vector single-precision atanh(x) using modified log1p.
41 The maximum error is 2.93 ULP:
42 _ZGVnN4v_atanhf(0x1.f43d7p-5) got 0x1.f4dcfep-5
43 want 0x1.f4dcf8p-5. */
V_NAME_F1(atanh)44 float32x4_t VPCS_ATTR NOINLINE V_NAME_F1 (atanh) (float32x4_t x)
45 {
46 const struct data *d = ptr_barrier (&data);
47
48 float32x4_t halfsign = vbslq_f32 (AbsMask, v_f32 (0.5), x);
49 float32x4_t ax = vabsq_f32 (x);
50 uint32x4_t iax = vreinterpretq_u32_f32 (ax);
51
52 #if WANT_SIMD_EXCEPT
53 uint32x4_t special
54 = vorrq_u32 (vcgeq_u32 (iax, d->one), vcltq_u32 (iax, d->tiny_bound));
55 /* Side-step special cases by setting those lanes to 0, which will trigger no
56 exceptions. These will be fixed up later. */
57 if (unlikely (v_any_u32 (special)))
58 ax = v_zerofy_f32 (ax, special);
59 #else
60 uint32x4_t special = vcgeq_u32 (iax, d->one);
61 #endif
62
63 float32x4_t y = vdivq_f32 (vaddq_f32 (ax, ax),
64 vsubq_f32 (vreinterpretq_f32_u32 (d->one), ax));
65 y = log1pf_inline (y, &d->log1pf_consts);
66
67 /* If exceptions not required, pass ax to special-case for shorter dependency
68 chain. If exceptions are required ax will have been zerofied, so have to
69 pass x. */
70 if (unlikely (v_any_u32 (special)))
71 #if WANT_SIMD_EXCEPT
72 return special_case (x, halfsign, y, special);
73 #else
74 return special_case (ax, halfsign, y, special);
75 #endif
76 return vmulq_f32 (halfsign, y);
77 }
78
79 HALF_WIDTH_ALIAS_F1 (atanh)
80
81 TEST_SIG (V, F, 1, atanh, -1.0, 1.0)
82 TEST_ULP (V_NAME_F1 (atanh), 2.44)
83 TEST_DISABLE_FENV_IF_NOT (V_NAME_F1 (atanh), WANT_SIMD_EXCEPT)
84 TEST_SYM_INTERVAL (V_NAME_F1 (atanh), 0, 0x1p-12, 500)
85 TEST_SYM_INTERVAL (V_NAME_F1 (atanh), 0x1p-12, 1, 200000)
86 TEST_SYM_INTERVAL (V_NAME_F1 (atanh), 1, inf, 1000)
87 /* atanh is asymptotic at 1, which is the default control value - have to set
88 -c 0 specially to ensure fp exceptions are triggered correctly (choice of
89 control lane is irrelevant if fp exceptions are disabled). */
90 TEST_CONTROL_VALUE (V_NAME_F1 (atanh), 0)
91