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Searched refs:xcc_inst (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_mqd_manager.c112 int xcc_inst = inst + ffs(mm->dev->xcc_mask) - 1; in mqd_symmetrically_map_cu_mask() local
152 cu_info->bitmap[xcc_inst][se % 4][sh + (se / 4) * in mqd_symmetrically_map_cu_mask()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gc_9_4_3.c224 u32 pasid, unsigned int vmid, uint32_t xcc_inst) in kgd_gfx_v9_4_3_set_pasid_vmid_mapping() argument
228 unsigned int phy_inst = GET_INST(GC, xcc_inst); in kgd_gfx_v9_4_3_set_pasid_vmid_mapping()
262 * and the 4th is reserved. Therefore "aid * 4 + (xcc_inst % 2) + 1" in kgd_gfx_v9_4_3_set_pasid_vmid_mapping()
H A Dsdma_v7_1.c122 int xcc_inst = dev_inst % adev->sdma.num_inst_per_xcc; in sdma_v7_1_get_reg_offset() local
126 if (xcc_inst != 0) in sdma_v7_1_get_reg_offset()
127 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * xcc_inst; in sdma_v7_1_get_reg_offset()
130 if (xcc_inst != 0) in sdma_v7_1_get_reg_offset()
131 internal_offset += SDMA1_REG_OFFSET * xcc_inst; in sdma_v7_1_get_reg_offset()
H A Damdgpu_gmc.c880 uint32_t xcc_inst) in amdgpu_gmc_fw_reg_write_reg_wait()
882 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_inst]; in amdgpu_gmc_fw_reg_write_reg_wait()
888 if (adev->mes.ring[MES_PIPE_INST(xcc_inst, 0)].sched.ready) { in amdgpu_gmc_fw_reg_write_reg_wait()
890 ref, mask, xcc_inst); in amdgpu_gmc_fw_reg_write_reg_wait()
869 amdgpu_gmc_fw_reg_write_reg_wait(struct amdgpu_device * adev,uint32_t reg0,uint32_t reg1,uint32_t ref,uint32_t mask,uint32_t xcc_inst) amdgpu_gmc_fw_reg_write_reg_wait() argument
H A Damdgpu_gmc.h453 uint32_t xcc_inst);
H A Damdgpu_gfx.c513 int xcc_inst = ffs(adev->gfx.xcc_mask) - 1; in amdgpu_gfx_mqd_symmetrically_map_cu_mask() local
519 if (xcc_inst < 0) in amdgpu_gfx_mqd_symmetrically_map_cu_mask()
520 xcc_inst = 0; in amdgpu_gfx_mqd_symmetrically_map_cu_mask()
533 cu_info->bitmap[xcc_inst][se % 4][sh + (se / 4) * in amdgpu_gfx_mqd_symmetrically_map_cu_mask()