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Searched refs:writel_relaxed (Results 1 – 25 of 457) sorted by relevance

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/linux/drivers/gpu/drm/meson/
H A Dmeson_vpp.c59 writel_relaxed(is_horizontal ? VPP_SCALE_HORIZONTAL_COEF : 0, in meson_vpp_write_scaling_filter_coefs()
62 writel_relaxed(coefs[i], in meson_vpp_write_scaling_filter_coefs()
84 writel_relaxed(is_horizontal ? VPP_SCALE_HORIZONTAL_COEF : 0, in meson_vpp_write_vd_scaling_filter_coefs()
87 writel_relaxed(coefs[i], in meson_vpp_write_vd_scaling_filter_coefs()
95 writel_relaxed(0x108080, priv->io_base + _REG(VPP_DUMMY_DATA1)); in meson_vpp_init()
99 writel_relaxed(VPP_PPS_DUMMY_DATA_MODE, in meson_vpp_init()
101 writel_relaxed(0x1020080, in meson_vpp_init()
103 writel_relaxed(0x42020, in meson_vpp_init()
106 writel_relaxed(0xf, priv->io_base + _REG(DOLBY_PATH_CTRL)); in meson_vpp_init()
110 writel_relaxed(VPP_OFIFO_SIZE_DEFAULT, in meson_vpp_init()
[all …]
/linux/drivers/clocksource/
H A Dtimer-gx6605s.c30 writel_relaxed(GX6605S_STATUS_CLR, base + TIMER_STATUS); in gx6605s_timer_interrupt()
31 writel_relaxed(0, base + TIMER_INI); in gx6605s_timer_interrupt()
43 writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL); in gx6605s_timer_set_oneshot()
46 writel_relaxed(GX6605S_CONFIG_EN | GX6605S_CONFIG_IRQ_EN, in gx6605s_timer_set_oneshot()
58 writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL); in gx6605s_timer_set_next_event()
61 writel_relaxed(ULONG_MAX - delta, base + TIMER_INI); in gx6605s_timer_set_next_event()
62 writel_relaxed(GX6605S_CONTRL_START, base + TIMER_CONTRL); in gx6605s_timer_set_next_event()
71 writel_relaxed(0, base + TIMER_CONTRL); in gx6605s_timer_shutdown()
72 writel_relaxed(0, base + TIMER_CONFIG); in gx6605s_timer_shutdown()
105 writel_relaxed(0, base + TIMER_DIV); in gx6605s_clkevt_init()
[all …]
H A Dtimer-lpc32xx.c75 writel_relaxed(LPC32XX_TIMER_TCR_CRST, ddata->base + LPC32XX_TIMER_TCR); in lpc32xx_clkevt_next_event()
76 writel_relaxed(delta, ddata->base + LPC32XX_TIMER_MR0); in lpc32xx_clkevt_next_event()
77 writel_relaxed(LPC32XX_TIMER_TCR_CEN, ddata->base + LPC32XX_TIMER_TCR); in lpc32xx_clkevt_next_event()
88 writel_relaxed(0, ddata->base + LPC32XX_TIMER_TCR); in lpc32xx_clkevt_shutdown()
102 writel_relaxed(0, ddata->base + LPC32XX_TIMER_TCR); in lpc32xx_clkevt_oneshot()
105 writel_relaxed(LPC32XX_TIMER_MCR_MR0I | LPC32XX_TIMER_MCR_MR0R | in lpc32xx_clkevt_oneshot()
116 writel_relaxed(LPC32XX_TIMER_MCR_MR0I | LPC32XX_TIMER_MCR_MR0R, in lpc32xx_clkevt_periodic()
123 writel_relaxed(LPC32XX_TIMER_TCR_CRST, ddata->base + LPC32XX_TIMER_TCR); in lpc32xx_clkevt_periodic()
124 writel_relaxed(ddata->ticks_per_jiffy, ddata->base + LPC32XX_TIMER_MR0); in lpc32xx_clkevt_periodic()
125 writel_relaxed(LPC32XX_TIMER_TCR_CEN, ddata->base + LPC32XX_TIMER_TCR); in lpc32xx_clkevt_periodic()
[all …]
H A Dasm9260_timer.c113 writel_relaxed(delta, priv.base + HW_MR0); in asm9260_timer_set_next_event()
115 writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG); in asm9260_timer_set_next_event()
122 writel_relaxed(BM_C0_EN, priv.base + HW_TCR + CLR_REG); in __asm9260_timer_shutdown()
136 writel_relaxed(BM_MCR_RES_EN(0) | BM_MCR_STOP_EN(0), in asm9260_timer_set_oneshot()
146 writel_relaxed(BM_MCR_RES_EN(0) | BM_MCR_STOP_EN(0), in asm9260_timer_set_periodic()
149 writel_relaxed(priv.ticks_per_jiffy, priv.base + HW_MR0); in asm9260_timer_set_periodic()
151 writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG); in asm9260_timer_set_periodic()
173 writel_relaxed(BM_IR_MR0, priv.base + HW_IR); in asm9260_timer_interrupt()
218 writel_relaxed(BM_DIR_DEFAULT, priv.base + HW_DIR); in asm9260_timer_init()
220 writel_relaxed(BM_PR_DISABLE, priv.base + HW_PR); in asm9260_timer_init()
[all …]
H A Dtimer-imx-gpt.c99 writel_relaxed(tmp & ~MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL); in imx1_gpt_irq_disable()
104 writel_relaxed(0, imxtm->base + V2_IR); in imx31_gpt_irq_disable()
112 writel_relaxed(tmp | MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL); in imx1_gpt_irq_enable()
117 writel_relaxed(1<<0, imxtm->base + V2_IR); in imx31_gpt_irq_enable()
122 writel_relaxed(0, imxtm->base + MX1_2_TSTAT); in imx1_gpt_irq_acknowledge()
127 writel_relaxed(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, in imx21_gpt_irq_acknowledge()
133 writel_relaxed(V2_TSTAT_OF1, imxtm->base + V2_TSTAT); in imx31_gpt_irq_acknowledge()
180 writel_relaxed(tcmp, imxtm->base + MX1_2_TCMP); in mx1_2_set_next_event()
194 writel_relaxed(tcmp, imxtm->base + V2_TCMP); in v2_set_next_event()
211 writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp); in mxc_shutdown()
[all …]
H A Dtimer-davinci.c82 writel_relaxed(val, clockevent->base + reg); in davinci_clockevent_write()
99 writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR); in davinci_tim12_shutdown()
112 writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR); in davinci_tim12_set_oneshot()
205 writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM34); in davinci_clocksource_init_tim34()
206 writel_relaxed(UINT_MAX, base + DAVINCI_TIMER_REG_PRD34); in davinci_clocksource_init_tim34()
207 writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR); in davinci_clocksource_init_tim34()
222 writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM12); in davinci_clocksource_init_tim12()
223 writel_relaxed(UINT_MAX, base + DAVINCI_TIMER_REG_PRD12); in davinci_clocksource_init_tim12()
224 writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR); in davinci_clocksource_init_tim12()
230 writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TCR); in davinci_timer_init()
[all …]
H A Dtimer-milbeaut.c57 writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); in mlb_timer_interrupt()
71 writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); in mlb_evt_timer_start()
79 writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); in mlb_evt_timer_stop()
84 writel_relaxed(cnt, timer_of_base(to) + MLB_TMR_EVT_TMRLR1_OFS); in mlb_evt_timer_register_count()
129 writel_relaxed(val, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS); in mlb_config_clock_source()
130 writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR1_OFS); in mlb_config_clock_source()
131 writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR2_OFS); in mlb_config_clock_source()
133 writel_relaxed(val, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS); in mlb_config_clock_source()
139 writel_relaxed(0, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); in mlb_config_clock_event()
/linux/arch/arm/mach-hisi/
H A Dhotplug.c82 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2), in set_cpu_hi3620()
87 writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREEN); in set_cpu_hi3620()
92 writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS); in set_cpu_hi3620()
95 writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN); in set_cpu_hi3620()
99 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2), in set_cpu_hi3620()
106 writel_relaxed(val, ctrl_base + SCPERCTRL0); in set_cpu_hi3620()
111 writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS); in set_cpu_hi3620()
116 writel_relaxed(val, ctrl_base + SCPERCTRL0); in set_cpu_hi3620()
119 writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREDIS); in set_cpu_hi3620()
123 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2), in set_cpu_hi3620()
[all …]
/linux/drivers/perf/
H A Dqcom_l3_pmu.c203 writel_relaxed(gang, l3pmu->regs + L3_M_BC_GANG); in qcom_l3_cache__64bit_counter_start()
207 writel_relaxed(0, l3pmu->regs + L3_HML3_PM_EVCNTR(idx + 1)); in qcom_l3_cache__64bit_counter_start()
208 writel_relaxed(0, l3pmu->regs + L3_HML3_PM_EVCNTR(idx)); in qcom_l3_cache__64bit_counter_start()
214 writel_relaxed(EVSEL(0), l3pmu->regs + L3_HML3_PM_EVTYPE(idx + 1)); in qcom_l3_cache__64bit_counter_start()
215 writel_relaxed(EVSEL(evsel), l3pmu->regs + L3_HML3_PM_EVTYPE(idx)); in qcom_l3_cache__64bit_counter_start()
218 writel_relaxed(PMCNT_RESET, l3pmu->regs + L3_HML3_PM_CNTCTL(idx + 1)); in qcom_l3_cache__64bit_counter_start()
219 writel_relaxed(PMCNTENSET(idx + 1), l3pmu->regs + L3_M_BC_CNTENSET); in qcom_l3_cache__64bit_counter_start()
220 writel_relaxed(PMCNT_RESET, l3pmu->regs + L3_HML3_PM_CNTCTL(idx)); in qcom_l3_cache__64bit_counter_start()
221 writel_relaxed(PMCNTENSET(idx), l3pmu->regs + L3_M_BC_CNTENSET); in qcom_l3_cache__64bit_counter_start()
232 writel_relaxed(PMCNTENCLR(idx), l3pmu->regs + L3_M_BC_CNTENCLR); in qcom_l3_cache__64bit_counter_stop()
[all …]
/linux/drivers/thermal/
H A Dimx91_thermal.c87 writel_relaxed(val, tmu->base + IMX91_TMU_CTRL1 + REG_SET); in imx91_tmu_start()
96 writel_relaxed(IMX91_TMU_CTRL1_EN, tmu->base + reg); in imx91_tmu_enable()
129 writel_relaxed(IMX91_TMU_CTRL0_THR1_IE, tmu->base + IMX91_TMU_CTRL0 + REG_CLR); in imx91_tmu_set_trips()
132 writel_relaxed(IMX91_TMU_THR_CTRL01_THR1_MASK, tmu->base + IMX91_TMU_THR_CTRL01 + REG_CLR); in imx91_tmu_set_trips()
135 writel_relaxed(val, tmu->base + IMX91_TMU_THR_CTRL01 + REG_SET); in imx91_tmu_set_trips()
137 writel_relaxed(IMX91_TMU_STAT0_THR1_IF, tmu->base + IMX91_TMU_STAT0 + REG_CLR); in imx91_tmu_set_trips()
139 writel_relaxed(IMX91_TMU_CTRL0_THR1_IE, tmu->base + IMX91_TMU_CTRL0 + REG_SET); in imx91_tmu_set_trips()
161 writel_relaxed(trim1, tmu->base + IMX91_TMU_TRIM1); in imx91_init_from_nvmem_cells()
162 writel_relaxed(trim2, tmu->base + IMX91_TMU_TRIM2); in imx91_init_from_nvmem_cells()
186 writel_relaxed(IMX91_TMU_CTRL0_THR1_IE, tmu->base + IMX91_TMU_CTRL0 + REG_CLR); in imx91_tmu_alarm_irq()
[all …]
H A Drockchip_thermal.c716 writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, in rk_tsadcv2_initialize()
719 writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, in rk_tsadcv2_initialize()
722 writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD); in rk_tsadcv2_initialize()
723 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, in rk_tsadcv2_initialize()
725 writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME, in rk_tsadcv2_initialize()
727 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, in rk_tsadcv2_initialize()
757 writel_relaxed(TSADCV2_USER_INTER_PD_SOC, regs + in rk_tsadcv3_initialize()
760 writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, in rk_tsadcv3_initialize()
762 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, in rk_tsadcv3_initialize()
764 writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME, in rk_tsadcv3_initialize()
[all …]
/linux/drivers/mmc/host/
H A Dmmci_qcom_dml.c64 writel_relaxed(config, base + DML_CONFIG); in qcom_dma_start()
67 writel_relaxed(data->blksz, base + DML_PRODUCER_BAM_BLOCK_SIZE); in qcom_dma_start()
70 writel_relaxed(data->blocks * data->blksz, in qcom_dma_start()
75 writel_relaxed(config, base + DML_CONFIG); in qcom_dma_start()
77 writel_relaxed(1, base + DML_PRODUCER_START); in qcom_dma_start()
84 writel_relaxed(config, base + DML_CONFIG); in qcom_dma_start()
88 writel_relaxed(config, base + DML_CONFIG); in qcom_dma_start()
90 writel_relaxed(1, base + DML_CONSUMER_START); in qcom_dma_start()
141 writel_relaxed(1, base + DML_SW_RESET); in qcom_dma_setup()
162 writel_relaxed(config, base + DML_CONFIG); in qcom_dma_setup()
[all …]
/linux/arch/arm/mach-qcom/
H A Dplatsmp.c70 writel_relaxed(0, base + VDD_SC1_ARRAY_CLAMP_GFS_CTL); in scss_release_secondary()
71 writel_relaxed(0, base + SCSS_CPU1CORE_RESET); in scss_release_secondary()
72 writel_relaxed(3, base + SCSS_DBG_STATUS_CORE_PWRDUP); in scss_release_secondary()
171 writel_relaxed(0xA4, saw_reg + APCS_SAW2_VCTL); in kpssv1_release_secondary()
177 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
179 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
184 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
189 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
194 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
199 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
[all …]
/linux/drivers/rtc/
H A Drtc-rtd119x.c61 writel_relaxed(val, data->base + RTD_RTCCR); in rtd119x_rtc_reset()
76 writel_relaxed(0x5a, data->base + RTD_RTCEN); in rtd119x_rtc_set_enabled()
78 writel_relaxed(0, data->base + RTD_RTCEN); in rtd119x_rtc_set_enabled()
145 writel_relaxed((tm->tm_sec << 1) & RTD_RTCSEC_RTCSEC_MASK, data->base + RTD_RTCSEC); in rtd119x_rtc_set_time()
146 writel_relaxed(tm->tm_min & RTD_RTCMIN_RTCMIN_MASK, data->base + RTD_RTCMIN); in rtd119x_rtc_set_time()
147 writel_relaxed(tm->tm_hour & RTD_RTCHR_RTCHR_MASK, data->base + RTD_RTCHR); in rtd119x_rtc_set_time()
148 writel_relaxed(day & RTD_RTCDATE1_RTCDATE1_MASK, data->base + RTD_RTCDATE1); in rtd119x_rtc_set_time()
149 writel_relaxed((day >> 8) & RTD_RTCDATE2_RTCDATE2_MASK, data->base + RTD_RTCDATE2); in rtd119x_rtc_set_time()
195 writel_relaxed(RTD_RTCACR_RTCPWR, data->base + RTD_RTCACR); in rtd119x_rtc_probe()
199 writel_relaxed(0, data->base + RTD_RTCMIN); in rtd119x_rtc_probe()
[all …]
H A Drtc-sa1100.c55 writel_relaxed(0, info->rtsr); in sa1100_rtc_interrupt()
62 writel_relaxed((RTSR_AL | RTSR_HZ) & (rtsr >> 2), info->rtsr); in sa1100_rtc_interrupt()
71 writel_relaxed(RTSR_AL | RTSR_HZ, info->rtsr); in sa1100_rtc_interrupt()
77 writel_relaxed(rtsr & (RTSR_ALE | RTSR_HZE), info->rtsr); in sa1100_rtc_interrupt()
103 writel_relaxed(rtsr, info->rtsr); in sa1100_rtc_alarm_irq_enable()
120 writel_relaxed(rtc_tm_to_time64(tm), info->rcnr); in sa1100_rtc_set_time()
141 writel_relaxed(readl_relaxed(info->rtsr) & in sa1100_rtc_set_alarm()
143 writel_relaxed(rtc_tm_to_time64(&alrm->time), info->rtar); in sa1100_rtc_set_alarm()
145 writel_relaxed(readl_relaxed(info->rtsr) | RTSR_ALE, info->rtsr); in sa1100_rtc_set_alarm()
147 writel_relaxed(readl_relaxed(info->rtsr) & ~RTSR_ALE, info->rtsr); in sa1100_rtc_set_alarm()
[all …]
/linux/drivers/net/ethernet/hisilicon/
H A Dhix5hd2_gmac.c316 writel_relaxed(val, priv->ctrl_base); in hix5hd2_config_port()
319 writel_relaxed(BIT_MODE_CHANGE_EN, priv->base + MODE_CHANGE_EN); in hix5hd2_config_port()
326 writel_relaxed(val, priv->base + PORT_MODE); in hix5hd2_config_port()
327 writel_relaxed(0, priv->base + MODE_CHANGE_EN); in hix5hd2_config_port()
328 writel_relaxed(duplex, priv->base + MAC_DUPLEX_HALF_CTRL); in hix5hd2_config_port()
333 writel_relaxed(BITS_RX_FQ_DEPTH_EN, priv->base + RX_FQ_REG_EN); in hix5hd2_set_desc_depth()
334 writel_relaxed(rx << 3, priv->base + RX_FQ_DEPTH); in hix5hd2_set_desc_depth()
335 writel_relaxed(0, priv->base + RX_FQ_REG_EN); in hix5hd2_set_desc_depth()
337 writel_relaxed(BITS_RX_BQ_DEPTH_EN, priv->base + RX_BQ_REG_EN); in hix5hd2_set_desc_depth()
338 writel_relaxed(rx << 3, priv->base + RX_BQ_DEPTH); in hix5hd2_set_desc_depth()
[all …]
/linux/drivers/irqchip/
H A Dirq-sa11x0.c40 writel_relaxed(reg, iobase + ICMR); in sa1100_mask_irq()
49 writel_relaxed(reg, iobase + ICMR); in sa1100_unmask_irq()
100 writel_relaxed(st->icmr & 0xfffff000, iobase + ICMR); in sa1100irq_suspend()
110 writel_relaxed(st->iccr, iobase + ICCR); in sa1100irq_resume()
111 writel_relaxed(st->iclr, iobase + ICLR); in sa1100irq_resume()
113 writel_relaxed(st->icmr, iobase + ICMR); in sa1100irq_resume()
158 writel_relaxed(0, iobase + ICMR); in sa11x0_init_irq_nodt()
161 writel_relaxed(0, iobase + ICLR); in sa11x0_init_irq_nodt()
167 writel_relaxed(1, iobase + ICCR); in sa11x0_init_irq_nodt()
H A Dirq-gic-common.c82 writel_relaxed(val, base + confoff); in gic_configure_irq()
99 writel_relaxed(GICD_INT_ACTLOW_LVLTRIG, in gic_dist_config()
106 writel_relaxed(REPEAT_BYTE_U32(priority), in gic_dist_config()
114 writel_relaxed(GICD_INT_EN_CLR_X32, in gic_dist_config()
116 writel_relaxed(GICD_INT_EN_CLR_X32, in gic_dist_config()
130 writel_relaxed(GICD_INT_EN_CLR_X32, in gic_cpu_config()
132 writel_relaxed(GICD_INT_EN_CLR_X32, in gic_cpu_config()
140 writel_relaxed(REPEAT_BYTE_U32(priority), in gic_cpu_config()
H A Dirq-tegra.c88 writel_relaxed(mask, base + reg); in tegra_ictlr_write_mask()
151 writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_COP_IER_CLR); in tegra_ictlr_suspend()
154 writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_CPU_IER_CLR); in tegra_ictlr_suspend()
157 writel_relaxed(lic->ictlr_wake_mask[i], ictlr + ICTLR_CPU_IER_SET); in tegra_ictlr_suspend()
173 writel_relaxed(lic->cpu_iep[i], in tegra_ictlr_resume()
175 writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_CPU_IER_CLR); in tegra_ictlr_resume()
176 writel_relaxed(lic->cpu_ier[i], in tegra_ictlr_resume()
178 writel_relaxed(lic->cop_iep[i], in tegra_ictlr_resume()
180 writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_COP_IER_CLR); in tegra_ictlr_resume()
181 writel_relaxed(lic->cop_ier[i], in tegra_ictlr_resume()
[all …]
/linux/drivers/i2c/busses/
H A Di2c-st.c201 writel_relaxed(readl_relaxed(reg) | mask, reg); in st_i2c_set_bits()
206 writel_relaxed(readl_relaxed(reg) & ~mask, reg); in st_i2c_clr_bits()
282 writel_relaxed(val, i2c_dev->base + SSC_CLR); in st_i2c_hw_config()
286 writel_relaxed(val, i2c_dev->base + SSC_CTL); in st_i2c_hw_config()
293 writel_relaxed(val, i2c_dev->base + SSC_BRG); in st_i2c_hw_config()
296 writel_relaxed(1, i2c_dev->base + SSC_PRE_SCALER_BRG); in st_i2c_hw_config()
299 writel_relaxed(SSC_I2C_I2CM, i2c_dev->base + SSC_I2C); in st_i2c_hw_config()
303 writel_relaxed(val, i2c_dev->base + SSC_REP_START_HOLD); in st_i2c_hw_config()
307 writel_relaxed(val, i2c_dev->base + SSC_REP_START_SETUP); in st_i2c_hw_config()
311 writel_relaxed(val, i2c_dev->base + SSC_START_HOLD); in st_i2c_hw_config()
[all …]
/linux/drivers/clk/tegra/
H A Dclk-tegra210.c525 writel_relaxed(value, clk_base + PLLE_MISC0); in tegra210_plle_hw_sequence_start()
530 writel_relaxed(value, clk_base + PLLE_AUX); in tegra210_plle_hw_sequence_start()
535 writel_relaxed(value, clk_base + PLLE_AUX); in tegra210_plle_hw_sequence_start()
552 writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0); in tegra210_xusb_pll_hw_control_enable()
562 writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0); in tegra210_xusb_pll_hw_sequence_start()
574 writel_relaxed(val, clk_base + SATA_PLL_CFG0); in tegra210_sata_pll_hw_control_enable()
584 writel_relaxed(val, clk_base + SATA_PLL_CFG0); in tegra210_sata_pll_hw_sequence_start()
604 writel_relaxed(val, clk_base + SATA_PLL_CFG0); in tegra210_set_sata_pll_seq_sw()
613 writel_relaxed(CLK_OUT_ENB_X_CLK_ENB_EMC_DLL, clk_base + offset); in tegra210_clk_emc_dll_enable()
619 writel_relaxed(emc_dll_src_value, clk_base + CLK_SOURCE_EMC_DLL); in tegra210_clk_emc_dll_update_setting()
[all …]
/linux/arch/arm/mach-imx/
H A Dgpc.c36 writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) | in imx_gpc_set_arm_power_up_timing()
42 writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) | in imx_gpc_set_arm_power_down_timing()
48 writel_relaxed(power_off, gpc_base + GPC_PGC_CPU_PDN); in imx_gpc_set_arm_power_in_lpm()
59 writel_relaxed(val, gpc_base + GPC_CNTR); in imx_gpc_set_l2_mem_power_in_lpm()
73 writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4); in imx_gpc_pre_suspend()
86 writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4); in imx_gpc_post_resume()
112 writel_relaxed(~0, reg_imr1 + i * 4); in imx_gpc_mask_all()
122 writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4); in imx_gpc_restore_all()
133 writel_relaxed(val, reg); in imx_gpc_hwirq_unmask()
144 writel_relaxed(val, reg); in imx_gpc_hwirq_mask()
[all …]
/linux/drivers/dma/
H A Darm-dma350.c301 writel_relaxed(CH_CMD_PAUSE, dch->base + CH_CMD); in d350_pause()
316 writel_relaxed(CH_CMD_RESUME, dch->base + CH_CMD); in d350_resume()
349 writel_relaxed(CH_CMD_STOP, dch->base + CH_CMD); in d350_terminate_all()
421 writel_relaxed(*reg++, dch->base + CH_INTREN); in d350_start_next()
423 writel_relaxed(*reg++, dch->base + CH_CTRL); in d350_start_next()
425 writel_relaxed(*reg++, dch->base + CH_SRCADDR); in d350_start_next()
427 writel_relaxed(*reg++, dch->base + CH_SRCADDRHI); in d350_start_next()
429 writel_relaxed(*reg++, dch->base + CH_DESADDR); in d350_start_next()
431 writel_relaxed(*reg++, dch->base + CH_DESADDRHI); in d350_start_next()
433 writel_relaxed(*reg++, dch->base + CH_XSIZE); in d350_start_next()
[all …]
/linux/arch/arm/mach-omap2/
H A Domap4-common.c83 writel_relaxed(0, dram_sync); in omap4_mb()
118 writel_relaxed(readl_relaxed(dram_sync), dram_sync); in omap_interconnect_sync()
119 writel_relaxed(readl_relaxed(sram_sync), sram_sync); in omap_interconnect_sync()
177 writel_relaxed(0x0, gic_dist_base_addr + GIC_DIST_CTRL); in gic_dist_disable()
183 writel_relaxed(0x1, gic_dist_base_addr + GIC_DIST_CTRL); in gic_dist_enable()
203 writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT); in gic_timer_retrigger()
205 writel_relaxed(1, twd_base + TWD_TIMER_COUNTER); in gic_timer_retrigger()
207 writel_relaxed(twd_ctrl, twd_base + TWD_TIMER_CONTROL); in gic_timer_retrigger()
/linux/drivers/pinctrl/
H A Dpinctrl-at91.c405 writel_relaxed(mask, pio + PIO_IDR); in at91_mux_disable_interrupt()
416 writel_relaxed(mask, pio + PIO_PPDDR); in at91_mux_set_pullup()
418 writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR)); in at91_mux_set_pullup()
430 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); in at91_mux_set_output()
431 writel_relaxed(mask, pio + (is_on ? PIO_OER : PIO_ODR)); in at91_mux_set_output()
441 writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR)); in at91_mux_set_multidrive()
446 writel_relaxed(mask, pio + PIO_ASR); in at91_mux_set_A_periph()
451 writel_relaxed(mask, pio + PIO_BSR); in at91_mux_set_B_periph()
457 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, in at91_mux_pio3_set_A_periph()
459 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, in at91_mux_pio3_set_A_periph()
[all …]

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