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Searched refs:write_reg (Results 1 – 25 of 107) sorted by relevance

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/linux/drivers/staging/fbtft/
H A Dfb_bd663474.c31 write_reg(par, 0x000, 0x0001); /*oscillator 0: stop, 1: operation */ in init_display()
35 write_reg(par, 0x100, 0x0000); /* power supply setup */ in init_display()
36 write_reg(par, 0x101, 0x0000); in init_display()
37 write_reg(par, 0x102, 0x3110); in init_display()
38 write_reg(par, 0x103, 0xe200); in init_display()
39 write_reg(par, 0x110, 0x009d); in init_display()
40 write_reg(par, 0x111, 0x0022); in init_display()
41 write_reg(par, 0x100, 0x0120); in init_display()
44 write_reg(par, 0x100, 0x3120); in init_display()
47 write_reg(par, 0x001, 0x0100); in init_display()
[all …]
H A Dfb_upd161704.c31 write_reg(par, 0x0003, 0x0001); /* Soft reset */ in init_display()
34 write_reg(par, 0x003A, 0x0001); /*Oscillator 0: stop, 1: operation */ in init_display()
38 write_reg(par, 0x0024, 0x007B); /* amplitude setting */ in init_display()
40 write_reg(par, 0x0025, 0x003B); /* amplitude setting */ in init_display()
41 write_reg(par, 0x0026, 0x0034); /* amplitude setting */ in init_display()
43 write_reg(par, 0x0027, 0x0004); /* amplitude setting */ in init_display()
44 write_reg(par, 0x0052, 0x0025); /* circuit setting 1 */ in init_display()
46 write_reg(par, 0x0053, 0x0033); /* circuit setting 2 */ in init_display()
47 write_reg(par, 0x0061, 0x001C); /* adjustment V10 positive polarity */ in init_display()
49 write_reg(par, 0x0062, 0x002C); /* adjustment V9 negative polarity */ in init_display()
[all …]
H A Dfb_ili9320.c26 write_reg(par, 0x0000); in read_devicecode()
47 write_reg(par, 0x00E5, 0x8000); in init_display()
50 write_reg(par, 0x0000, 0x0001); in init_display()
53 write_reg(par, 0x0001, 0x0100); in init_display()
56 write_reg(par, 0x0002, 0x0700); in init_display()
59 write_reg(par, 0x0004, 0x0000); in init_display()
62 write_reg(par, 0x0008, 0x0202); in init_display()
65 write_reg(par, 0x0009, 0x0000); in init_display()
68 write_reg(par, 0x000A, 0x0000); in init_display()
71 write_reg(par, 0x000C, 0x0000); in init_display()
[all …]
H A Dfb_s6d1121.c33 write_reg(par, 0x0011, 0x2004); in init_display()
34 write_reg(par, 0x0013, 0xCC00); in init_display()
35 write_reg(par, 0x0015, 0x2600); in init_display()
36 write_reg(par, 0x0014, 0x252A); in init_display()
37 write_reg(par, 0x0012, 0x0033); in init_display()
38 write_reg(par, 0x0013, 0xCC04); in init_display()
39 write_reg(par, 0x0013, 0xCC06); in init_display()
40 write_reg(par, 0x0013, 0xCC4F); in init_display()
41 write_reg(par, 0x0013, 0x674F); in init_display()
42 write_reg(par, 0x0011, 0x2003); in init_display()
[all …]
H A Dfb_ili9325.c96 write_reg(par, 0x00E3, 0x3008); /* Set internal timing */ in init_display()
97 write_reg(par, 0x00E7, 0x0012); /* Set internal timing */ in init_display()
98 write_reg(par, 0x00EF, 0x1231); /* Set internal timing */ in init_display()
99 write_reg(par, 0x0001, 0x0100); /* set SS and SM bit */ in init_display()
100 write_reg(par, 0x0002, 0x0700); /* set 1 line inversion */ in init_display()
101 write_reg(par, 0x0004, 0x0000); /* Resize register */ in init_display()
102 write_reg(par, 0x0008, 0x0207); /* set the back porch and front porch */ in init_display()
103 write_reg(par, 0x0009, 0x0000); /* set non-display area refresh cycle */ in init_display()
104 write_reg(par, 0x000A, 0x0000); /* FMARK function */ in init_display()
105 write_reg(par, 0x000C, 0x0000); /* RGB interface setting */ in init_display()
[all …]
H A Dfb_ra8875.c48 write_reg(par, 0x88, 0x0A); in init_display()
49 write_reg(par, 0x89, 0x02); in init_display()
52 write_reg(par, 0x10, 0x0C); in init_display()
54 write_reg(par, 0x04, 0x03); in init_display()
57 write_reg(par, 0x14, 0x27); in init_display()
58 write_reg(par, 0x15, 0x00); in init_display()
59 write_reg(par, 0x16, 0x05); in init_display()
60 write_reg(par, 0x17, 0x04); in init_display()
61 write_reg(par, 0x18, 0x03); in init_display()
63 write_reg(par, 0x19, 0xEF); in init_display()
[all …]
H A Dfb_ssd1289.c30 write_reg(par, 0x00, 0x0001); in init_display()
31 write_reg(par, 0x03, 0xA8A4); in init_display()
32 write_reg(par, 0x0C, 0x0000); in init_display()
33 write_reg(par, 0x0D, 0x080C); in init_display()
34 write_reg(par, 0x0E, 0x2B00); in init_display()
35 write_reg(par, 0x1E, 0x00B7); in init_display()
36 write_reg(par, 0x01, in init_display()
38 write_reg(par, 0x02, 0x0600); in init_display()
39 write_reg(par, 0x10, 0x0000); in init_display()
40 write_reg(par, 0x05, 0x0000); in init_display()
[all …]
H A Dfb_hx8347d.c28 write_reg(par, 0xEA, 0x00); in init_display()
29 write_reg(par, 0xEB, 0x20); in init_display()
30 write_reg(par, 0xEC, 0x0C); in init_display()
31 write_reg(par, 0xED, 0xC4); in init_display()
32 write_reg(par, 0xE8, 0x40); in init_display()
33 write_reg(par, 0xE9, 0x38); in init_display()
34 write_reg(par, 0xF1, 0x01); in init_display()
35 write_reg(par, 0xF2, 0x10); in init_display()
36 write_reg(par, 0x27, 0xA3); in init_display()
39 write_reg(par, 0x1B, 0x1B); in init_display()
[all …]
H A Dfb_ssd1306.c46 write_reg(par, 0xAE); in init_display()
49 write_reg(par, 0xD5); in init_display()
50 write_reg(par, 0x80); in init_display()
53 write_reg(par, 0xA8); in init_display()
55 write_reg(par, 0x3F); in init_display()
57 write_reg(par, 0x2F); in init_display()
59 write_reg(par, 0x1F); in init_display()
62 write_reg(par, 0xD3); in init_display()
63 write_reg(par, 0x0); in init_display()
66 write_reg(par, 0x40 | 0x0); in init_display()
[all …]
H A Dfb_ssd1305.c47 write_reg(par, 0xAE); in init_display()
50 write_reg(par, 0xD5); in init_display()
51 write_reg(par, 0x80); in init_display()
54 write_reg(par, 0xA8); in init_display()
56 write_reg(par, 0x3F); in init_display()
58 write_reg(par, 0x1F); in init_display()
61 write_reg(par, 0xD3); in init_display()
62 write_reg(par, 0x0); in init_display()
65 write_reg(par, 0x40 | 0x0); in init_display()
68 write_reg(par, 0x8D); in init_display()
[all …]
H A Dfb_ssd1325.c38 write_reg(par, 0xb3); in init_display()
39 write_reg(par, 0xf0); in init_display()
40 write_reg(par, 0xae); in init_display()
41 write_reg(par, 0xa1); in init_display()
42 write_reg(par, 0x00); in init_display()
43 write_reg(par, 0xa8); in init_display()
44 write_reg(par, 0x3f); in init_display()
45 write_reg(par, 0xa0); in init_display()
46 write_reg(par, 0x45); in init_display()
47 write_reg(par, 0xa2); in init_display()
[all …]
H A Dfb_uc1701.c68 write_reg(par, LCD_RESET_CMD); in init_display()
72 write_reg(par, LCD_START_LINE); in init_display()
75 write_reg(par, LCD_BOTTOMVIEW | 1); in init_display()
78 write_reg(par, LCD_SCAN_DIR | 0x00); in init_display()
81 write_reg(par, LCD_ALL_PIXEL | 0); in init_display()
84 write_reg(par, LCD_DISPLAY_INVERT | 0); in init_display()
87 write_reg(par, LCD_BIAS | 0); in init_display()
90 write_reg(par, LCD_POWER_CONTROL | 0x07); in init_display()
93 write_reg(par, LCD_VOLTAGE | 0x07); in init_display()
96 write_reg(par, LCD_VOLUME_MODE); in init_display()
[all …]
H A Dfb_ssd1331.c29 write_reg(par, 0xae); /* Display Off */ in init_display()
33 write_reg(par, 0xa0, 0x60 | (par->bgr << 2)); in init_display()
35 write_reg(par, 0xa0, 0x72 | (par->bgr << 2)); in init_display()
37 write_reg(par, 0x72); /* RGB colour */ in init_display()
38 write_reg(par, 0xa1, 0x00); /* Set Display Start Line */ in init_display()
39 write_reg(par, 0xa2, 0x00); /* Set Display Offset */ in init_display()
40 write_reg(par, 0xa4); /* NORMALDISPLAY */ in init_display()
41 write_reg(par, 0xa8, 0x3f); /* Set multiplex */ in init_display()
42 write_reg(par, 0xad, 0x8e); /* Set master */ in init_display()
44 write_reg(par, 0xb1, 0x31); /* Precharge */ in init_display()
[all …]
H A Dfb_uc1611.c81 write_reg(par, 0xE2); in init_display()
84 write_reg(par, 0xE8 | (ratio & 0x03)); in init_display()
87 write_reg(par, 0x81); in init_display()
88 write_reg(par, (gain & 0x03) << 6 | (pot & 0x3F)); in init_display()
91 write_reg(par, 0x24 | (temp & 0x03)); in init_display()
94 write_reg(par, 0x28 | (load & 0x03)); in init_display()
97 write_reg(par, 0x2C | (pump & 0x03)); in init_display()
100 write_reg(par, 0xA6 | 0x01); in init_display()
103 write_reg(par, 0xD0 | (0x02 & 0x03)); in init_display()
106 write_reg(par, 0xA8 | 0x07); in init_display()
[all …]
H A Dfb_st7789v.c154 write_reg(par, MIPI_DCS_EXIT_SLEEP_MODE); in init_display()
158 write_reg(par, MIPI_DCS_SET_PIXEL_FORMAT, MIPI_DCS_PIXEL_FMT_16BIT); in init_display()
160 write_reg(par, PORCTRL, 0x05, 0x05, 0x00, 0x33, 0x33); in init_display()
163 write_reg(par, PORCTRL, 0x08, 0x08, 0x00, 0x22, 0x22); in init_display()
170 write_reg(par, GCTRL, 0x75); in init_display()
172 write_reg(par, GCTRL, 0x35); in init_display()
178 write_reg(par, VDVVRHEN, 0x01, 0xFF); in init_display()
185 write_reg(par, VRHS, 0x13); in init_display()
187 write_reg(par, VRHS, 0x0B); in init_display()
190 write_reg(par, VDVS, 0x20); in init_display()
[all …]
H A Dfb_sh1106.c38 write_reg(par, 0xAE); in init_display()
41 write_reg(par, 0xD5, 0x80); in init_display()
44 write_reg(par, 0xA8, par->info->var.yres - 1); in init_display()
47 write_reg(par, 0xD3, 0x00); in init_display()
50 write_reg(par, 0x40 | 0x0); in init_display()
54 write_reg(par, 0xA0 | 0x1); in init_display()
58 write_reg(par, 0xC8); in init_display()
63 write_reg(par, 0xDA, 0x12); in init_display()
66 write_reg(par, 0xDA, 0x12); in init_display()
69 write_reg(par, 0xDA, 0x02); in init_display()
[all …]
H A Dfb_tls8204.c38 write_reg(par, 0x21); /* 5:1 1 in init_display()
46 write_reg(par, 0x10 | (bs & 0x7)); in init_display()
55 write_reg(par, 0x04 | (64 >> 6)); in init_display()
56 write_reg(par, 0x40 | (64 & 0x3F)); in init_display()
59 write_reg(par, 0x20); in init_display()
62 write_reg(par, 0x08 | 4); in init_display()
75 write_reg(par, 0x80); /* 7:1 1 in set_addr_win()
80 write_reg(par, 0x40); /* 7:0 0 in set_addr_win()
98 write_reg(par, 0x80 | 0); in write_vmem()
99 write_reg(par, 0x40 | y); in write_vmem()
[all …]
H A Dfb_pcd8544.c45 write_reg(par, 0x21); in init_display()
53 write_reg(par, 0x04 | (tc & 0x3)); in init_display()
63 write_reg(par, 0x10 | (bs & 0x7)); in init_display()
72 write_reg(par, 0x22); in init_display()
81 write_reg(par, 0x08 | 4); in init_display()
93 write_reg(par, 0x80); in set_addr_win()
101 write_reg(par, 0x40); in set_addr_win()
136 write_reg(par, 0x23); /* turn on extended instruction set */ in set_gamma()
137 write_reg(par, 0x80 | curves[0]); in set_gamma()
138 write_reg(par, 0x22); /* turn off extended instruction set */ in set_gamma()
/linux/arch/sh/boards/mach-kfr2r09/
H A Dlcd_wqvga.c65 static void write_reg(void *sohandle, in write_reg() function
82 write_reg(sohandle, so, 1, data[i]); in write_data()
91 write_reg(sohandle, so, 0, 0xb0); in read_device_code()
92 write_reg(sohandle, so, 1, 0x00); in read_device_code()
95 write_reg(sohandle, so, 0, 0xb1); in read_device_code()
96 write_reg(sohandle, so, 1, 0x00); in read_device_code()
99 write_reg(sohandle, so, 0, 0xbf); in read_device_code()
117 write_reg(sohandle, so, 0, 0x2c); in write_memory_start()
130 write_reg(sohandle, so, 1, 0x00); in clear_memory()
137 write_reg(sohandle, so, 0, 0xb0); in display_on()
[all …]
/linux/drivers/media/dvb-frontends/
H A Dstv0910.c127 static int write_reg(struct stv *state, u16 reg, u8 val) in write_reg() function
179 status = write_reg(state, reg, (tmp & ~mask) | (val & mask)); in write_shared_reg()
197 return write_reg(state, field >> 16, new); in write_field()
205 write_reg(state, state->nr ? RSTV0910_P2_##_reg : \
554 write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, tmp); in tracking_optimization()
567 write_reg(state, RSTV0910_P2_ACLC2S2Q + in tracking_optimization()
570 write_reg(state, RSTV0910_P2_ACLC2S2Q + in tracking_optimization()
572 write_reg(state, RSTV0910_P2_ACLC2S28 + in tracking_optimization()
575 write_reg(state, RSTV0910_P2_ACLC2S2Q + in tracking_optimization()
577 write_reg(state, RSTV0910_P2_ACLC2S216A + in tracking_optimization()
[all …]
H A Dcxd2099.c150 static int write_reg(struct cxd *ci, u8 reg, u8 val) in write_reg() function
215 write_reg(ci, 0x0d, 0x00); in cam_mode()
216 write_reg(ci, 0x0e, 0x01); in cam_mode()
234 status = write_reg(ci, 0x00, 0x00); in init()
237 status = write_reg(ci, 0x01, 0x00); in init()
240 status = write_reg(ci, 0x02, 0x10); in init()
243 status = write_reg(ci, 0x03, 0x00); in init()
246 status = write_reg(ci, 0x05, 0xFF); in init()
249 status = write_reg(ci, 0x06, 0x1F); in init()
252 status = write_reg(ci, 0x07, 0x1F); in init()
[all …]
/linux/drivers/net/ethernet/intel/igb/
H A De1000_phy.c62 phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0); in igb_get_phy_id()
91 if (!(hw->phy.ops.write_reg)) in igb_phy_reset_dsp()
94 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); in igb_phy_reset_dsp()
98 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); in igb_phy_reset_dsp()
484 ret_val = phy->ops.write_reg(hw, I82580_CFG_REG, phy_data); in igb_copper_link_setup_82580()
509 ret_val = hw->phy.ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data); in igb_copper_link_setup_82580()
575 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); in igb_copper_link_setup_m88()
602 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, in igb_copper_link_setup_m88()
683 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); in igb_copper_link_setup_m88_gen2()
698 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); in igb_copper_link_setup_m88_gen2()
[all …]
/linux/drivers/media/radio/
H A Dradio-tea5777.c184 tea->write_reg &= ~TEA5777_W_AM_FM_MASK; in radio_tea5777_set_freq()
186 tea->write_reg &= ~TEA5777_W_FM_PLL_MASK; in radio_tea5777_set_freq()
187 tea->write_reg |= (u64)freq << TEA5777_W_FM_PLL_SHIFT; in radio_tea5777_set_freq()
188 tea->write_reg &= ~TEA5777_W_FM_FREF_MASK; in radio_tea5777_set_freq()
189 tea->write_reg |= TEA5777_W_FM_FREF_VALUE << in radio_tea5777_set_freq()
191 tea->write_reg &= ~TEA5777_W_FM_FORCEMONO_MASK; in radio_tea5777_set_freq()
193 tea->write_reg |= 1LL << TEA5777_W_FM_FORCEMONO_SHIFT; in radio_tea5777_set_freq()
196 tea->write_reg &= ~TEA5777_W_AM_FM_MASK; in radio_tea5777_set_freq()
197 tea->write_reg |= (1LL << TEA5777_W_AM_FM_SHIFT); in radio_tea5777_set_freq()
199 tea->write_reg &= ~TEA5777_W_AM_PLL_MASK; in radio_tea5777_set_freq()
[all …]
/linux/drivers/media/dvb-frontends/cxd2880/
H A Dcxd2880_tnrdmd_dvbt2.c180 ret = tnr_dmd->io->write_reg(tnr_dmd->io, in x_tune_dvbt2_demod_setting()
193 ret = tnr_dmd->io->write_reg(tnr_dmd->io, in x_tune_dvbt2_demod_setting()
199 ret = tnr_dmd->io->write_reg(tnr_dmd->io, in x_tune_dvbt2_demod_setting()
205 ret = tnr_dmd->io->write_reg(tnr_dmd->io, in x_tune_dvbt2_demod_setting()
211 ret = tnr_dmd->io->write_reg(tnr_dmd->io, in x_tune_dvbt2_demod_setting()
223 ret = tnr_dmd->io->write_reg(tnr_dmd->io, in x_tune_dvbt2_demod_setting()
229 ret = tnr_dmd->io->write_reg(tnr_dmd->io, in x_tune_dvbt2_demod_setting()
235 ret = tnr_dmd->io->write_reg(tnr_dmd->io, in x_tune_dvbt2_demod_setting()
241 ret = tnr_dmd->io->write_reg(tnr_dmd->io, in x_tune_dvbt2_demod_setting()
279 ret = tnr_dmd->io->write_reg(tnr_dmd->io, in x_tune_dvbt2_demod_setting()
[all …]
H A Dcxd2880_tnrdmd_mon.c29 ret = tnr_dmd->io->write_reg(tnr_dmd->io, in cxd2880_tnrdmd_mon_rf_lvl()
35 ret = tnr_dmd->io->write_reg(tnr_dmd->io, in cxd2880_tnrdmd_mon_rf_lvl()
41 ret = tnr_dmd->io->write_reg(tnr_dmd->io, in cxd2880_tnrdmd_mon_rf_lvl()
55 ret = tnr_dmd->io->write_reg(tnr_dmd->io, in cxd2880_tnrdmd_mon_rf_lvl()
82 ret = tnr_dmd->io->write_reg(tnr_dmd->io, in cxd2880_tnrdmd_mon_rf_lvl()
88 ret = tnr_dmd->io->write_reg(tnr_dmd->io, in cxd2880_tnrdmd_mon_rf_lvl()
121 ret = tnr_dmd->io->write_reg(tnr_dmd->io, in cxd2880_tnrdmd_mon_internal_cpu_status()

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