| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | display_mode_util.c | 303 void dml_print_ttu_regs_st(const dml_display_ttu_regs_st *ttu_regs) in dml_print_ttu_regs_st() argument
305 (void)ttu_regs; in dml_print_ttu_regs_st()
308 dml_print("DML: qos_level_low_wm = 0x%x\n", ttu_regs->qos_level_low_wm); in dml_print_ttu_regs_st()
309 dml_print("DML: qos_level_high_wm = 0x%x\n", ttu_regs->qos_level_high_wm); in dml_print_ttu_regs_st()
310 dml_print("DML: min_ttu_vblank = 0x%x\n", ttu_regs->min_ttu_vblank); in dml_print_ttu_regs_st()
311 dml_print("DML: qos_level_flip = 0x%x\n", ttu_regs->qos_level_flip); in dml_print_ttu_regs_st()
312 dml_print("DML: refcyc_per_req_delivery_pre_l = 0x%x\n", ttu_regs->refcyc_per_req_delivery_pre_l); in dml_print_ttu_regs_st()
313 dml_print("DML: refcyc_per_req_delivery_l = 0x%x\n", ttu_regs->refcyc_per_req_delivery_l); in dml_print_ttu_regs_st()
314 dml_print("DML: refcyc_per_req_delivery_pre_c = 0x%x\n", ttu_regs->refcyc_per_req_delivery_pre_c); in dml_print_ttu_regs_st()
315 dml_print("DML: refcyc_per_req_delivery_c = 0x%x\n", ttu_regs->refcyc_per_req_delivery_c); in dml_print_ttu_regs_st()
[all …]
|
| H A D | dml2_translation_helper.c | 1513 memset(&out->ttu_regs, 0, sizeof(out->ttu_regs)); in dml2_update_pipe_ctx_dchub_regs()
1514 out->ttu_regs.qos_level_low_wm = disp_ttu_regs->qos_level_low_wm; in dml2_update_pipe_ctx_dchub_regs()
1515 out->ttu_regs.qos_level_high_wm = disp_ttu_regs->qos_level_high_wm; in dml2_update_pipe_ctx_dchub_regs()
1516 out->ttu_regs.min_ttu_vblank = disp_ttu_regs->min_ttu_vblank; in dml2_update_pipe_ctx_dchub_regs()
1517 out->ttu_regs.qos_level_flip = disp_ttu_regs->qos_level_flip; in dml2_update_pipe_ctx_dchub_regs()
1518 out->ttu_regs.refcyc_per_req_delivery_l = disp_ttu_regs->refcyc_per_req_delivery_l; in dml2_update_pipe_ctx_dchub_regs()
1519 out->ttu_regs.refcyc_per_req_delivery_c = disp_ttu_regs->refcyc_per_req_delivery_c; in dml2_update_pipe_ctx_dchub_regs()
1520 out->ttu_regs.refcyc_per_req_delivery_cur0 = disp_ttu_regs->refcyc_per_req_delivery_cur0; in dml2_update_pipe_ctx_dchub_regs()
1521 out->ttu_regs.refcyc_per_req_delivery_cur1 = disp_ttu_regs->refcyc_per_req_delivery_cur1; in dml2_update_pipe_ctx_dchub_regs()
1522 out->ttu_regs.refcyc_per_req_delivery_pre_l = disp_ttu_regs->refcyc_per_req_delivery_pre_l; in dml2_update_pipe_ctx_dchub_regs()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_lib.h | 54 display_ttu_regs_st *ttu_regs,
72 display_ttu_regs_st *ttu_regs,
|
| H A D | dml1_display_rq_dlg_calc.h | 57 struct _vcs_dpi_display_ttu_regs_st *ttu_regs,
|
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | display_rq_dlg_calc_32.h | 65 display_ttu_regs_st *ttu_regs,
|
| H A D | dcn32_fpu.c | 1763 &context->res_ctx.pipe_ctx[i].dlg_regs, &context->res_ctx.pipe_ctx[i].ttu_regs, pipes, in dcn32_calculate_dlg_params()
|
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| H A D | display_rq_dlg_calc_21.h | 63 display_ttu_regs_st *ttu_regs,
|
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | display_rq_dlg_calc_20.h | 63 display_ttu_regs_st *ttu_regs,
|
| H A D | display_rq_dlg_calc_20v2.h | 63 display_ttu_regs_st *ttu_regs,
|
| H A D | dcn20_fpu.c | 1236 &context->res_ctx.pipe_ctx[i].ttu_regs, in dcn20_calculate_dlg_params()
|
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | display_rq_dlg_calc_31.h | 59 display_ttu_regs_st *ttu_regs,
|
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| H A D | display_rq_dlg_calc_314.h | 60 display_ttu_regs_st *ttu_regs,
|
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | display_rq_dlg_calc_30.h | 59 display_ttu_regs_st *ttu_regs,
|
| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_hw_sequencer.c | 2998 struct _vcs_dpi_display_ttu_regs_st *ttu_regs = params->hubp_setup_params.ttu_regs; in hwss_hubp_setup() local
3003 hubp->funcs->hubp_setup(hubp, dlg_regs, ttu_regs, rq_regs, pipe_dest); in hwss_hubp_setup()
3028 struct _vcs_dpi_display_ttu_regs_st *ttu_regs = params->hubp_setup_interdependent_params.ttu_regs; in hwss_hubp_setup_interdependent() local
3031 hubp->funcs->hubp_setup_interdependent(hubp, dlg_regs, ttu_regs); in hwss_hubp_setup_interdependent()
3861 struct _vcs_dpi_display_ttu_regs_st *ttu_regs, in hwss_add_hubp_setup() argument
3869 seq_state->steps[*seq_state->num_steps].params.hubp_setup_params.ttu_regs = ttu_regs; in hwss_add_hubp_setup()
3903 struct _vcs_dpi_display_ttu_regs_st *ttu_regs) in hwss_add_hubp_setup_interdependent() argument
3909 …eq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent_params.ttu_regs = ttu_regs; in hwss_add_hubp_setup_interdependent()
|
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 2821 struct dml2_display_ttu_regs old_ttu_regs = old_pipe->hubp_regs.ttu_regs; in dcn401_detect_pipe_changes()
2824 struct dml2_display_ttu_regs *new_ttu_regs = &new_pipe->hubp_regs.ttu_regs; in dcn401_detect_pipe_changes()
3548 &pipe_ctx->ttu_regs, &pipe_ctx->rq_regs, &pipe_ctx->pipe_dlg_param); in dcn401_update_dchubp_dpp_sequence()
3561 hwss_add_hubp_setup_interdependent(seq_state, hubp, &pipe_ctx->dlg_regs, &pipe_ctx->ttu_regs); in dcn401_update_dchubp_dpp_sequence()
|
| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/ |
| H A D | dml2_core_dcn4_calcs.c | 12796 …rq_dlg_get_dlg_reg(&mode_lib->scratch, &out->dlg_regs, &out->ttu_regs, display_cfg, mode_lib, pipe… in dml2_core_calcs_get_pipe_regs()
|