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Searched refs:tg_mask (Results 1 – 25 of 29) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/optc/dcn201/
H A Ddcn201_optc.c39 optc1->tg_shift->field_name, optc1->tg_mask->field_name
189 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn201_timing_generator_init()
190 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn201_timing_generator_init()
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn35/
H A Ddcn35_optc.c45 optc1->tg_shift->field_name, optc1->tg_mask->field_name
219 if (optc1->base.ctx->dc->debug.otg_crc_db && optc1->tg_mask->OTG_CRC_WINDOW_DB_EN != 0) in optc35_configure_crc()
252 if (optc1->base.ctx->dc->debug.otg_crc_db && optc1->tg_mask->OTG_CRC_WINDOW_DB_EN != 0) in optc35_configure_crc()
501 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn35_timing_generator_init()
502 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn35_timing_generator_init()
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn314/
H A Ddcn314_optc.c43 optc1->tg_shift->field_name, optc1->tg_mask->field_name
264 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn314_timing_generator_init()
265 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn314_timing_generator_init()
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn31/
H A Ddcn31_optc.c41 optc1->tg_shift->field_name, optc1->tg_mask->field_name
315 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn31_timing_generator_init()
316 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn31_timing_generator_init()
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn20/
H A Ddcn20_optc.c38 optc1->tg_shift->field_name, optc1->tg_mask->field_name
571 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn20_timing_generator_init()
572 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn20_timing_generator_init()
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn401/
H A Ddcn401_optc.c22 optc1->tg_shift->field_name, optc1->tg_mask->field_name
536 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn401_timing_generator_init()
537 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn401_timing_generator_init()
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn10/
H A Ddcn10_optc.c40 optc1->tg_shift->field_name, optc1->tg_mask->field_name
308 if (REG(OPTC_DATA_FORMAT_CONTROL) && optc1->tg_mask->OPTC_DATA_FORMAT != 0) { in optc1_program_timing()
319 if (optc1->tg_mask->OTG_H_TIMING_DIV_MODE != 0) { in optc1_program_timing()
1672 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn10_timing_generator_init()
1673 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn10_timing_generator_init()
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Doptc.h50 const struct dcn_optc_mask *tg_mask; member
/linux/drivers/net/ethernet/mscc/
H A Docelot_vcap.c46 u32 tg_mask; /* Current type-group mask */ member
199 data->tg_mask = 0; in vcap_data_offset_get()
203 data->tg_mask |= GENMASK(offset + width - 1, offset); in vcap_data_offset_get()
365 data.tg = (data.tg & ~data.tg_mask); in is2_entry_set()
688 data.tg = (data.tg & ~data.tg_mask); in is1_entry_set()
827 data.tg = (data.tg & ~data.tg_mask); in es0_entry_set()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/
H A Ddcn201_resource.c513 static const struct dcn_optc_mask tg_mask = { variable
772 tgn10->tg_mask = &tg_mask; in dcn201_timing_generator_create()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.c271 uint32_t tg_mask = 0; in dcn32_update_clocks_update_dtb_dto() local
280 !(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) { in dcn32_update_clocks_update_dtb_dto()
281 tg_mask |= (1 << pipe_ctx->stream_res.tg->inst); in dcn32_update_clocks_update_dtb_dto()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn10/
H A Ddcn10_resource.c405 static const struct dcn_optc_mask tg_mask = { variable
715 tgn10->tg_mask = &tg_mask; in dcn10_timing_generator_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/
H A Ddcn21_resource.c272 static const struct dcn_optc_mask tg_mask = { variable
1055 tgn10->tg_mask = &tg_mask; in dcn21_timing_generator_create()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_clk_mgr.c250 uint32_t tg_mask = 0; in dcn35_update_clocks_update_dtb_dto() local
259 !(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) { in dcn35_update_clocks_update_dtb_dto()
260 tg_mask |= (1 << pipe_ctx->stream_res.tg->inst); in dcn35_update_clocks_update_dtb_dto()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.c515 static const struct dcn_optc_mask tg_mask = { variable
895 tgn10->tg_mask = &tg_mask; in dcn20_timing_generator_create()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddcn30_fpu.c44 optc1->tg_shift->field_name, optc1->tg_mask->field_name
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/
H A Ddcn302_resource.c615 tgn10->tg_mask = &optc_mask; in dcn302_timing_generator_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/
H A Ddcn303_resource.c588 tgn10->tg_mask = &optc_mask; in dcn303_timing_generator_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn301/
H A Ddcn301_resource.c859 tgn10->tg_mask = &optc_mask; in dcn301_timing_generator_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/
H A Ddcn316_resource.c1061 tgn10->tg_mask = &optc_mask; in dcn31_timing_generator_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/
H A Ddcn314_resource.c1125 tgn10->tg_mask = &optc_mask; in dcn31_timing_generator_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/
H A Ddcn31_resource.c1069 tgn10->tg_mask = &optc_mask; in dcn31_timing_generator_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/
H A Ddcn321_resource.c1011 tgn10->tg_mask = &optc_mask; in dcn321_timing_generator_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.c1050 tgn10->tg_mask = &optc_mask; in dcn35_timing_generator_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/
H A Ddcn351_resource.c1030 tgn10->tg_mask = &optc_mask; in dcn35_timing_generator_create()

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