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Searched refs:rq_regs (Results 1 – 21 of 21) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn201/
H A Ddcn201_hubp.c67 struct _vcs_dpi_display_rq_regs_st *rq_regs) in hubp201_program_requestor() argument
72 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); in hubp201_program_requestor()
75 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, in hubp201_program_requestor()
76 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, in hubp201_program_requestor()
77 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, in hubp201_program_requestor()
78 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); in hubp201_program_requestor()
82 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, in hubp201_program_requestor()
83 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, in hubp201_program_requestor()
84 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, in hubp201_program_requestor()
85 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, in hubp201_program_requestor()
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/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddml_display_rq_dlg_calc.c39 void dml_rq_dlg_get_rq_reg(dml_display_rq_regs_st *rq_regs, in dml_rq_dlg_get_rq_reg() argument
73 memset(rq_regs, 0, sizeof(*rq_regs)); in dml_rq_dlg_get_rq_reg()
97 rq_regs->rq_regs_l.chunk_size = (dml_uint_t)(dml_log2((dml_float_t) pixel_chunk_bytes) - 10); in dml_rq_dlg_get_rq_reg()
98 rq_regs->rq_regs_c.chunk_size = (dml_uint_t)(dml_log2((dml_float_t) p1_pixel_chunk_bytes) - 10); in dml_rq_dlg_get_rq_reg()
101 rq_regs->rq_regs_l.min_chunk_size = 0; in dml_rq_dlg_get_rq_reg()
103 …rq_regs->rq_regs_l.min_chunk_size = (dml_uint_t)(dml_log2((dml_float_t) min_pixel_chunk_bytes) - 8… in dml_rq_dlg_get_rq_reg()
106 rq_regs->rq_regs_c.min_chunk_size = 0; in dml_rq_dlg_get_rq_reg()
108 …rq_regs->rq_regs_c.min_chunk_size = (dml_uint_t)(dml_log2((dml_float_t) p1_min_pixel_chunk_bytes) … in dml_rq_dlg_get_rq_reg()
110 rq_regs->rq_regs_l.meta_chunk_size = (dml_uint_t)(dml_log2((dml_float_t) meta_chunk_bytes) - 10); in dml_rq_dlg_get_rq_reg()
111 …rq_regs->rq_regs_c.meta_chunk_size = (dml_uint_t)(dml_log2((dml_float_t) p1_meta_chunk_bytes) - 10… in dml_rq_dlg_get_rq_reg()
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H A Ddml2_translation_helper.c1435 void dml2_update_pipe_ctx_dchub_regs(struct _vcs_dpi_dml_display_rq_regs_st *rq_regs, in dml2_update_pipe_ctx_dchub_regs() argument
1440 memset(&out->rq_regs, 0, sizeof(out->rq_regs)); in dml2_update_pipe_ctx_dchub_regs()
1441 out->rq_regs.rq_regs_l.chunk_size = rq_regs->rq_regs_l.chunk_size; in dml2_update_pipe_ctx_dchub_regs()
1442 out->rq_regs.rq_regs_l.min_chunk_size = rq_regs->rq_regs_l.min_chunk_size; in dml2_update_pipe_ctx_dchub_regs()
1443 out->rq_regs.rq_regs_l.meta_chunk_size = rq_regs->rq_regs_l.meta_chunk_size; in dml2_update_pipe_ctx_dchub_regs()
1444 out->rq_regs.rq_regs_l.min_meta_chunk_size = rq_regs->rq_regs_l.min_meta_chunk_size; in dml2_update_pipe_ctx_dchub_regs()
1445 out->rq_regs.rq_regs_l.dpte_group_size = rq_regs->rq_regs_l.dpte_group_size; in dml2_update_pipe_ctx_dchub_regs()
1446 out->rq_regs.rq_regs_l.mpte_group_size = rq_regs->rq_regs_l.mpte_group_size; in dml2_update_pipe_ctx_dchub_regs()
1447 out->rq_regs.rq_regs_l.swath_height = rq_regs->rq_regs_l.swath_height; in dml2_update_pipe_ctx_dchub_regs()
1448 out->rq_regs.rq_regs_l.pte_row_height_linear = rq_regs->rq_regs_l.pte_row_height_linear; in dml2_update_pipe_ctx_dchub_regs()
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H A Ddisplay_mode_util.c219 void dml_print_data_rq_regs_st(const dml_display_plane_rq_regs_st *rq_regs) in dml_print_data_rq_regs_st() argument
221 (void)rq_regs; in dml_print_data_rq_regs_st()
224 dml_print("DML: chunk_size = 0x%x\n", rq_regs->chunk_size); in dml_print_data_rq_regs_st()
225 dml_print("DML: min_chunk_size = 0x%x\n", rq_regs->min_chunk_size); in dml_print_data_rq_regs_st()
226 dml_print("DML: meta_chunk_size = 0x%x\n", rq_regs->meta_chunk_size); in dml_print_data_rq_regs_st()
227 dml_print("DML: min_meta_chunk_size = 0x%x\n", rq_regs->min_meta_chunk_size); in dml_print_data_rq_regs_st()
228 dml_print("DML: dpte_group_size = 0x%x\n", rq_regs->dpte_group_size); in dml_print_data_rq_regs_st()
229 dml_print("DML: mpte_group_size = 0x%x\n", rq_regs->mpte_group_size); in dml_print_data_rq_regs_st()
230 dml_print("DML: swath_height = 0x%x\n", rq_regs->swath_height); in dml_print_data_rq_regs_st()
231 dml_print("DML: pte_row_height_linear = 0x%x\n", rq_regs->pte_row_height_linear); in dml_print_data_rq_regs_st()
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H A Ddml2_utils.c340 dml_rq_dlg_get_rq_reg(&s->rq_regs, &in_ctx->v20.dml_core_ctx, dml_pipe_idx); in dml2_calculate_rq_and_dlg_params()
342 …dml2_update_pipe_ctx_dchub_regs(&s->rq_regs, &s->disp_dlg_regs, &s->disp_ttu_regs, &out_new_hw_sta… in dml2_calculate_rq_and_dlg_params()
/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_lib.h65 display_rq_regs_st *rq_regs,
76 void (*rq_dlg_get_rq_reg_v2)(display_rq_regs_st *rq_regs,
H A Ddml1_display_rq_dlg_calc.h35 struct _vcs_dpi_display_rq_regs_st *rq_regs,
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_rq_dlg_calc_32.h44 void dml32_rq_dlg_get_rq_reg(display_rq_regs_st *rq_regs,
H A Ddcn32_fpu.c1766 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg_v2(&context->res_ctx.pipe_ctx[i].rq_regs, in dcn32_calculate_dlg_params()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/
H A Ddisplay_rq_dlg_calc_21.h46 display_rq_regs_st *rq_regs,
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddisplay_rq_dlg_calc_20.h45 display_rq_regs_st *rq_regs,
H A Ddisplay_rq_dlg_calc_20v2.h45 display_rq_regs_st *rq_regs,
H A Ddcn20_fpu.c1245 &context->res_ctx.pipe_ctx[i].rq_regs, in dcn20_calculate_dlg_params()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddisplay_rq_dlg_calc_31.h43 display_rq_regs_st *rq_regs,
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/
H A Ddisplay_rq_dlg_calc_314.h44 display_rq_regs_st *rq_regs,
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddisplay_rq_dlg_calc_30.h43 display_rq_regs_st *rq_regs,
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn21/
H A Ddcn21_hubp.h133 struct _vcs_dpi_display_rq_regs_st *rq_regs);
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/
H A Ddml2_core_dcn4_calcs.c12274 static void rq_dlg_get_rq_reg(struct dml2_display_rq_regs *rq_regs, in rq_dlg_get_rq_reg() argument
12328 rq_regs->unbounded_request_enabled = dml_get_unbounded_request_enabled(mode_lib); in rq_dlg_get_rq_reg()
12329 rq_regs->rq_regs_l.chunk_size = log_and_substract_if_non_zero(pixel_chunk_bytes, 10); in rq_dlg_get_rq_reg()
12330 rq_regs->rq_regs_c.chunk_size = log_and_substract_if_non_zero(p1_pixel_chunk_bytes, 10); in rq_dlg_get_rq_reg()
12333 rq_regs->rq_regs_l.min_chunk_size = 0; in rq_dlg_get_rq_reg()
12335 rq_regs->rq_regs_l.min_chunk_size = log_and_substract_if_non_zero(min_pixel_chunk_bytes, 8 - 1); in rq_dlg_get_rq_reg()
12338 rq_regs->rq_regs_c.min_chunk_size = 0; in rq_dlg_get_rq_reg()
12340 …rq_regs->rq_regs_c.min_chunk_size = log_and_substract_if_non_zero(p1_min_pixel_chunk_bytes, 8 - 1); in rq_dlg_get_rq_reg()
12342 rq_regs->rq_regs_l.meta_chunk_size = log_and_substract_if_non_zero(meta_chunk_bytes, 10); in rq_dlg_get_rq_reg()
12343 rq_regs->rq_regs_c.meta_chunk_size = log_and_substract_if_non_zero(p1_meta_chunk_bytes, 10); in rq_dlg_get_rq_reg()
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/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/
H A Ddml21_utils.c227 pipe_ctx->unbounded_req = pln_prog->pipe_regs[pipe_reg_index]->rq_regs.unbounded_request_enabled; in dml21_program_dc_pipe()
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_hw_sequencer.c2999 struct _vcs_dpi_display_rq_regs_st *rq_regs = params->hubp_setup_params.rq_regs; in hwss_hubp_setup() local
3003 hubp->funcs->hubp_setup(hubp, dlg_regs, ttu_regs, rq_regs, pipe_dest); in hwss_hubp_setup()
3862 struct _vcs_dpi_display_rq_regs_st *rq_regs, in hwss_add_hubp_setup() argument
3870 seq_state->steps[*seq_state->num_steps].params.hubp_setup_params.rq_regs = rq_regs; in hwss_add_hubp_setup()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c2822 struct dml2_display_rq_regs old_rq_regs = old_pipe->hubp_regs.rq_regs; in dcn401_detect_pipe_changes()
2825 struct dml2_display_rq_regs *new_rq_regs = &new_pipe->hubp_regs.rq_regs; in dcn401_detect_pipe_changes()
3548 &pipe_ctx->ttu_regs, &pipe_ctx->rq_regs, &pipe_ctx->pipe_dlg_param); in dcn401_update_dchubp_dpp_sequence()