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Searched refs:regGCMC_VM_AGP_BASE (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dimu_v11_0_3.c97 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_BASE, 0x00000000, 0xe0000000),
121 if (entry->reg == regGCMC_VM_AGP_BASE) in program_rlc_ram_register_setting()
H A Dimu_v11_0.c245 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_BASE, 0x00000000, 0xe0000000),
304 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_BASE, 0x00000000, 0xe0000000),
338 if (entry->reg == regGCMC_VM_AGP_BASE) in program_imu_rlc_ram()
H A Dimu_v12_0.c242 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_BASE, 0x00000000, 0x1c0000),
270 if (entry->reg == regGCMC_VM_AGP_BASE) in program_imu_rlc_ram_old()
314 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_AGP_BASE)) in imu_v12_init_gfxhub_settings()
H A Dgfxhub_v3_0_3.c161 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0); in gfxhub_v3_0_3_init_system_aperture_regs()
H A Dgfxhub_v11_5_0.c159 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0); in gfxhub_v11_5_0_init_system_aperture_regs()
H A Dgfxhub_v3_0.c155 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0); in gfxhub_v3_0_init_system_aperture_regs()
H A Dgfxhub_v12_0.c163 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0); in gfxhub_v12_0_init_system_aperture_regs()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_12_0_0_offset.h2880 #define regGCMC_VM_AGP_BASE … macro
H A Dgc_11_0_3_offset.h3012 #define regGCMC_VM_AGP_BASE … macro
H A Dgc_11_0_0_offset.h2838 #define regGCMC_VM_AGP_BASE … macro