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Searched refs:ras (Results 1 – 25 of 44) sorted by relevance

12

/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_umc.c125 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_umc_handle_bad_pages()
126 adev->umc.ras->ras_block.hw_ops->query_ras_error_count) in amdgpu_umc_handle_bad_pages()
127 adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, in amdgpu_umc_handle_bad_pages()
130 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_umc_handle_bad_pages()
131 adev->umc.ras->ras_block.hw_ops->query_ras_error_address && in amdgpu_umc_handle_bad_pages()
150 adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, in amdgpu_umc_handle_bad_pages()
155 if (adev->umc.ras && in amdgpu_umc_handle_bad_pages()
156 adev->umc.ras in amdgpu_umc_handle_bad_pages()
327 struct amdgpu_umc_ras *ras; amdgpu_umc_ras_sw_init() local
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H A Damdgpu_mmhub.c27 struct amdgpu_mmhub_ras *ras; in amdgpu_mmhub_ras_sw_init() local
29 if (!adev->mmhub.ras) in amdgpu_mmhub_ras_sw_init()
32 ras = adev->mmhub.ras; in amdgpu_mmhub_ras_sw_init()
33 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_mmhub_ras_sw_init()
39 strcpy(ras->ras_block.ras_comm.name, "mmhub"); in amdgpu_mmhub_ras_sw_init()
40 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MMHUB; in amdgpu_mmhub_ras_sw_init()
41 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_mmhub_ras_sw_init()
42 adev->mmhub.ras_if = &ras->ras_block.ras_comm; in amdgpu_mmhub_ras_sw_init()
H A Damdgpu_nbio.c28 struct amdgpu_nbio_ras *ras; in amdgpu_nbio_ras_sw_init() local
30 if (!adev->nbio.ras) in amdgpu_nbio_ras_sw_init()
33 ras = adev->nbio.ras; in amdgpu_nbio_ras_sw_init()
34 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_nbio_ras_sw_init()
40 strcpy(ras->ras_block.ras_comm.name, "pcie_bif"); in amdgpu_nbio_ras_sw_init()
41 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__PCIE_BIF; in amdgpu_nbio_ras_sw_init()
42 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_nbio_ras_sw_init()
43 adev->nbio.ras_if = &ras->ras_block.ras_comm; in amdgpu_nbio_ras_sw_init()
H A Damdgpu_mca.c33 if (adev->umc.ras->check_ecc_err_status) in amdgpu_mca_is_deferred_error()
34 return adev->umc.ras->check_ecc_err_status(adev, in amdgpu_mca_is_deferred_error()
87 struct amdgpu_mca_ras_block *ras; in amdgpu_mca_mp0_ras_sw_init() local
89 if (!adev->mca.mp0.ras) in amdgpu_mca_mp0_ras_sw_init()
92 ras = adev->mca.mp0.ras; in amdgpu_mca_mp0_ras_sw_init()
94 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_mca_mp0_ras_sw_init()
100 strcpy(ras->ras_block.ras_comm.name, "mca.mp0"); in amdgpu_mca_mp0_ras_sw_init()
101 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MCA; in amdgpu_mca_mp0_ras_sw_init()
102 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_mca_mp0_ras_sw_init()
103 adev->mca.mp0.ras_if = &ras->ras_block.ras_comm; in amdgpu_mca_mp0_ras_sw_init()
[all …]
H A Damdgpu_ras_eeprom.c331 "Failed to alloc buf to write table ras info\n"); in __write_table_ras_info()
346 dev_err(adev->dev, "Failed to write EEPROM table ras info:%d", in __write_table_ras_info()
782 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in amdgpu_ras_eeprom_update_header()
790 control->ras_num_bad_pages > ras->bad_page_cnt_threshold) { in amdgpu_ras_eeprom_update_header()
793 control->ras_num_bad_pages, ras->bad_page_cnt_threshold); in amdgpu_ras_eeprom_update_header()
806 ras->is_rma = true; in amdgpu_ras_eeprom_update_header()
854 control->ras_num_bad_pages <= ras->bad_page_cnt_threshold) in amdgpu_ras_eeprom_update_header()
855 control->tbl_rai.health_percent = ((ras->bad_page_cnt_threshold - in amdgpu_ras_eeprom_update_header()
857 ras->bad_page_cnt_threshold; in amdgpu_ras_eeprom_update_header()
1058 if (!adev->umc.ras || !ade in amdgpu_ras_eeprom_read_idx()
779 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_eeprom_update_header() local
1207 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_debugfs_eeprom_size_read() local
1264 struct amdgpu_ras *ras = container_of(control, struct amdgpu_ras, amdgpu_ras_debugfs_set_ret_size() local
1276 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_debugfs_table_read() local
1395 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_debugfs_eeprom_table_read() local
1520 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_smu_eeprom_init() local
1557 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_eeprom_init() local
1632 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_smu_eeprom_check() local
1674 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_eeprom_check() local
1768 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_eeprom_check_and_recover() local
1797 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_get_smu_ras_drv() local
1936 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_check_bad_page_status() local
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H A Damdgpu_ras.c53 static const char *RAS_FS_NAME = "ras";
94 /* ras block link */
215 dev_warn(adev->dev, " echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n"); in amdgpu_reserve_page_direct()
522 * echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
523 * echo "enable <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
524 * echo "inject <block> <error> <sub-block> <address> <value> <mask>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
548 * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
549 * echo inject umc ce 0 0 0 3 > /sys/kernel/debug/dri/0/ras/ras_ctrl
550 * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
554 * To check disable/enable, see "ras" feature in amdgpu_ras_debugfs_ctrl_write()
1099 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_get_ecc_info() local
2868 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_in_recovery() local
2892 struct amdgpu_ras *ras = amdgpu_ras_do_recovery() local
3615 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_poison_creation_handler() local
4223 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_event_mgr_init() local
4726 struct amdgpu_ras *ras; amdgpu_ras_get_fed_status() local
4737 struct amdgpu_ras *ras; amdgpu_ras_set_fed() local
4750 struct amdgpu_ras *ras; amdgpu_ras_clear_err_state() local
4762 struct amdgpu_ras *ras; amdgpu_ras_set_err_poison() local
4771 struct amdgpu_ras *ras; amdgpu_ras_is_err_state() local
4788 struct amdgpu_ras *ras; __get_ras_event_mgr() local
4860 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_global_ras_isr() local
5052 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_is_supported() local
5080 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_reset_gpu() local
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H A Damdgpu_sdma.c314 struct amdgpu_sdma_ras *ras = NULL; in amdgpu_sdma_ras_sw_init() local
319 if (!adev->sdma.ras) in amdgpu_sdma_ras_sw_init()
322 ras = adev->sdma.ras; in amdgpu_sdma_ras_sw_init()
324 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_sdma_ras_sw_init()
330 strcpy(ras->ras_block.ras_comm.name, "sdma"); in amdgpu_sdma_ras_sw_init()
331 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__SDMA; in amdgpu_sdma_ras_sw_init()
332 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_sdma_ras_sw_init()
333 adev->sdma.ras_if = &ras->ras_block.ras_comm; in amdgpu_sdma_ras_sw_init()
336 if (!ras->ras_block.ras_late_init) in amdgpu_sdma_ras_sw_init()
337 ras->ras_block.ras_late_init = amdgpu_sdma_ras_late_init; in amdgpu_sdma_ras_sw_init()
[all …]
H A Daldebaran.c381 if (tmp_adev->sdma.ras && in aldebaran_mode2_restore_hwcontext()
382 tmp_adev->sdma.ras->ras_block.ras_late_init) { in aldebaran_mode2_restore_hwcontext()
383 r = tmp_adev->sdma.ras->ras_block.ras_late_init(tmp_adev, in aldebaran_mode2_restore_hwcontext()
384 &tmp_adev->sdma.ras->ras_block.ras_comm); in aldebaran_mode2_restore_hwcontext()
391 if (tmp_adev->gfx.ras && in aldebaran_mode2_restore_hwcontext()
392 tmp_adev->gfx.ras->ras_block.ras_late_init) { in aldebaran_mode2_restore_hwcontext()
393 r = tmp_adev->gfx.ras->ras_block.ras_late_init(tmp_adev, in aldebaran_mode2_restore_hwcontext()
394 &tmp_adev->gfx.ras->ras_block.ras_comm); in aldebaran_mode2_restore_hwcontext()
H A Dumc_v6_7.c101 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v6_7_ecc_info_query_correctable_error_count() local
109 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v6_7_ecc_info_query_correctable_error_count()
116 if (ras->umc_ecc.record_ce_addr_supported) { in umc_v6_7_ecc_info_query_correctable_error_count()
121 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_ceumc_addr; in umc_v6_7_ecc_info_query_correctable_error_count()
143 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v6_7_ecc_info_querry_uncorrectable_error_count() local
150 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v6_7_ecc_info_querry_uncorrectable_error_count()
228 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v6_7_ecc_info_query_error_address() local
232 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v6_7_ecc_info_query_error_address()
244 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr; in umc_v6_7_ecc_info_query_error_address()
H A Damdgpu_jpeg.c317 struct amdgpu_jpeg_ras *ras; in amdgpu_jpeg_ras_sw_init() local
319 if (!adev->jpeg.ras) in amdgpu_jpeg_ras_sw_init()
322 ras = adev->jpeg.ras; in amdgpu_jpeg_ras_sw_init()
323 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_jpeg_ras_sw_init()
329 strcpy(ras->ras_block.ras_comm.name, "jpeg"); in amdgpu_jpeg_ras_sw_init()
330 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__JPEG; in amdgpu_jpeg_ras_sw_init()
331 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON; in amdgpu_jpeg_ras_sw_init()
332 adev->jpeg.ras_if = &ras->ras_block.ras_comm; in amdgpu_jpeg_ras_sw_init()
334 if (!ras->ras_block.ras_late_init) in amdgpu_jpeg_ras_sw_init()
335 ras->ras_block.ras_late_init = amdgpu_jpeg_ras_late_init; in amdgpu_jpeg_ras_sw_init()
H A Dumc_v8_7.c56 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_7_ecc_info_query_correctable_error_count() local
63 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_7_ecc_info_query_correctable_error_count()
75 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_7_ecc_info_querry_uncorrectable_error_count() local
80 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_7_ecc_info_querry_uncorrectable_error_count()
137 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_7_ecc_info_query_error_address() local
140 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_7_ecc_info_query_error_address()
152 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr; in umc_v8_7_ecc_info_query_error_address()
H A Dumc_v8_10.c341 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_10_ecc_info_query_correctable_error_count() local
349 ecc_ce_cnt = ras->umc_ecc.ecc[eccinfo_table_idx].ce_count_lo_chip; in umc_v8_10_ecc_info_query_correctable_error_count()
360 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_10_ecc_info_query_uncorrectable_error_count() local
368 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_10_ecc_info_query_uncorrectable_error_count()
408 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_10_ecc_info_query_error_address() local
415 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_10_ecc_info_query_error_address()
428 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr; in umc_v8_10_ecc_info_query_error_address()
H A Damdgpu_virt.c250 * amdgpu_virt_rcvd_ras_interrupt() - receive ras interrupt
394 * 1) a ras bad page has been allocated (used by someone); in amdgpu_virt_ras_reserve_bps()
395 * 2) a ras bad page has been reserved (duplicate error injection in amdgpu_virt_ras_reserve_bps()
909 ratelimit_state_init(&adev->virt.ras.ras_error_cnt_rs, 5 * HZ, 1); in amdgpu_virt_init_ras()
910 ratelimit_state_init(&adev->virt.ras.ras_cper_dump_rs, 5 * HZ, 1); in amdgpu_virt_init_ras()
911 ratelimit_state_init(&adev->virt.ras.ras_chk_criti_rs, 5 * HZ, 1); in amdgpu_virt_init_ras()
913 ratelimit_set_flags(&adev->virt.ras.ras_error_cnt_rs, in amdgpu_virt_init_ras()
915 ratelimit_set_flags(&adev->virt.ras.ras_cper_dump_rs, in amdgpu_virt_init_ras()
917 ratelimit_set_flags(&adev->virt.ras.ras_chk_criti_rs, in amdgpu_virt_init_ras()
920 mutex_init(&adev->virt.ras in amdgpu_virt_init_ras()
[all...]
H A Dgfx_v11_0_3.c95 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in gfx_v11_0_3_poison_consumption_handler() local
97 ras->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE2_RESET; in gfx_v11_0_3_poison_consumption_handler()
H A Dgmc_v9_0.c1362 adev->umc.ras = &umc_v6_1_ras; in gmc_v9_0_need_reset_on_init()
1371 adev->umc.ras = &umc_v6_1_ras;
1381 adev->umc.ras = &umc_v6_7_ras; in gmc_v9_0_set_gmc_funcs()
1396 adev->umc.ras = &umc_v12_0_ras; in gmc_v9_0_set_umc_funcs()
1474 adev->mmhub.ras = &mmhub_v1_0_ras; in gmc_v9_0_set_mmhub_ras_funcs()
1477 adev->mmhub.ras = &mmhub_v9_4_ras; in gmc_v9_0_set_mmhub_ras_funcs()
1480 adev->mmhub.ras = &mmhub_v1_7_ras; in gmc_v9_0_set_gfxhub_funcs()
1484 adev->mmhub.ras = &mmhub_v1_8_ras; in gmc_v9_0_set_gfxhub_funcs()
1487 /* mmhub ras is not available */ in gmc_v9_0_set_hdp_ras_funcs()
1502 adev->hdp.ras in gmc_v9_0_set_mca_ras_funcs()
[all...]
H A Dsoc15.c508 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in soc15_asic_baco_reset() local
512 if (ras && adev->ras_enabled) in soc15_asic_baco_reset()
520 if (ras && adev->ras_enabled) in soc15_asic_baco_reset()
531 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in soc15_asic_reset_method() local
565 if (ras && adev->ras_enabled && in soc15_asic_reset_method()
1334 if (adev->nbio.ras && in soc15_common_hw_fini()
1335 adev->nbio.ras->init_ras_controller_interrupt) in soc15_common_hw_fini()
1337 if (adev->nbio.ras && in soc15_common_hw_fini()
1338 adev->nbio.ras->init_ras_err_event_athub_interrupt) in soc15_common_hw_fini()
H A Damdgpu_xgmi.c1611 struct amdgpu_xgmi_ras *ras; in amdgpu_xgmi_ras_sw_init()
1613 if (!adev->gmc.xgmi.ras) in amdgpu_xgmi_ras_sw_init()
1616 ras = adev->gmc.xgmi.ras; in amdgpu_xgmi_ras_sw_init()
1617 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_xgmi_ras_sw_init()
1619 dev_err(adev->dev, "Failed to register xgmi_wafl_pcs ras block!\n"); in amdgpu_xgmi_ras_sw_init()
1623 strcpy(ras->ras_block.ras_comm.name, "xgmi_wafl");
1624 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__XGMI_WAFL; in amdgpu_xgmi_reset_on_init_work()
1625 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_xgmi_reset_on_init_work()
1626 adev->gmc.xgmi.ras_if = &ras in amdgpu_xgmi_reset_on_init_work()
1604 struct amdgpu_xgmi_ras *ras; amdgpu_xgmi_ras_sw_init() local
[all...]
H A Damdgpu_mmhub.h77 struct amdgpu_mmhub_ras *ras;
71 struct amdgpu_mmhub_ras *ras; global() member
/linux/drivers/edac/
H A Di5100_edac.c433 unsigned ras, in i5100_handle_ce() argument
441 bank, cas, ras); in i5100_handle_ce()
455 unsigned ras, in i5100_handle_ue() argument
463 bank, cas, ras); in i5100_handle_ue()
483 unsigned ras; in i5100_read_log() local
503 ras = i5100_recmemb_ras(dw2); in i5100_read_log()
512 i5100_handle_ce(mci, chan, bank, rank, syndrome, cas, ras, msg); in i5100_read_log()
525 ras = i5100_nrecmemb_ras(dw2); in i5100_read_log()
534 i5100_handle_ue(mci, chan, bank, rank, syndrome, cas, ras, msg); in i5100_read_log()
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega20_baco.c75 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in vega20_baco_set_state() local
86 if (!ras || !adev->ras_enabled) { in vega20_baco_set_state()
/linux/net/netfilter/
H A Dnf_conntrack_h323_main.c1626 unsigned char **data, RasMessage *ras) in process_ras() argument
1628 switch (ras->choice) { in process_ras()
1631 &ras->gatekeeperRequest); in process_ras()
1634 &ras->gatekeeperConfirm); in process_ras()
1637 &ras->registrationRequest); in process_ras()
1640 &ras->registrationConfirm); in process_ras()
1643 &ras->unregistrationRequest); in process_ras()
1646 &ras->admissionRequest); in process_ras()
1649 &ras->admissionConfirm); in process_ras()
1652 &ras->locationRequest); in process_ras()
[all …]
/linux/drivers/ras/
H A DKconfig34 source "arch/x86/ras/Kconfig"
35 source "drivers/ras/amd/atl/Kconfig"
H A DMakefile2 obj-$(CONFIG_RAS) += ras.o
/linux/include/linux/netfilter/
H A Dnf_conntrack_h323_asn1.h91 int DecodeRasMessage(unsigned char *buf, size_t sz, RasMessage * ras);
/linux/arch/x86/ras/
H A DKconfig20 Add extra files to (debugfs)/ras/cec to test the correctable error

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