| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn302/ |
| H A D | dcn302_hwseq.c | 47 uint32_t power_gate = power_on ? 0 : 1; in dcn302_dpp_pg_control() local
58 DOMAIN1_POWER_GATE, power_gate); in dcn302_dpp_pg_control()
66 DOMAIN3_POWER_GATE, power_gate); in dcn302_dpp_pg_control()
74 DOMAIN5_POWER_GATE, power_gate); in dcn302_dpp_pg_control()
82 DOMAIN7_POWER_GATE, power_gate); in dcn302_dpp_pg_control()
90 DOMAIN9_POWER_GATE, power_gate); in dcn302_dpp_pg_control()
104 uint32_t power_gate = power_on ? 0 : 1; in dcn302_hubp_pg_control() local
115 DOMAIN0_POWER_GATE, power_gate); in dcn302_hubp_pg_control()
123 DOMAIN2_POWER_GATE, power_gate); in dcn302_hubp_pg_control()
131 DOMAIN4_POWER_GATE, power_gate); in dcn302_hubp_pg_control()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/pg/dcn35/ |
| H A D | dcn35_pg_cntl.c | 79 uint32_t power_gate = power_on ? 0 : 1; in pg_cntl35_dsc_pg_control() local
106 DOMAIN_POWER_GATE, power_gate); in pg_cntl35_dsc_pg_control()
114 DOMAIN_POWER_GATE, power_gate); in pg_cntl35_dsc_pg_control()
122 DOMAIN_POWER_GATE, power_gate); in pg_cntl35_dsc_pg_control()
130 DOMAIN_POWER_GATE, power_gate); in pg_cntl35_dsc_pg_control()
178 uint32_t power_gate = power_on ? 0 : 1; in pg_cntl35_hubp_dpp_pg_control() local
206 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); in pg_cntl35_hubp_dpp_pg_control()
211 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); in pg_cntl35_hubp_dpp_pg_control()
216 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); in pg_cntl35_hubp_dpp_pg_control()
221 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); in pg_cntl35_hubp_dpp_pg_control()
[all …]
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| /linux/drivers/gpu/drm/amd/pm/swsmu/ |
| H A D | amdgpu_smu.c | 255 struct smu_power_gate *power_gate = &smu_power->power_gate; in smu_dpm_set_vcn_enable() local
267 if (atomic_read(&power_gate->vcn_gated[inst]) ^ enable) in smu_dpm_set_vcn_enable()
272 atomic_set(&power_gate->vcn_gated[inst], !enable); in smu_dpm_set_vcn_enable()
281 struct smu_power_gate *power_gate = &smu_power->power_gate; in smu_dpm_set_jpeg_enable() local
290 if (atomic_read(&power_gate->jpeg_gated) ^ enable) in smu_dpm_set_jpeg_enable()
295 atomic_set(&power_gate->jpeg_gated, !enable); in smu_dpm_set_jpeg_enable()
304 struct smu_power_gate *power_gate = &smu_power->power_gate; in smu_dpm_set_vpe_enable() local
310 if (atomic_read(&power_gate->vpe_gated) ^ enable) in smu_dpm_set_vpe_enable()
315 atomic_set(&power_gate->vpe_gated, !enable); in smu_dpm_set_vpe_enable()
324 struct smu_power_gate *power_gate = &smu_power->power_gate; in smu_dpm_set_isp_enable() local
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn31/ |
| H A D | dcn31_hwseq.c | 284 uint32_t power_gate = power_on ? 0 : 1; in dcn31_dsc_pg_control() local
304 DOMAIN_POWER_GATE, power_gate); in dcn31_dsc_pg_control()
312 DOMAIN_POWER_GATE, power_gate); in dcn31_dsc_pg_control()
320 DOMAIN_POWER_GATE, power_gate); in dcn31_dsc_pg_control()
448 uint32_t power_gate = power_on ? 0 : 1; in dcn31_hubp_pg_control() local
462 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); in dcn31_hubp_pg_control()
466 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); in dcn31_hubp_pg_control()
470 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); in dcn31_hubp_pg_control()
474 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); in dcn31_hubp_pg_control()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
| H A D | dcn32_hwseq.c | 75 uint32_t power_gate = power_on ? 0 : 1; in dcn32_dsc_pg_control() local
93 DC_LOG_DSC("%s DSC power gate for inst %d", power_gate ? "enable" : "disable", dsc_inst); in dcn32_dsc_pg_control()
97 DOMAIN_POWER_GATE, power_gate); in dcn32_dsc_pg_control()
105 DOMAIN_POWER_GATE, power_gate); in dcn32_dsc_pg_control()
113 DOMAIN_POWER_GATE, power_gate); in dcn32_dsc_pg_control()
121 DOMAIN_POWER_GATE, power_gate); in dcn32_dsc_pg_control()
169 uint32_t power_gate = power_on ? 0 : 1; in dcn32_hubp_pg_control() local
183 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); in dcn32_hubp_pg_control()
187 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); in dcn32_hubp_pg_control()
191 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); in dcn32_hubp_pg_control()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| H A D | dcn20_hwseq.c | 464 uint32_t power_gate = power_on ? 0 : 1; in dcn20_dsc_pg_control() local
481 DOMAIN16_POWER_GATE, power_gate); in dcn20_dsc_pg_control()
489 DOMAIN17_POWER_GATE, power_gate); in dcn20_dsc_pg_control()
497 DOMAIN18_POWER_GATE, power_gate); in dcn20_dsc_pg_control()
505 DOMAIN19_POWER_GATE, power_gate); in dcn20_dsc_pg_control()
513 DOMAIN20_POWER_GATE, power_gate); in dcn20_dsc_pg_control()
521 DOMAIN21_POWER_GATE, power_gate); in dcn20_dsc_pg_control()
541 uint32_t power_gate = power_on ? 0 : 1; in dcn20_dpp_pg_control() local
552 DOMAIN1_POWER_GATE, power_gate); in dcn20_dpp_pg_control()
560 DOMAIN3_POWER_GATE, power_gate); in dcn20_dpp_pg_control()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| H A D | dcn10_hwseq.c | 900 uint32_t power_gate = power_on ? 0 : 1; in dcn10_dpp_pg_control() local
911 DOMAIN1_POWER_GATE, power_gate); in dcn10_dpp_pg_control()
919 DOMAIN3_POWER_GATE, power_gate); in dcn10_dpp_pg_control()
927 DOMAIN5_POWER_GATE, power_gate); in dcn10_dpp_pg_control()
935 DOMAIN7_POWER_GATE, power_gate); in dcn10_dpp_pg_control()
961 uint32_t power_gate = power_on ? 0 : 1; in dcn10_hubp_pg_control() local
972 DOMAIN0_POWER_GATE, power_gate); in dcn10_hubp_pg_control()
980 DOMAIN2_POWER_GATE, power_gate); in dcn10_hubp_pg_control()
988 DOMAIN4_POWER_GATE, power_gate); in dcn10_hubp_pg_control()
996 DOMAIN6_POWER_GATE, power_gate); in dcn10_hubp_pg_control()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/inc/ |
| H A D | amdgpu_smu.h | 471 struct smu_power_gate power_gate; member
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| /linux/drivers/gpu/drm/amd/display/dmub/inc/ |
| H A D | dmub_cmd.h | 2938 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ member
|