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Searched refs:port_clock (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/i915/display/
H A Dintel_cx0_phy.c430 (crtc_state->port_clock == 540000 || in intel_c10_get_tx_vboost_lvl()
431 crtc_state->port_clock == 810000)) in intel_c10_get_tx_vboost_lvl()
444 (crtc_state->port_clock == 540000 || in intel_c10_get_tx_term_ctl()
445 crtc_state->port_clock == 810000)) in intel_c10_get_tx_term_ctl()
2124 bool is_dp, int port_clock, int lane_count, in intel_c10pll_calc_state_from_table() argument
2134 if (intel_dpll_clock_matches(port_clock, clock)) { in intel_c10pll_calc_state_from_table()
2165 crtc_state->port_clock, crtc_state->lane_count, in intel_c10pll_calc_state()
2173 crtc_state->port_clock); in intel_c10pll_calc_state()
2377 int port_clock, in intel_c20_compute_hdmi_tmds_pll() argument
2391 if (port_clock < 25175 || port_clock > 600000) in intel_c20_compute_hdmi_tmds_pll()
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H A Dintel_lt_phy.c1204 int port_clock, in intel_lt_phy_program_port_clock_ctl() argument
1221 if (intel_lt_phy_is_hdmi(ltpll) && intel_hdmi_is_frl(port_clock)) in intel_lt_phy_program_port_clock_ctl()
1270 u32 port_clock) in intel_lt_phy_config_changed() argument
1286 if (port_clock == 1620000 && port_clock == clock) in intel_lt_phy_config_changed()
1762 if (intel_dpll_clock_matches(crtc_state->port_clock, clock)) { in intel_lt_phy_pll_calc_state()
1778 crtc_state->port_clock); in intel_lt_phy_pll_calc_state()
1912 int port_clock = intel_lt_phy_calc_port_clock(display, &dpll_hw_state->ltpll); in intel_lt_phy_pll_enable() local
1932 port_clock, lane_reversal); in intel_lt_phy_pll_enable()
1942 if (intel_lt_phy_config_changed(encoder, &dpll_hw_state->ltpll, port_clock)) { in intel_lt_phy_pll_enable()
1980 intel_ddi_link_symbol_clock(encoder, port_clock)); in intel_lt_phy_pll_enable()
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H A Dintel_ddi.c271 int clock = crtc_state->port_clock; in icl_pll_to_ddi_clk_sel()
306 static u32 ddi_buf_phy_link_rate(int port_clock) in ddi_buf_phy_link_rate() argument
308 switch (port_clock) { in ddi_buf_phy_link_rate()
326 MISSING_CASE(port_clock); in ddi_buf_phy_link_rate()
331 static int dp_phy_lane_stagger_delay(int port_clock) in dp_phy_lane_stagger_delay() argument
350 return DIV_ROUND_UP(port_clock, intel_dp_link_symbol_size(port_clock) * 1000); in dp_phy_lane_stagger_delay()
377 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); in intel_ddi_init_dp_buf_reg()
383 int delay = dp_phy_lane_stagger_delay(crtc_state->port_clock); in intel_ddi_init_dp_buf_reg()
1162 if (crtc_state->port_clock > 600000) in icl_combo_phy_loadgen_select()
1359 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); in icl_mg_phy_set_signal_levels()
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H A Dintel_pmdemand.h28 enum pipe pipe, int port_clock);
H A Dintel_dp_link_training.c1147 crtc_state->port_clock, in intel_dp_update_downspread_ctrl()
1210 } else if (crtc_state->port_clock == 810000) { in intel_dp_training_pattern()
1228 } else if (crtc_state->port_clock >= 540000) { in intel_dp_training_pattern()
1270 intel_dp_compute_rate(intel_dp, crtc_state->port_clock, in intel_dp_prepare_link_train()
1827 crtc_state->port_clock, crtc_state->lane_count); in intel_dp_link_train_phy()
1859 .rate = crtc_state->port_clock, in reduce_link_params()
1896 .rate = crtc_state->port_clock, in intel_dp_get_link_train_fallback_values()
1955 crtc_state->lane_count, crtc_state->port_clock, in intel_dp_get_link_train_fallback_values()
2248 crtc_state->port_clock, crtc_state->lane_count); in intel_dp_128b132b_link_train()
H A Dintel_dp_mst.c174 return div64_u64(mul_u32_u32(intel_dp_link_symbol_clock(crtc_state->port_clock) * 72, in intel_dp_mst_max_dpt_bpp()
189 return intel_dp_link_bw_overhead(crtc_state->port_clock, in intel_dp_mst_bw_overhead()
208 crtc_state->port_clock, in intel_dp_mst_compute_m_n()
282 mst_state->pbn_div = drm_dp_get_vc_payload_bw(crtc_state->port_clock, in intel_dp_mtp_tu_compute_config()
460 crtc_state->port_clock = max_link_config.rate; in mst_stream_compute_link_config()
497 crtc_state->port_clock = max_link_config.rate; in mst_stream_dsc_compute_link_config()
1234 crtc_state->port_clock, crtc_state->lane_count)) in intel_mst_reprobe_topology()
1240 crtc_state->port_clock, crtc_state->lane_count); in intel_mst_reprobe_topology()
H A Dintel_dp.c131 return drm_dp_is_uhbr_rate(crtc_state->port_clock); in intel_dp_is_uhbr()
1544 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, in intel_dp_compute_rate() argument
1550 if (display->platform.g4x && port_clock == 268800) in intel_dp_compute_rate()
1551 port_clock = 270000; in intel_dp_compute_rate()
1557 intel_dp_rate_select(intel_dp, port_clock); in intel_dp_compute_rate()
1559 *link_bw = drm_dp_link_rate_to_bw_code(port_clock); in intel_dp_compute_rate()
1747 pipe_config->port_clock = link_config.rate; in intel_dp_compute_link_config_wide()
1974 pipe_config->port_clock = link_config.rate; in dsc_compute_link_config()
2241 pipe_config->port_clock = max_link_config.rate; in dsc_compute_compressed_bpp()
2800 return intel_dp_link_required(crtc_state->port_clock, crtc_state->lane_count, in intel_dp_config_required_rate()
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H A Dintel_display_types.h1210 int port_clock; member
H A Dintel_cdclk.c3283 switch (crtc_state->port_clock / 2) { in skl_dpll0_vco()
H A Dintel_psr.c1315 req_ns = ((60 / crtc_state->lane_count) + 11) * 1000 / (crtc_state->port_clock / 1000); in _compute_psr2_sdp_prior_scanline_indication()