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Searched refs:pll_state (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/i915/display/
H A Dintel_cx0_phy.c1986 struct intel_cx0pll_state *pll_state, bool is_dp) in intel_cx0pll_update_ssc() argument
1993 pll_state->ssc_enabled = in intel_cx0pll_update_ssc()
2002 static bool intel_c10pll_ssc_enabled(const struct intel_c10pll_state *pll_state) in intel_c10pll_ssc_enabled() argument
2004 return memchr_inv(&pll_state->pll[C10_PLL_SSC_REG_START_IDX], in intel_c10pll_ssc_enabled()
2005 0, sizeof(pll_state->pll[0]) * C10_PLL_SSC_REG_COUNT); in intel_c10pll_ssc_enabled()
2009 struct intel_cx0pll_state *pll_state) in intel_c10pll_update_pll() argument
2014 if (pll_state->ssc_enabled) in intel_c10pll_update_pll()
2017 drm_WARN_ON(display->drm, ARRAY_SIZE(pll_state->c10.pll) < in intel_c10pll_update_pll()
2022 pll_state->c10.pll[i] = 0; in intel_c10pll_update_pll()
2025 static bool c10pll_state_is_dp(const struct intel_c10pll_state *pll_state) in c10pll_state_is_dp() argument
2030 c20pll_state_is_dp(const struct intel_c20pll_state * pll_state) c20pll_state_is_dp() argument
2035 cx0pll_state_is_dp(const struct intel_cx0pll_state * pll_state) cx0pll_state_is_dp() argument
2043 intel_c10pll_calc_port_clock(const struct intel_c10pll_state * pll_state) intel_c10pll_calc_port_clock() argument
2074 intel_c20pll_calc_port_clock(const struct intel_c20pll_state * pll_state) intel_c20pll_calc_port_clock() argument
2125 intel_c10pll_calc_state_from_table(struct intel_encoder * encoder,const struct intel_cx0pll_params * tables,bool is_dp,int port_clock,int lane_count,struct intel_cx0pll_state * pll_state) intel_c10pll_calc_state_from_table() argument
2239 struct intel_c10pll_state *pll_state = &cx0pll_state->c10; intel_c10pll_readout_hw_state() local
2279 intel_c10_pll_program(struct intel_display * display,struct intel_encoder * encoder,const struct intel_c10pll_state * pll_state) intel_c10_pll_program() argument
2378 intel_c20_compute_hdmi_tmds_pll(struct intel_display * display,int port_clock,struct intel_c20pll_state * pll_state) intel_c20_compute_hdmi_tmds_pll() argument
2638 intel_c20pll_calc_state_from_table(const struct intel_crtc_state * crtc_state,struct intel_encoder * encoder,struct intel_cx0pll_state * pll_state) intel_c20pll_calc_state_from_table() argument
2702 struct intel_c20pll_state *pll_state = &cx0pll_state->c20; intel_c20pll_readout_hw_state() local
2828 intel_c20_pll_program(struct intel_display * display,struct intel_encoder * encoder,const struct intel_c20pll_state * pll_state) intel_c20_pll_program() argument
2921 intel_program_port_clock_ctl(struct intel_encoder * encoder,const struct intel_cx0pll_state * pll_state,int port_clock,bool lane_reversal) intel_program_port_clock_ctl() argument
3170 intel_cx0pll_enable(struct intel_encoder * encoder,const struct intel_cx0pll_state * pll_state) intel_cx0pll_enable() argument
3624 intel_cx0pll_readout_hw_state(struct intel_encoder * encoder,struct intel_cx0pll_state * pll_state) intel_cx0pll_readout_hw_state() argument
3692 intel_cx0pll_calc_port_clock(struct intel_encoder * encoder,const struct intel_cx0pll_state * pll_state) intel_cx0pll_calc_port_clock() argument
3721 struct intel_cx0pll_state pll_state = {}; intel_cx0_pll_power_save_wa() local
3755 intel_c10pll_verify_clock(struct intel_display * display,int precomputed_clock,const char * pll_state_name,const struct intel_c10pll_state * pll_state,bool is_precomputed_state) intel_c10pll_verify_clock() argument
3786 struct intel_c10pll_state pll_state; intel_c10pll_verify_params() local
3801 intel_c20pll_verify_clock(struct intel_display * display,int precomputed_clock,const char * pll_state_name,const struct intel_c20pll_state * pll_state,bool is_precomputed_state) intel_c20pll_verify_clock() argument
3832 struct intel_c20pll_state pll_state; intel_c20pll_verify_params() local
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H A Dintel_lt_phy.c2243 struct intel_lt_phy_pll_state *pll_state) in intel_lt_phy_pll_readout_hw_state() argument
2253 pll_state->tbt_mode = intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)); in intel_lt_phy_pll_readout_hw_state()
2254 if (pll_state->tbt_mode) in intel_lt_phy_pll_readout_hw_state()
2260 pll_state->ssc_enabled = readout_ssc_state(encoder); in intel_lt_phy_pll_readout_hw_state()
2262 pll_state->lane_count = intel_readout_lane_count(encoder, INTEL_LT_PHY_LANE0, in intel_lt_phy_pll_readout_hw_state()
2264 pll_state->config[0] = intel_lt_phy_read(encoder, lane, LT_PHY_VDR_0_CONFIG); in intel_lt_phy_pll_readout_hw_state()
2265 pll_state->config[1] = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_1_CONFIG); in intel_lt_phy_pll_readout_hw_state()
2266 pll_state->config[2] = intel_lt_phy_read(encoder, lane, LT_PHY_VDR_2_CONFIG); in intel_lt_phy_pll_readout_hw_state()
2270 pll_state->data[i][k] = in intel_lt_phy_pll_readout_hw_state()
2301 const struct intel_lt_phy_pll_state *pll_state, in intel_lt_phy_pll_verify_clock() argument
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/linux/drivers/clk/
H A Dclk-stm32f4.c728 int pll_state; in stm32f4_pll_set_rate() local
730 pll_state = stm32f4_pll_is_enabled(hw); in stm32f4_pll_set_rate()
732 if (pll_state) in stm32f4_pll_set_rate()
745 if (pll_state) in stm32f4_pll_set_rate()
782 int pll_state, ret; in stm32f4_pll_div_set_rate() local
787 pll_state = stm32f4_pll_is_enabled(pll_div->hw_pll); in stm32f4_pll_div_set_rate()
789 if (pll_state) in stm32f4_pll_div_set_rate()
794 if (pll_state) in stm32f4_pll_div_set_rate()
857 int pll_state; in stm32f4_pll_init_ssc() local
871 pll_state = stm32f4_pll_is_enabled(hw); in stm32f4_pll_init_ssc()
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/linux/sound/soc/codecs/
H A Dwm8580.c227 struct pll_state { struct
247 struct pll_state a; argument
248 struct pll_state b;
465 struct pll_state *state; in wm8580_set_dai_pll()