| /linux/drivers/gpu/drm/sti/ |
| H A D | sti_crtc.c | 54 struct clk *compo_clk, *pix_clk; in sti_crtc_mode_set() local
64 pix_clk = compo->clk_pix_main; in sti_crtc_mode_set()
67 pix_clk = compo->clk_pix_aux; in sti_crtc_mode_set()
77 if (clk_set_rate(pix_clk, rate) < 0) { in sti_crtc_mode_set()
81 if (clk_prepare_enable(pix_clk)) { in sti_crtc_mode_set()
96 clk_disable_unprepare(pix_clk); in sti_crtc_mode_set()
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| /linux/drivers/media/v4l2-core/ |
| H A D | v4l2-dv-timings.c | 505 unsigned int pix_clk; in v4l2_detect_cvt() local
600 pix_clk = (image_width + h_blank) * hfreq; in v4l2_detect_cvt()
601 pix_clk = (pix_clk / clk_gran) * clk_gran; in v4l2_detect_cvt()
620 pix_clk = (image_width + h_blank) * hfreq; in v4l2_detect_cvt()
621 pix_clk = (pix_clk / CVT_PXL_CLK_GRAN) * CVT_PXL_CLK_GRAN; in v4l2_detect_cvt()
655 t.bt.pixelclock = pix_clk; in v4l2_detect_cvt()
725 int pix_clk; in v4l2_detect_gtf() local
787 pix_clk = (image_width + h_blank) * hfreq; in v4l2_detect_gtf()
788 pix_clk = pix_clk / GTF_PXL_CLK_GRAN * GTF_PXL_CLK_GRAN; in v4l2_detect_gtf()
819 t.bt.pixelclock = pix_clk; in v4l2_detect_gtf()
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| /linux/drivers/video/fbdev/omap/ |
| H A D | hwa742.c | 763 unsigned long *sys_clk, unsigned long *pix_clk) in calc_hwa742_clk_rates() argument
779 *pix_clk = *sys_clk / pix_div; /* HZ */ in calc_hwa742_clk_rates()
784 *sys_clk, *pix_clk); in calc_hwa742_clk_rates()
788 static int setup_tearsync(unsigned long pix_clk, int extif_div) in setup_tearsync() argument
830 hwa742.line_upd_time = (hdisp + hndp) * 1000000 / (pix_clk / 1000); in setup_tearsync()
866 hs = hs * 1000000 / (pix_clk / 1000); /* ps */ in setup_tearsync()
869 vs = vs * (hdisp + hndp) * 1000000 / (pix_clk / 1000); /* ps */ in setup_tearsync()
889 pix_clk, hwa742.pix_tx_time, hwa742.line_upd_time); in setup_tearsync()
940 unsigned long sys_clk, pix_clk; in hwa742_init() local
968 calc_hwa742_clk_rates(ext_clk, &sys_clk, &pix_clk); in hwa742_init()
[all …]
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| /linux/drivers/gpu/drm/imx/dcss/ |
| H A D | dcss-dev.c | 25 clk_prepare_enable(dcss->pix_clk); in dcss_clocks_enable()
30 clk_disable_unprepare(dcss->pix_clk); in dcss_clocks_disable()
137 {"pix", &dcss->pix_clk}, in dcss_clks_init()
158 devm_clk_put(dcss->dev, dcss->pix_clk); in dcss_clks_release()
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| H A D | dcss-dev.h | 83 struct clk *pix_clk; member
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| /linux/drivers/gpu/drm/fsl-dcu/ |
| H A D | fsl_dcu_drm_crtc.c | 63 clk_disable_unprepare(fsl_dev->pix_clk); in fsl_dcu_drm_crtc_atomic_disable()
72 clk_prepare_enable(fsl_dev->pix_clk); in fsl_dcu_drm_crtc_atomic_enable()
91 clk_set_rate(fsl_dev->pix_clk, mode->clock * 1000); in fsl_dcu_drm_crtc_mode_set_nofb()
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| /linux/drivers/gpu/drm/ingenic/ |
| H A D | ingenic-drm-drv.c | 96 struct clk *lcd_clk, *pix_clk; member
399 rate = clk_round_rate(priv->pix_clk, mode->clock * 1000); in ingenic_drm_crtc_mode_valid()
443 clk_set_rate(priv->pix_clk, in ingenic_drm_crtc_atomic_flush()
1182 priv->pix_clk = devm_clk_get(dev, "lcd_pclk"); in ingenic_drm_bind()
1183 if (IS_ERR(priv->pix_clk)) { in ingenic_drm_bind()
1185 ret = PTR_ERR(priv->pix_clk); in ingenic_drm_bind()
1345 ret = clk_prepare_enable(priv->pix_clk); in ingenic_drm_bind()
1383 parent_clk = clk_get_parent(priv->pix_clk); in ingenic_drm_bind()
1422 clk_disable_unprepare(priv->pix_clk); in ingenic_drm_bind()
1436 struct clk *parent_clk = clk_get_parent(priv->pix_clk); in ingenic_drm_unbind()
[all …]
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| /linux/drivers/gpu/drm/bridge/ |
| H A D | samsung-dsim.c | 874 unsigned long hs_clk, byte_clk, esc_clk, pix_clk; in samsung_dsim_enable_clock() local
881 pix_clk = m->clock * 1000; in samsung_dsim_enable_clock()
887 hs_clk = samsung_dsim_set_pll(dsi, DIV_ROUND_UP(pix_clk * bpp, dsi->lanes)); in samsung_dsim_enable_clock()
1172 u64 pix_clk = m->clock * 1000; in samsung_dsim_set_display_mode() local
1174 int hfp = DIV64_U64_ROUND_UP((m->hsync_start - m->hdisplay) * byte_clk, pix_clk); in samsung_dsim_set_display_mode()
1175 int hbp = DIV64_U64_ROUND_UP((m->htotal - m->hsync_end) * byte_clk, pix_clk); in samsung_dsim_set_display_mode()
1176 int hsa = DIV64_U64_ROUND_UP((m->hsync_end - m->hsync_start) * byte_clk, pix_clk); in samsung_dsim_set_display_mode()
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| /linux/drivers/gpu/drm/amd/display/dc/link/protocols/ |
| H A D | link_ddc.c | 541 uint32_t pix_clk, in write_scdc_data() argument
544 bool over_340_mhz = pix_clk > 340000 ? 1 : 0; in write_scdc_data()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_resource.c | 3684 uint32_t pix_clk = timing->pix_clk_100hz; in get_norm_pix_clk() local
3685 uint32_t normalized_pix_clk = pix_clk; in get_norm_pix_clk()
3688 pix_clk /= 2; in get_norm_pix_clk()
3693 normalized_pix_clk = pix_clk; in get_norm_pix_clk()
3696 normalized_pix_clk = (pix_clk * 30) / 24; in get_norm_pix_clk()
3699 normalized_pix_clk = (pix_clk * 36) / 24; in get_norm_pix_clk()
3702 normalized_pix_clk = (pix_clk * 42) / 24; in get_norm_pix_clk()
3705 normalized_pix_clk = (pix_clk * 48) / 24; in get_norm_pix_clk()
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| /linux/drivers/gpu/drm/radeon/ |
| H A D | r100.c | 3170 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff; in r100_bandwidth_update() local
3287 pix_clk.full = 0; in r100_bandwidth_update()
3292 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */ in r100_bandwidth_update()
3293 pix_clk.full = dfixed_div(pix_clk, temp_ff); in r100_bandwidth_update()
3295 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff); in r100_bandwidth_update()
3498 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff); in r100_bandwidth_update()
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| /linux/include/video/ |
| H A D | imx-ipu-v3.h | |