| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_dp_tunnel.c | 141 static int allocate_initial_tunnel_bw_for_pipes(struct intel_dp *intel_dp, u8 pipe_mask) in allocate_initial_tunnel_bw_for_pipes() argument
149 for_each_intel_crtc_in_pipe_mask(display, crtc, pipe_mask) { in allocate_initial_tunnel_bw_for_pipes()
180 u8 pipe_mask; in allocate_initial_tunnel_bw() local
183 err = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask); in allocate_initial_tunnel_bw()
187 return allocate_initial_tunnel_bw_for_pipes(intel_dp, pipe_mask); in allocate_initial_tunnel_bw()
359 u8 pipe_mask; in intel_dp_tunnel_resume()
393 pipe_mask = 0; in intel_dp_tunnel_resume()
398 pipe_mask |= BIT(crtc->pipe);
401 err = allocate_initial_tunnel_bw_for_pipes(intel_dp, pipe_mask); in get_inherited_tunnel()
519 u32 pipe_mask;
341 u8 pipe_mask; intel_dp_tunnel_resume() local
501 u32 pipe_mask; intel_dp_tunnel_atomic_add_group_state() local
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| H A D | g4x_dp.c | 1388 intel_encoder->pipe_mask = BIT(PIPE_C); in g4x_dp_init()
1390 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_dp_init()
1392 intel_encoder->pipe_mask = ~0; in g4x_dp_init()
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| H A D | intel_lvds.c | 931 encoder->pipe_mask = BIT(PIPE_B); in intel_lvds_init()
933 encoder->pipe_mask = ~0; in intel_lvds_init()
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| H A D | intel_dvo.c | 515 encoder->pipe_mask = ~0; in intel_dvo_init()
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| H A D | intel_display_irq.c | 2251 u8 pipe_mask) in valleyview_enable_display_irqs()
2264 for_each_pipe_masked(display, pipe, pipe_mask) in valleyview_disable_display_irqs()
2273 u8 pipe_mask) in valleyview_disable_display_irqs()
2284 for_each_pipe_masked(display, pipe, pipe_mask) in ilk_de_irq_postinstall()
2172 gen8_irq_power_well_post_enable(struct intel_display * display,u8 pipe_mask) gen8_irq_power_well_post_enable() argument
2194 gen8_irq_power_well_pre_disable(struct intel_display * display,u8 pipe_mask) gen8_irq_power_well_pre_disable() argument
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| H A D | intel_dp.c | 5925 u8 *pipe_mask) in intel_dp_handle_link_service_irq()
5932 *pipe_mask = 0; in intel_dp_handle_link_service_irq()
5962 *pipe_mask |= BIT(crtc->pipe);
5987 u8 pipe_mask; in intel_dp_short_pulse()
6001 ret = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask); in intel_dp_short_pulse()
6005 if (pipe_mask == 0) in intel_dp_short_pulse()
6016 ret = intel_modeset_commit_pipes(display, pipe_mask, ctx); in intel_dp_short_pulse()
5770 intel_dp_get_active_pipes(struct intel_dp * intel_dp,struct drm_modeset_acquire_ctx * ctx,u8 * pipe_mask) intel_dp_get_active_pipes() argument
5832 u8 pipe_mask; intel_dp_retrain_link() local
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| H A D | intel_display_types.h | 169 u8 pipe_mask; member
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| H A D | intel_tv.c | 2016 intel_encoder->pipe_mask = ~0; in intel_tv_init()
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| H A D | intel_display.c | 556 * if in case pipe A is disabled, use the first pipe from pipe_mask. in intel_plane_fb_max_stride()
3498 return pipes & DISPLAY_RUNTIME_INFO(display)->pipe_mask; in joiner_pipes()
5662 u8 pipe_mask, in intel_modeset_commit_pipes()
5676 for_each_intel_crtc_in_pipe_mask(display, crtc, pipe_mask) { in intel_modeset_commit_pipes()
7797 for_each_intel_crtc_in_pipe_mask(display, crtc, encoder->pipe_mask) in intel_encoder_possible_clones()
5658 intel_modeset_commit_pipes(struct intel_display * display,u8 pipe_mask,struct drm_modeset_acquire_ctx * ctx) intel_modeset_commit_pipes() argument
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| H A D | icl_dsi.c | 1972 encoder->pipe_mask = ~0; in icl_dsi_init()
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| H A D | intel_sdvo.c | 3053 intel_sdvo->base.pipe_mask = ~0; in intel_sdvo_output_cleanup()
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| /linux/drivers/usb/renesas_usbhs/ |
| H A D | common.c | 276 u16 pipe_mask = (u16)GENMASK(usbhs_get_dparam(priv, pipe_size), 0); in usbhs_xxxsts_clear() local
278 usbhs_write(priv, sts_reg, ~(1 << bit) & pipe_mask); in usbhs_xxxsts_clear()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/ |
| H A D | dml21_utils.c | 438 static_base_state->stream_v1.base.pipe_mask |= (1 << dc_pipe_idx); in dml21_build_fams2_stream_programming_v2()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 3144 cs->offload_streams[stream_idx].payloads[payload_idx].pipe_mask |= (1u << pipe->pipe_idx); in dcn401_program_all_writeback_pipes_in_tree_sequence()
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