| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_lib.h | 56 const unsigned int num_pipes,
74 const unsigned int num_pipes,
79 const unsigned int num_pipes,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | display_rq_dlg_calc_32.h | 47 const unsigned int num_pipes,
67 const unsigned int num_pipes,
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| /linux/drivers/gpu/drm/radeon/ |
| H A D | r420.c | 94 unsigned num_pipes; in r420_pipes_init() local
105 num_pipes = ((gb_pipe_select >> 12) & 3) + 1; in r420_pipes_init()
110 num_pipes = 1; in r420_pipes_init()
112 rdev->num_gb_pipes = num_pipes; in r420_pipes_init()
114 switch (num_pipes) { in r420_pipes_init()
117 num_pipes = 1; in r420_pipes_init()
132 WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1); in r420_pipes_init()
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_mes.c | 106 int i, r, num_pipes, num_queues = 0; in amdgpu_mes_init() local
132 num_pipes = adev->gfx.me.num_pipe_per_me * adev->gfx.me.num_me; in amdgpu_mes_init()
133 if (num_pipes > AMDGPU_MES_MAX_GFX_PIPES) in amdgpu_mes_init()
135 num_pipes, AMDGPU_MES_MAX_GFX_PIPES); in amdgpu_mes_init()
138 if (i >= num_pipes) in amdgpu_mes_init()
144 num_pipes = adev->gfx.mec.num_pipe_per_mec * adev->gfx.mec.num_mec; in amdgpu_mes_init()
145 if (num_pipes > AMDGPU_MES_MAX_COMPUTE_PIPES) in amdgpu_mes_init()
147 num_pipes, AMDGPU_MES_MAX_COMPUTE_PIPES); in amdgpu_mes_init()
162 num_pipes = adev->sdma.num_inst_per_xcc ? in amdgpu_mes_init()
164 if (num_pipes > AMDGPU_MES_MAX_SDMA_PIPES) in amdgpu_mes_init()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | dml2_wrapper_fpu.c | 67 unsigned int num_pipes = 0; in map_hw_resources() local
88 …dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[num_pipes] = dml2->v20.scratch.… in map_hw_resources()
89 dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[num_pipes] = true; in map_hw_resources()
90 …dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id[num_pipes] = dml2->v20.scratch.d… in map_hw_resources()
91 dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id_valid[num_pipes] = true; in map_hw_resources()
92 num_pipes++; in map_hw_resources()
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| /linux/include/drm/intel/ |
| H A D | intel_lpe_audio.h | 45 int num_pipes; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| H A D | display_rq_dlg_calc_21.h | 65 const unsigned int num_pipes,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | display_rq_dlg_calc_20.h | 65 const unsigned int num_pipes,
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| H A D | display_rq_dlg_calc_20v2.h | 65 const unsigned int num_pipes,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | display_rq_dlg_calc_31.h | 61 const unsigned int num_pipes,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| H A D | display_rq_dlg_calc_314.h | 62 const unsigned int num_pipes,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | display_rq_dlg_calc_30.h | 61 const unsigned int num_pipes,
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/tests/ |
| H A D | amdgpu_dm_plane_test.c | 538 adev->gfx.config.gb_addr_config_fields.num_pipes = 2; in dm_test_fill_gfx12_plane_attributes_from_modifiers()
588 adev->gfx.config.gb_addr_config_fields.num_pipes = 2; in dm_test_fill_gfx9_plane_attributes_from_modifiers()
953 adev->gfx.config.gb_addr_config_fields.num_pipes = 4; in dm_test_fill_gfx9_tiling_info_from_device_pre_10_3()
966 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.num_pipes, 4U); in dm_test_fill_gfx9_tiling_info_from_device_pre_10_3()
990 adev->gfx.config.gb_addr_config_fields.num_pipes = 2; in dm_test_fill_gfx9_tiling_info_from_device_10_3_plus()
1001 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.num_pipes, 2U); in dm_test_fill_gfx9_tiling_info_from_device_10_3_plus()
1026 adev->gfx.config.gb_addr_config_fields.num_pipes = 4; in dm_test_fill_gfx9_tiling_info_from_modifier_linear()
1038 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.num_pipes, 4U); in dm_test_fill_gfx9_tiling_info_from_modifier_linear()
1064 adev->gfx.config.gb_addr_config_fields.num_pipes = 4; in dm_test_fill_gfx9_tiling_info_from_modifier_pre_nv()
1083 KUNIT_EXPECT_EQ(test, tiling_info.gfx9.num_pipes, 32U); in dm_test_fill_gfx9_tiling_info_from_modifier_pre_nv()
[all …]
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| /linux/sound/x86/ |
| H A D | intel_hdmi_audio.h | 120 int num_pipes;
140 int num_pipes; global() member
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| H A D | intel_hdmi_audio.c | 41 for ((pipe) = 0; (pipe) < (card_ctx)->num_pipes; (pipe)++)
1684 card_ctx->num_pipes = pdata->num_pipes; in __hdmi_lpe_audio_probe()
1728 card_ctx->num_pipes = pdata->num_pipes; in __hdmi_lpe_audio_probe()
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| /linux/drivers/staging/media/atomisp/pci/ |
| H A D | sh_css.c | 124 int num_pipes; member
1208 for (i = 0; i < stream->num_pipes; i++) { in sh_css_invalidate_shading_tables()
1521 for (i = 1; i < stream->num_pipes; i++) in map_sp_threads()
1607 for (i = 1; i < stream->num_pipes && 0 == err; i++) { in create_host_pipeline_structure()
1738 for (i = 1; i < stream->num_pipes && 0 == err; i++) { in create_host_pipeline()
3975 n = event->pipe->stream->num_pipes; in ia_css_dequeue_psys_event()
4097 for (i = 1; i < stream->num_pipes && 0 == err ; i++) { in sh_css_pipe_start()
4153 for (i = 1; i < stream->num_pipes; i++) { in sh_css_pipe_start()
7769 find_pipe(struct ia_css_pipe *pipes[], unsigned int num_pipes, in find_pipe() argument
7775 for (i = 0; i < num_pipes; i++) { in find_pipe()
[all …]
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| H A D | ia_css_stream_public.h | 171 int num_pipes,
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_plane.c | 236 tiling_info->gfx9.num_pipes = in amdgpu_dm_plane_fill_gfx6_tiling_info_from_modifier()
237 adev->gfx.config.gb_addr_config_fields.num_pipes; in amdgpu_dm_plane_fill_gfx6_tiling_info_from_modifier()
270 tiling_info->gfx9.num_pipes = 1u << pipes_log2;
431 int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); in amdgpu_dm_plane_fill_gfx12_attrs_from_modifiers()
721 int pipes = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); in amdgpu_dm_plane_add_gfx6_modifiers()
828 int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); in amdgpu_dm_plane_add_gfx9_modifiers()
900 int num_pipes = 0; in amdgpu_dm_plane_add_gfx10_3_modifiers()
919 num_pipes = 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PIPES); in amdgpu_dm_plane_add_gfx11_modifiers()
920 pipe_xor_bits = ilog2(num_pipes); in amdgpu_dm_plane_add_gfx11_modifiers()
925 if (num_pipes > 1 in amdgpu_dm_plane_add_gfx11_modifiers()
918 int num_pipes = 0; amdgpu_dm_plane_add_gfx11_modifiers() local
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | dwb.h | 144 unsigned int num_pipes; /* number of DWB pipes */ member
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| H A D | dcn321_resource.c | 1809 uint32_t num_pipes = 4; in dcn321_resource_construct() local
1839 num_pipes = pool->base.res_cap->num_timing_generator; in dcn321_resource_construct()
1844 num_pipes--; in dcn321_resource_construct()
1855 dcn3_21_ip.max_num_dpp = num_pipes; in dcn321_resource_construct()
1856 dcn3_21_ip.max_num_otg = num_pipes; in dcn321_resource_construct()
1864 pool->base.timing_generator_count = num_pipes; in dcn321_resource_construct()
1865 pool->base.pipe_count = num_pipes; in dcn321_resource_construct()
1866 pool->base.mpcc_count = num_pipes; in dcn321_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.c | 2314 uint32_t num_pipes = 4; in dcn32_resource_construct() local
2343 num_pipes = pool->base.res_cap->num_timing_generator; in dcn32_resource_construct()
2348 num_pipes--; in dcn32_resource_construct()
2359 dcn3_2_ip.max_num_dpp = num_pipes; in dcn32_resource_construct()
2360 dcn3_2_ip.max_num_otg = num_pipes; in dcn32_resource_construct()
2368 pool->base.timing_generator_count = num_pipes; in dcn32_resource_construct()
2369 pool->base.pipe_count = num_pipes; in dcn32_resource_construct()
2370 pool->base.mpcc_count = num_pipes; in dcn32_resource_construct()
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| /linux/drivers/gpu/drm/omapdrm/ |
| H A D | omap_irq.c | 221 for (id = 0; id < priv->num_pipes; id++) { in omap_irq_handler()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn60/ |
| H A D | dcn60_resource.c | 1962 uint32_t num_pipes = 4; in dcn60_resource_construct() local
1991 num_pipes = pool->base.res_cap->num_timing_generator; in dcn60_resource_construct()
1996 num_pipes--; in dcn60_resource_construct()
2010 pool->base.timing_generator_count = num_pipes; in dcn60_resource_construct()
2011 pool->base.pipe_count = num_pipes; in dcn60_resource_construct()
2012 pool->base.mpcc_count = num_pipes; in dcn60_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| H A D | dcn401_resource.c | 2020 uint32_t num_pipes = 4; in dcn401_resource_construct() local
2049 num_pipes = pool->base.res_cap->num_timing_generator; in dcn401_resource_construct()
2054 num_pipes--; in dcn401_resource_construct()
2068 pool->base.timing_generator_count = num_pipes; in dcn401_resource_construct()
2069 pool->base.pipe_count = num_pipes; in dcn401_resource_construct()
2070 pool->base.mpcc_count = num_pipes; in dcn401_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_dwb.c | 56 caps->num_pipes = 1; in dwb2_get_caps()
|