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Searched refs:mtdcr (Results 1 – 7 of 7) sorted by relevance

/linux/arch/powerpc/platforms/44x/
H A Dsoc.c35 mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, addr); in l2c_diag()
36 mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_DIAG); in l2c_diag()
62 mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, 0); in l2c_error_handler()
63 mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE); in l2c_error_handler()
126 mtdcr(dcrbase_isram + DCRN_SRAM0_DPC, in ppc4xx_l2c_probe()
128 mtdcr(dcrbase_isram + DCRN_SRAM0_SB0CR, in ppc4xx_l2c_probe()
130 mtdcr(dcrbase_isram + DCRN_SRAM0_SB1CR, in ppc4xx_l2c_probe()
132 mtdcr(dcrbase_isram + DCRN_SRAM0_SB2CR, in ppc4xx_l2c_probe()
134 mtdcr(dcrbase_isram + DCRN_SRAM0_SB3CR, in ppc4xx_l2c_probe()
141 mtdcr(dcrbase_l2c + DCRN_L2C0_CFG, r); in ppc4xx_l2c_probe()
[all …]
H A Dfsp2.h249 mtdcr(DCRN_CMU_ADDR, reg); \
250 mtdcr(DCRN_CMU_DATA, data); \
255 mtdcr(DCRN_CMU_ADDR, reg); \
261 mtdcr(DCRN_L2CDCRAI, reg); \
262 mtdcr(DCRN_L2CDCRDI, data); \
267 mtdcr(DCRN_L2CDCRAI, reg); \
/linux/arch/powerpc/boot/
H A Ddcr.h11 #define mtdcr(rn, val) \ macro
29 mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
32 mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
33 mtdcr(DCRN_SDRAM0_CFGDATA, data); })
171 mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
174 mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
175 mtdcr(DCRN_SDR0_CONFIG_DATA, data); })
189 mtdcr(DCRN_CPR0_CFGADDR, offset); \
192 mtdcr(DCRN_CPR0_CFGADDR, offset); \
193 mtdcr(DCRN_CPR0_CFGDATA, data); })
H A D4xx.c283 mtdcr(DCRN_MAL0_CFG, MAL_RESET); in ibm4xx_quiesce_eth()
299 mtdcr(DCRN_EBC0_CFGADDR, EBC_BXCR(i)); in ibm4xx_fixup_ebc_ranges()
/linux/arch/powerpc/sysdev/
H A Ddcr-low.S37 mtdcr 0,r4; blr
42 mtdcr dcr,r4; blr
/linux/arch/powerpc/include/asm/
H A Ddcr-native.h30 #define dcr_write_native(host, dcr_n, value) mtdcr(dcr_n + host.base, value)
64 #define mtdcr(rn, v) \ macro
/linux/arch/powerpc/kernel/
H A Dcpu_setup_44x.S66 mtdcr DCRN_PLB4A0_ACR,r3