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Searched refs:mpcc_inst (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_mpc.c62 static void mpc201_init_mpcc(struct mpcc *mpcc, int mpcc_inst) in mpc201_init_mpcc() argument
64 mpcc->mpcc_id = mpcc_inst; in mpc201_init_mpcc()
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dpg_cntl.h45 void (*mpcc_pg_control)(struct pg_cntl *pg_cntl, unsigned int mpcc_inst, bool power_on);
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
H A Ddcn30_hwseq.c447 ASSERT(wb_info->mpcc_inst >= 0); in dcn30_set_writeback()
448 ASSERT(wb_info->mpcc_inst < (int)dc->res_pool->mpcc_count); in dcn30_set_writeback()
454 wb_info->dwb_pipe_inst, wb_info->mpcc_inst); in dcn30_set_writeback()
469 wb_info->mpcc_inst); in dcn30_update_writeback()
547 wb_info->mpcc_inst); in dcn30_enable_writeback()
613 wb_info.mpcc_inst = -1; in dcn30_program_all_writeback_pipes_in_tree()
621 wb_info.mpcc_inst = pipe_ctx->plane_res.mpcc_inst; in dcn30_program_all_writeback_pipes_in_tree()
626 if (wb_info.mpcc_inst == -1) { in dcn30_program_all_writeback_pipes_in_tree()
/linux/drivers/gpu/drm/amd/display/dc/pg/dcn42/
H A Ddcn42_pg_cntl.c379 unsigned int mpcc_inst, bool power_on) in pg_cntl42_mpcc_pg_control() argument
384 if (mpcc_inst < MAX_PIPES) in pg_cntl42_mpcc_pg_control()
385 pg_cntl->pg_pipe_res_enable[PG_MPCC][mpcc_inst] = power_on; in pg_cntl42_mpcc_pg_control()
/linux/drivers/gpu/drm/amd/display/dc/pg/dcn35/
H A Ddcn35_pg_cntl.h179 unsigned int mpcc_inst, bool power_on);
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_resource.c2706 split_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[i]->inst; in acquire_first_split_pipe()
4054 pipe_ctx->plane_res.mpcc_inst = (uint8_t)pool->dpps[id_src[i]]->inst; in acquire_resource_from_hw_enabled_state()
4059 pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s); in acquire_resource_from_hw_enabled_state()
4062 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id = in acquire_resource_from_hw_enabled_state()
4066 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot = in acquire_resource_from_hw_enabled_state()
4198 pipe_ctx->plane_res.mpcc_inst = (uint8_t)pool->dpps[pipe_idx]->inst; in acquire_otg_master_pipe_for_stream()
5954 sec_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[pipe_idx]->inst; in dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy()
H A Ddc.c838 .mpcc_id = pipes->plane_res.mpcc_inst, in dc_stream_set_gamut_remap()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.c2952 idle_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[idle_pipe->pipe_idx]->inst; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
3011 free_pipe->plane_res.mpcc_inst = in dcn32_acquire_free_pipe_as_secondary_dpp_pipe()
3044 free_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[free_pipe_idx]->inst; in dcn32_acquire_free_pipe_as_secondary_opp_head()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c1699 sec_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[pipe_idx]->inst; in dcn30_split_stream_for_mpc_or_odm()