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Searched refs:mmUVD_GPCOM_VCPU_DATA1 (Results 1 – 20 of 20) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_d.h44 #define mmUVD_GPCOM_VCPU_DATA1 0x3BC5 macro
H A Duvd_4_2_d.h32 #define mmUVD_GPCOM_VCPU_DATA1 0x3bc5 macro
H A Duvd_3_1_d.h32 #define mmUVD_GPCOM_VCPU_DATA1 0x3bc5 macro
H A Duvd_5_0_d.h32 #define mmUVD_GPCOM_VCPU_DATA1 0x3bc5 macro
H A Duvd_6_0_d.h32 #define mmUVD_GPCOM_VCPU_DATA1 0x3bc5 macro
H A Duvd_7_0_offset.h58 #define mmUVD_GPCOM_VCPU_DATA1 … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v6_0.c933 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v6_0_ring_emit_fence()
940 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v6_0_ring_emit_fence()
1070 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v6_0_ring_emit_wreg()
1083 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v6_0_ring_emit_vm_flush()
1098 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v6_0_ring_emit_pipeline_sync()
H A Duvd_v4_2.c486 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v4_2_ring_emit_fence()
493 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v4_2_ring_emit_fence()
H A Duvd_v3_1.c119 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v3_1_ring_emit_fence()
126 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v3_1_ring_emit_fence()
H A Dvcn_v1_0.c54 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1),
173 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1); in vcn_v1_0_sw_init()
1521 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); in vcn_v1_0_dec_ring_emit_fence()
1531 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); in vcn_v1_0_dec_ring_emit_fence()
1581 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); in vcn_v1_0_dec_ring_emit_reg_wait()
1615 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); in vcn_v1_0_dec_ring_emit_wreg()
H A Duvd_v5_0.c502 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v5_0_ring_emit_fence()
509 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v5_0_ring_emit_fence()
H A Duvd_v7_0.c1194 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); in uvd_v7_0_ring_emit_fence()
1204 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); in uvd_v7_0_ring_emit_fence()
1376 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); in uvd_v7_0_ring_emit_wreg()
1392 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); in uvd_v7_0_ring_emit_reg_wait()
H A Dvcn_v2_0.c62 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1),
190 adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1); in vcn_v2_0_sw_init()
H A Dvcn_v2_5.c65 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1),
217 adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA1); in vcn_v2_5_sw_init()
H A Dvcn_v3_0.c69 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1),
210 adev->vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1); in vcn_v3_0_sw_init()
H A Damdgpu_uvd.c1011 case mmUVD_GPCOM_VCPU_DATA1: in amdgpu_uvd_cs_reg()
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h142 #define mmUVD_GPCOM_VCPU_DATA1 … macro
H A Dvcn_2_5_offset.h515 #define mmUVD_GPCOM_VCPU_DATA1 … macro
H A Dvcn_2_0_0_offset.h814 #define mmUVD_GPCOM_VCPU_DATA1 … macro
H A Dvcn_3_0_0_offset.h831 #define mmUVD_GPCOM_VCPU_DATA1 … macro