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Searched refs:mfdcr (Results 1 – 9 of 9) sorted by relevance

/linux/arch/powerpc/platforms/44x/
H A Dfsp2.c72 pr_err("GESR0: 0x%08x\n", mfdcr(base + PLB4OPB_GESR0)); in show_plbopb_regs()
73 pr_err("GESR1: 0x%08x\n", mfdcr(base + PLB4OPB_GESR1)); in show_plbopb_regs()
74 pr_err("GESR2: 0x%08x\n", mfdcr(base + PLB4OPB_GESR2)); in show_plbopb_regs()
75 pr_err("GEARU: 0x%08x\n", mfdcr(base + PLB4OPB_GEARU)); in show_plbopb_regs()
76 pr_err("GEAR: 0x%08x\n", mfdcr(base + PLB4OPB_GEAR)); in show_plbopb_regs()
86 pr_err("BC_SHD: 0x%08x\n", mfdcr(DCRN_PLB6_SHD)); in bus_err_handler()
87 pr_err("BC_ERR: 0x%08x\n", mfdcr(DCRN_PLB6_ERR)); in bus_err_handler()
90 pr_err("ESR: 0x%08x\n", mfdcr(DCRN_PLB6PLB4_ESR)); in bus_err_handler()
91 pr_err("EARH: 0x%08x\n", mfdcr(DCRN_PLB6PLB4_EARH)); in bus_err_handler()
92 pr_err("EARL: 0x%08x\n", mfdcr(DCRN_PLB6PLB4_EARL)); in bus_err_handler()
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H A Dsoc.c37 while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC)) in l2c_diag()
40 return mfdcr(dcrbase_l2c + DCRN_L2C0_DATA); in l2c_diag()
45 u32 sr = mfdcr(dcrbase_l2c + DCRN_L2C0_SR); in l2c_error_handler()
127 mfdcr(dcrbase_isram + DCRN_SRAM0_DPC) & ~SRAM_DPC_ENABLE); in ppc4xx_l2c_probe()
129 mfdcr(dcrbase_isram + DCRN_SRAM0_SB0CR) & ~SRAM_SBCR_BU_MASK); in ppc4xx_l2c_probe()
131 mfdcr(dcrbase_isram + DCRN_SRAM0_SB1CR) & ~SRAM_SBCR_BU_MASK); in ppc4xx_l2c_probe()
133 mfdcr(dcrbase_isram + DCRN_SRAM0_SB2CR) & ~SRAM_SBCR_BU_MASK); in ppc4xx_l2c_probe()
135 mfdcr(dcrbase_isram + DCRN_SRAM0_SB3CR) & ~SRAM_SBCR_BU_MASK); in ppc4xx_l2c_probe()
138 r = mfdcr(dcrbase_l2c + DCRN_L2C0_CFG) & in ppc4xx_l2c_probe()
147 while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC)) in ppc4xx_l2c_probe()
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H A Duic.c64 er = mfdcr(uic->dcrbase + UIC_ER); in uic_unmask_irq()
78 er = mfdcr(uic->dcrbase + UIC_ER); in uic_mask_irq()
104 er = mfdcr(uic->dcrbase + UIC_ER); in uic_mask_ack_irq()
152 tr = mfdcr(uic->dcrbase + UIC_TR); in uic_set_irq_type()
153 pr = mfdcr(uic->dcrbase + UIC_PR); in uic_set_irq_type()
211 msr = mfdcr(uic->dcrbase + UIC_MSR); in uic_irq_cascade()
327 msr = mfdcr(primary_uic->dcrbase + UIC_MSR); in uic_get_irq()
H A Dfsp2.h256 data = mfdcr(DCRN_CMU_DATA); \
268 data = mfdcr(DCRN_L2CDCRDI); \
/linux/arch/powerpc/boot/
H A D4xx.c106 banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B0BAS)); in ibm440spe_fixup_memsize()
109 banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B1BAS)); in ibm440spe_fixup_memsize()
112 banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B2BAS)); in ibm440spe_fixup_memsize()
115 banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B3BAS)); in ibm440spe_fixup_memsize()
284 while (mfdcr(DCRN_MAL0_CFG) & MAL_RESET) in ibm4xx_quiesce_eth()
300 bxcr = mfdcr(DCRN_EBC0_CFGDATA); in ibm4xx_fixup_ebc_ranges()
320 u32 sys0 = mfdcr(DCRN_CPC0_SYS0); in ibm440gp_fixup_clocks()
321 u32 cr0 = mfdcr(DCRN_CPC0_CR0); in ibm440gp_fixup_clocks()
H A Ddcr.h5 #define mfdcr(rn) \ macro
30 mfdcr(DCRN_SDRAM0_CFGDATA); })
172 mfdcr(DCRN_SDR0_CONFIG_DATA); })
190 mfdcr(DCRN_CPR0_CFGDATA); })
/linux/arch/powerpc/sysdev/
H A Ddcr-low.S35 mfdcr r3,0; blr
41 mfdcr r3,dcr; blr
/linux/arch/powerpc/include/asm/
H A Ddcr-native.h29 #define dcr_read_native(host, dcr_n) mfdcr(dcr_n + host.base)
53 #define mfdcr(rn) \ macro
/linux/arch/powerpc/kernel/
H A Dcpu_setup_44x.S63 mfdcr r3,DCRN_PLB4A0_ACR