Searched refs:memclk_mhz (Results 1 – 9 of 9) sorted by relevance
194 uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz; in dcn32_build_wm_range_table_fpu()207 if (clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz) in dcn32_build_wm_range_table_fpu()208 setb_min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz; in dcn32_build_wm_range_table_fpu()246 …mmy_pstate_table[0].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz * 16; in dcn32_build_wm_range_table_fpu()248 …mmy_pstate_table[1].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[1].memclk_mhz * 16; in dcn32_build_wm_range_table_fpu()250 …mmy_pstate_table[2].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz * 16; in dcn32_build_wm_range_table_fpu()252 …mmy_pstate_table[3].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[3].memclk_mhz * 16; in dcn32_build_wm_range_table_fpu()2483 dc->clk_mgr->bw_params->clk_table.entries[min_dram_speed_mts_offset].memclk_mhz * 16; in dcn32_calculate_wm_and_dlg_fpu()2644 if (bw_params->clk_table.entries[i].memclk_mhz > max_uclk_mhz) in dcn32_patch_dpm_table()2645 max_uclk_mhz = bw_params->clk_table.entries[i].memclk_mhz; in dcn32_patch_dpm_table()[all …]
632 s[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * in dcn31_update_bw_bounding_box_fpu()700 …dcn3_15_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->ent… in dcn315_update_bw_bounding_box_fpu()772 s[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * in dcn316_update_bw_bounding_box_fpu()
76 dml_clk_table->uclk.clk_values_khz[i] = dc_clk_table->entries[i].memclk_mhz * 1000; in dcn42_convert_dc_clock_table_to_soc_bb_clock_table()
2159 if (bw_params->clk_table.entries[0].memclk_mhz) { in dcn30_update_bw_bounding_box()2197 dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16, in dcn30_update_bw_bounding_box()2210 bw_params->clk_table.entries[j].memclk_mhz * 16; in dcn30_update_bw_bounding_box()2221 bw_params->clk_table.entries[j].memclk_mhz * 16; in dcn30_update_bw_bounding_box()2237 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn30_update_bw_bounding_box()2252 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn30_update_bw_bounding_box()
996 …clk_mgr_base->bw_params->clk_table.entries[dpm_clks->NumMemPstatesEnabled - 1 - i].memclk_mhz = dp… in dcn42_get_smu_clocks()
5862 static void blank_and_force_memclk(struct dc *dc, bool apply, unsigned int memclk_mhz) in blank_and_force_memclk() argument5886 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, memclk_mhz); in blank_and_force_memclk()5888 dc->clk_mgr->funcs->set_min_memclk(dc->clk_mgr, memclk_mhz); in blank_and_force_memclk()5929 if (dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz > maxDPM) in dc_enable_dcmode_clk_limit()5930 maxDPM = dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz; in dc_enable_dcmode_clk_limit()
2384 low_pstate_lvl.dram_speed_mts = clk_table->entries[0].memclk_mhz * 2; in construct_low_pstate_lvl()2437 s[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2; in dcn21_update_bw_bounding_box_fpu()
65 clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000; in dcn401_initialize_min_clocks()1304 …k_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz); in dcn401_prepare_bandwidth()
543 dml2->config.bbox_overrides.clks_table.clk_entries[i].memclk_mhz * transactions_per_mem_clock; in dml2_init_soc_states()