xref: /linux/drivers/net/ethernet/microchip/sparx5/sparx5_main.c (revision 06103dccbbd29408255a409f6f98f7f02387dc93)
1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
3  *
4  * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
5  *
6  * The Sparx5 Chip Register Model can be browsed at this location:
7  * https://github.com/microchip-ung/sparx-5_reginfo
8  */
9 #include <linux/module.h>
10 #include <linux/device.h>
11 #include <linux/netdevice.h>
12 #include <linux/platform_device.h>
13 #include <linux/interrupt.h>
14 #include <linux/of.h>
15 #include <linux/of_net.h>
16 #include <linux/of_mdio.h>
17 #include <net/switchdev.h>
18 #include <linux/etherdevice.h>
19 #include <linux/io.h>
20 #include <linux/printk.h>
21 #include <linux/iopoll.h>
22 #include <linux/mfd/syscon.h>
23 #include <linux/regmap.h>
24 #include <linux/types.h>
25 #include <linux/reset.h>
26 
27 #include "lan969x/lan969x.h" /* for lan969x match data */
28 
29 #include "sparx5_main_regs.h"
30 #include "sparx5_main.h"
31 #include "sparx5_port.h"
32 #include "sparx5_qos.h"
33 #include "sparx5_vcap_ag_api.h"
34 #include "sparx5_vcap_impl.h"
35 
36 const struct sparx5_regs *regs;
37 
38 #define IO_RANGES 3
39 
40 struct initial_port_config {
41 	u32 portno;
42 	struct device_node *node;
43 	struct sparx5_port_config conf;
44 	struct phy *serdes;
45 };
46 
47 struct sparx5_ram_config {
48 	void __iomem *init_reg;
49 	u32 init_val;
50 };
51 
52 static const struct sparx5_main_io_resource sparx5_main_iomap[] =  {
53 	{ TARGET_CPU,                         0, 0 }, /* 0x600000000 */
54 	{ TARGET_FDMA,                  0x80000, 0 }, /* 0x600080000 */
55 	{ TARGET_PCEP,                 0x400000, 0 }, /* 0x600400000 */
56 	{ TARGET_DEV2G5,             0x10004000, 1 }, /* 0x610004000 */
57 	{ TARGET_DEV5G,              0x10008000, 1 }, /* 0x610008000 */
58 	{ TARGET_PCS5G_BR,           0x1000c000, 1 }, /* 0x61000c000 */
59 	{ TARGET_DEV2G5 +  1,        0x10010000, 1 }, /* 0x610010000 */
60 	{ TARGET_DEV5G +  1,         0x10014000, 1 }, /* 0x610014000 */
61 	{ TARGET_PCS5G_BR +  1,      0x10018000, 1 }, /* 0x610018000 */
62 	{ TARGET_DEV2G5 +  2,        0x1001c000, 1 }, /* 0x61001c000 */
63 	{ TARGET_DEV5G +  2,         0x10020000, 1 }, /* 0x610020000 */
64 	{ TARGET_PCS5G_BR +  2,      0x10024000, 1 }, /* 0x610024000 */
65 	{ TARGET_DEV2G5 +  6,        0x10028000, 1 }, /* 0x610028000 */
66 	{ TARGET_DEV5G +  6,         0x1002c000, 1 }, /* 0x61002c000 */
67 	{ TARGET_PCS5G_BR +  6,      0x10030000, 1 }, /* 0x610030000 */
68 	{ TARGET_DEV2G5 +  7,        0x10034000, 1 }, /* 0x610034000 */
69 	{ TARGET_DEV5G +  7,         0x10038000, 1 }, /* 0x610038000 */
70 	{ TARGET_PCS5G_BR +  7,      0x1003c000, 1 }, /* 0x61003c000 */
71 	{ TARGET_DEV2G5 +  8,        0x10040000, 1 }, /* 0x610040000 */
72 	{ TARGET_DEV5G +  8,         0x10044000, 1 }, /* 0x610044000 */
73 	{ TARGET_PCS5G_BR +  8,      0x10048000, 1 }, /* 0x610048000 */
74 	{ TARGET_DEV2G5 +  9,        0x1004c000, 1 }, /* 0x61004c000 */
75 	{ TARGET_DEV5G +  9,         0x10050000, 1 }, /* 0x610050000 */
76 	{ TARGET_PCS5G_BR +  9,      0x10054000, 1 }, /* 0x610054000 */
77 	{ TARGET_DEV2G5 + 10,        0x10058000, 1 }, /* 0x610058000 */
78 	{ TARGET_DEV5G + 10,         0x1005c000, 1 }, /* 0x61005c000 */
79 	{ TARGET_PCS5G_BR + 10,      0x10060000, 1 }, /* 0x610060000 */
80 	{ TARGET_DEV2G5 + 11,        0x10064000, 1 }, /* 0x610064000 */
81 	{ TARGET_DEV5G + 11,         0x10068000, 1 }, /* 0x610068000 */
82 	{ TARGET_PCS5G_BR + 11,      0x1006c000, 1 }, /* 0x61006c000 */
83 	{ TARGET_DEV2G5 + 12,        0x10070000, 1 }, /* 0x610070000 */
84 	{ TARGET_DEV10G,             0x10074000, 1 }, /* 0x610074000 */
85 	{ TARGET_PCS10G_BR,          0x10078000, 1 }, /* 0x610078000 */
86 	{ TARGET_DEV2G5 + 14,        0x1007c000, 1 }, /* 0x61007c000 */
87 	{ TARGET_DEV10G +  2,        0x10080000, 1 }, /* 0x610080000 */
88 	{ TARGET_PCS10G_BR +  2,     0x10084000, 1 }, /* 0x610084000 */
89 	{ TARGET_DEV2G5 + 15,        0x10088000, 1 }, /* 0x610088000 */
90 	{ TARGET_DEV10G +  3,        0x1008c000, 1 }, /* 0x61008c000 */
91 	{ TARGET_PCS10G_BR +  3,     0x10090000, 1 }, /* 0x610090000 */
92 	{ TARGET_DEV2G5 + 16,        0x10094000, 1 }, /* 0x610094000 */
93 	{ TARGET_DEV2G5 + 17,        0x10098000, 1 }, /* 0x610098000 */
94 	{ TARGET_DEV2G5 + 18,        0x1009c000, 1 }, /* 0x61009c000 */
95 	{ TARGET_DEV2G5 + 19,        0x100a0000, 1 }, /* 0x6100a0000 */
96 	{ TARGET_DEV2G5 + 20,        0x100a4000, 1 }, /* 0x6100a4000 */
97 	{ TARGET_DEV2G5 + 21,        0x100a8000, 1 }, /* 0x6100a8000 */
98 	{ TARGET_DEV2G5 + 22,        0x100ac000, 1 }, /* 0x6100ac000 */
99 	{ TARGET_DEV2G5 + 23,        0x100b0000, 1 }, /* 0x6100b0000 */
100 	{ TARGET_DEV2G5 + 32,        0x100b4000, 1 }, /* 0x6100b4000 */
101 	{ TARGET_DEV2G5 + 33,        0x100b8000, 1 }, /* 0x6100b8000 */
102 	{ TARGET_DEV2G5 + 34,        0x100bc000, 1 }, /* 0x6100bc000 */
103 	{ TARGET_DEV2G5 + 35,        0x100c0000, 1 }, /* 0x6100c0000 */
104 	{ TARGET_DEV2G5 + 36,        0x100c4000, 1 }, /* 0x6100c4000 */
105 	{ TARGET_DEV2G5 + 37,        0x100c8000, 1 }, /* 0x6100c8000 */
106 	{ TARGET_DEV2G5 + 38,        0x100cc000, 1 }, /* 0x6100cc000 */
107 	{ TARGET_DEV2G5 + 39,        0x100d0000, 1 }, /* 0x6100d0000 */
108 	{ TARGET_DEV2G5 + 40,        0x100d4000, 1 }, /* 0x6100d4000 */
109 	{ TARGET_DEV2G5 + 41,        0x100d8000, 1 }, /* 0x6100d8000 */
110 	{ TARGET_DEV2G5 + 42,        0x100dc000, 1 }, /* 0x6100dc000 */
111 	{ TARGET_DEV2G5 + 43,        0x100e0000, 1 }, /* 0x6100e0000 */
112 	{ TARGET_DEV2G5 + 44,        0x100e4000, 1 }, /* 0x6100e4000 */
113 	{ TARGET_DEV2G5 + 45,        0x100e8000, 1 }, /* 0x6100e8000 */
114 	{ TARGET_DEV2G5 + 46,        0x100ec000, 1 }, /* 0x6100ec000 */
115 	{ TARGET_DEV2G5 + 47,        0x100f0000, 1 }, /* 0x6100f0000 */
116 	{ TARGET_DEV2G5 + 57,        0x100f4000, 1 }, /* 0x6100f4000 */
117 	{ TARGET_DEV25G +  1,        0x100f8000, 1 }, /* 0x6100f8000 */
118 	{ TARGET_PCS25G_BR +  1,     0x100fc000, 1 }, /* 0x6100fc000 */
119 	{ TARGET_DEV2G5 + 59,        0x10104000, 1 }, /* 0x610104000 */
120 	{ TARGET_DEV25G +  3,        0x10108000, 1 }, /* 0x610108000 */
121 	{ TARGET_PCS25G_BR +  3,     0x1010c000, 1 }, /* 0x61010c000 */
122 	{ TARGET_DEV2G5 + 60,        0x10114000, 1 }, /* 0x610114000 */
123 	{ TARGET_DEV25G +  4,        0x10118000, 1 }, /* 0x610118000 */
124 	{ TARGET_PCS25G_BR +  4,     0x1011c000, 1 }, /* 0x61011c000 */
125 	{ TARGET_DEV2G5 + 64,        0x10124000, 1 }, /* 0x610124000 */
126 	{ TARGET_DEV5G + 12,         0x10128000, 1 }, /* 0x610128000 */
127 	{ TARGET_PCS5G_BR + 12,      0x1012c000, 1 }, /* 0x61012c000 */
128 	{ TARGET_PORT_CONF,          0x10130000, 1 }, /* 0x610130000 */
129 	{ TARGET_DEV2G5 +  3,        0x10404000, 1 }, /* 0x610404000 */
130 	{ TARGET_DEV5G +  3,         0x10408000, 1 }, /* 0x610408000 */
131 	{ TARGET_PCS5G_BR +  3,      0x1040c000, 1 }, /* 0x61040c000 */
132 	{ TARGET_DEV2G5 +  4,        0x10410000, 1 }, /* 0x610410000 */
133 	{ TARGET_DEV5G +  4,         0x10414000, 1 }, /* 0x610414000 */
134 	{ TARGET_PCS5G_BR +  4,      0x10418000, 1 }, /* 0x610418000 */
135 	{ TARGET_DEV2G5 +  5,        0x1041c000, 1 }, /* 0x61041c000 */
136 	{ TARGET_DEV5G +  5,         0x10420000, 1 }, /* 0x610420000 */
137 	{ TARGET_PCS5G_BR +  5,      0x10424000, 1 }, /* 0x610424000 */
138 	{ TARGET_DEV2G5 + 13,        0x10428000, 1 }, /* 0x610428000 */
139 	{ TARGET_DEV10G +  1,        0x1042c000, 1 }, /* 0x61042c000 */
140 	{ TARGET_PCS10G_BR +  1,     0x10430000, 1 }, /* 0x610430000 */
141 	{ TARGET_DEV2G5 + 24,        0x10434000, 1 }, /* 0x610434000 */
142 	{ TARGET_DEV2G5 + 25,        0x10438000, 1 }, /* 0x610438000 */
143 	{ TARGET_DEV2G5 + 26,        0x1043c000, 1 }, /* 0x61043c000 */
144 	{ TARGET_DEV2G5 + 27,        0x10440000, 1 }, /* 0x610440000 */
145 	{ TARGET_DEV2G5 + 28,        0x10444000, 1 }, /* 0x610444000 */
146 	{ TARGET_DEV2G5 + 29,        0x10448000, 1 }, /* 0x610448000 */
147 	{ TARGET_DEV2G5 + 30,        0x1044c000, 1 }, /* 0x61044c000 */
148 	{ TARGET_DEV2G5 + 31,        0x10450000, 1 }, /* 0x610450000 */
149 	{ TARGET_DEV2G5 + 48,        0x10454000, 1 }, /* 0x610454000 */
150 	{ TARGET_DEV10G +  4,        0x10458000, 1 }, /* 0x610458000 */
151 	{ TARGET_PCS10G_BR +  4,     0x1045c000, 1 }, /* 0x61045c000 */
152 	{ TARGET_DEV2G5 + 49,        0x10460000, 1 }, /* 0x610460000 */
153 	{ TARGET_DEV10G +  5,        0x10464000, 1 }, /* 0x610464000 */
154 	{ TARGET_PCS10G_BR +  5,     0x10468000, 1 }, /* 0x610468000 */
155 	{ TARGET_DEV2G5 + 50,        0x1046c000, 1 }, /* 0x61046c000 */
156 	{ TARGET_DEV10G +  6,        0x10470000, 1 }, /* 0x610470000 */
157 	{ TARGET_PCS10G_BR +  6,     0x10474000, 1 }, /* 0x610474000 */
158 	{ TARGET_DEV2G5 + 51,        0x10478000, 1 }, /* 0x610478000 */
159 	{ TARGET_DEV10G +  7,        0x1047c000, 1 }, /* 0x61047c000 */
160 	{ TARGET_PCS10G_BR +  7,     0x10480000, 1 }, /* 0x610480000 */
161 	{ TARGET_DEV2G5 + 52,        0x10484000, 1 }, /* 0x610484000 */
162 	{ TARGET_DEV10G +  8,        0x10488000, 1 }, /* 0x610488000 */
163 	{ TARGET_PCS10G_BR +  8,     0x1048c000, 1 }, /* 0x61048c000 */
164 	{ TARGET_DEV2G5 + 53,        0x10490000, 1 }, /* 0x610490000 */
165 	{ TARGET_DEV10G +  9,        0x10494000, 1 }, /* 0x610494000 */
166 	{ TARGET_PCS10G_BR +  9,     0x10498000, 1 }, /* 0x610498000 */
167 	{ TARGET_DEV2G5 + 54,        0x1049c000, 1 }, /* 0x61049c000 */
168 	{ TARGET_DEV10G + 10,        0x104a0000, 1 }, /* 0x6104a0000 */
169 	{ TARGET_PCS10G_BR + 10,     0x104a4000, 1 }, /* 0x6104a4000 */
170 	{ TARGET_DEV2G5 + 55,        0x104a8000, 1 }, /* 0x6104a8000 */
171 	{ TARGET_DEV10G + 11,        0x104ac000, 1 }, /* 0x6104ac000 */
172 	{ TARGET_PCS10G_BR + 11,     0x104b0000, 1 }, /* 0x6104b0000 */
173 	{ TARGET_DEV2G5 + 56,        0x104b4000, 1 }, /* 0x6104b4000 */
174 	{ TARGET_DEV25G,             0x104b8000, 1 }, /* 0x6104b8000 */
175 	{ TARGET_PCS25G_BR,          0x104bc000, 1 }, /* 0x6104bc000 */
176 	{ TARGET_DEV2G5 + 58,        0x104c4000, 1 }, /* 0x6104c4000 */
177 	{ TARGET_DEV25G +  2,        0x104c8000, 1 }, /* 0x6104c8000 */
178 	{ TARGET_PCS25G_BR +  2,     0x104cc000, 1 }, /* 0x6104cc000 */
179 	{ TARGET_DEV2G5 + 61,        0x104d4000, 1 }, /* 0x6104d4000 */
180 	{ TARGET_DEV25G +  5,        0x104d8000, 1 }, /* 0x6104d8000 */
181 	{ TARGET_PCS25G_BR +  5,     0x104dc000, 1 }, /* 0x6104dc000 */
182 	{ TARGET_DEV2G5 + 62,        0x104e4000, 1 }, /* 0x6104e4000 */
183 	{ TARGET_DEV25G +  6,        0x104e8000, 1 }, /* 0x6104e8000 */
184 	{ TARGET_PCS25G_BR +  6,     0x104ec000, 1 }, /* 0x6104ec000 */
185 	{ TARGET_DEV2G5 + 63,        0x104f4000, 1 }, /* 0x6104f4000 */
186 	{ TARGET_DEV25G +  7,        0x104f8000, 1 }, /* 0x6104f8000 */
187 	{ TARGET_PCS25G_BR +  7,     0x104fc000, 1 }, /* 0x6104fc000 */
188 	{ TARGET_DSM,                0x10504000, 1 }, /* 0x610504000 */
189 	{ TARGET_ASM,                0x10600000, 1 }, /* 0x610600000 */
190 	{ TARGET_GCB,                0x11010000, 2 }, /* 0x611010000 */
191 	{ TARGET_QS,                 0x11030000, 2 }, /* 0x611030000 */
192 	{ TARGET_PTP,                0x11040000, 2 }, /* 0x611040000 */
193 	{ TARGET_ANA_ACL,            0x11050000, 2 }, /* 0x611050000 */
194 	{ TARGET_LRN,                0x11060000, 2 }, /* 0x611060000 */
195 	{ TARGET_VCAP_SUPER,         0x11080000, 2 }, /* 0x611080000 */
196 	{ TARGET_QSYS,               0x110a0000, 2 }, /* 0x6110a0000 */
197 	{ TARGET_QFWD,               0x110b0000, 2 }, /* 0x6110b0000 */
198 	{ TARGET_XQS,                0x110c0000, 2 }, /* 0x6110c0000 */
199 	{ TARGET_VCAP_ES2,           0x110d0000, 2 }, /* 0x6110d0000 */
200 	{ TARGET_VCAP_ES0,           0x110e0000, 2 }, /* 0x6110e0000 */
201 	{ TARGET_CLKGEN,             0x11100000, 2 }, /* 0x611100000 */
202 	{ TARGET_ANA_AC_POL,         0x11200000, 2 }, /* 0x611200000 */
203 	{ TARGET_QRES,               0x11280000, 2 }, /* 0x611280000 */
204 	{ TARGET_EACL,               0x112c0000, 2 }, /* 0x6112c0000 */
205 	{ TARGET_ANA_CL,             0x11400000, 2 }, /* 0x611400000 */
206 	{ TARGET_ANA_L3,             0x11480000, 2 }, /* 0x611480000 */
207 	{ TARGET_ANA_AC_SDLB,        0x11500000, 2 }, /* 0x611500000 */
208 	{ TARGET_HSCH,               0x11580000, 2 }, /* 0x611580000 */
209 	{ TARGET_REW,                0x11600000, 2 }, /* 0x611600000 */
210 	{ TARGET_ANA_L2,             0x11800000, 2 }, /* 0x611800000 */
211 	{ TARGET_ANA_AC,             0x11900000, 2 }, /* 0x611900000 */
212 	{ TARGET_VOP,                0x11a00000, 2 }, /* 0x611a00000 */
213 };
214 
is_sparx5(struct sparx5 * sparx5)215 bool is_sparx5(struct sparx5 *sparx5)
216 {
217 	switch (sparx5->target_ct) {
218 	case SPX5_TARGET_CT_7546:
219 	case SPX5_TARGET_CT_7549:
220 	case SPX5_TARGET_CT_7552:
221 	case SPX5_TARGET_CT_7556:
222 	case SPX5_TARGET_CT_7558:
223 	case SPX5_TARGET_CT_7546TSN:
224 	case SPX5_TARGET_CT_7549TSN:
225 	case SPX5_TARGET_CT_7552TSN:
226 	case SPX5_TARGET_CT_7556TSN:
227 	case SPX5_TARGET_CT_7558TSN:
228 		return true;
229 	default:
230 		return false;
231 	}
232 }
233 
sparx5_init_features(struct sparx5 * sparx5)234 static void sparx5_init_features(struct sparx5 *sparx5)
235 {
236 	switch (sparx5->target_ct) {
237 	case SPX5_TARGET_CT_7546:
238 	case SPX5_TARGET_CT_7549:
239 	case SPX5_TARGET_CT_7552:
240 	case SPX5_TARGET_CT_7556:
241 	case SPX5_TARGET_CT_7558:
242 	case SPX5_TARGET_CT_7546TSN:
243 	case SPX5_TARGET_CT_7549TSN:
244 	case SPX5_TARGET_CT_7552TSN:
245 	case SPX5_TARGET_CT_7556TSN:
246 	case SPX5_TARGET_CT_7558TSN:
247 	case SPX5_TARGET_CT_LAN9691VAO:
248 	case SPX5_TARGET_CT_LAN9694TSN:
249 	case SPX5_TARGET_CT_LAN9694RED:
250 	case SPX5_TARGET_CT_LAN9692VAO:
251 	case SPX5_TARGET_CT_LAN9696TSN:
252 	case SPX5_TARGET_CT_LAN9696RED:
253 	case SPX5_TARGET_CT_LAN9693VAO:
254 	case SPX5_TARGET_CT_LAN9698TSN:
255 	case SPX5_TARGET_CT_LAN9698RED:
256 		sparx5->features = (SPX5_FEATURE_PSFP | SPX5_FEATURE_PTP);
257 		break;
258 	default:
259 		break;
260 	}
261 }
262 
sparx5_has_feature(struct sparx5 * sparx5,enum sparx5_feature feature)263 bool sparx5_has_feature(struct sparx5 *sparx5, enum sparx5_feature feature)
264 {
265 	return sparx5->features & feature;
266 }
267 
sparx5_create_targets(struct sparx5 * sparx5)268 static int sparx5_create_targets(struct sparx5 *sparx5)
269 {
270 	const struct sparx5_main_io_resource *iomap = sparx5->data->iomap;
271 	int iomap_size = sparx5->data->iomap_size;
272 	int ioranges = sparx5->data->ioranges;
273 	struct resource *iores[IO_RANGES];
274 	void __iomem *iomem[IO_RANGES];
275 	void __iomem *begin[IO_RANGES];
276 	int range_id[IO_RANGES];
277 	int idx, jdx;
278 
279 	for (idx = 0, jdx = 0; jdx < iomap_size; jdx++) {
280 		const struct sparx5_main_io_resource *io = &iomap[jdx];
281 
282 		if (idx == io->range) {
283 			range_id[idx] = jdx;
284 			idx++;
285 		}
286 	}
287 	for (idx = 0; idx < ioranges; idx++) {
288 		iores[idx] = platform_get_resource(sparx5->pdev, IORESOURCE_MEM,
289 						   idx);
290 		if (!iores[idx]) {
291 			dev_err(sparx5->dev, "Invalid resource\n");
292 			return -EINVAL;
293 		}
294 		iomem[idx] = devm_ioremap(sparx5->dev,
295 					  iores[idx]->start,
296 					  resource_size(iores[idx]));
297 		if (!iomem[idx]) {
298 			dev_err(sparx5->dev, "Unable to get switch registers: %s\n",
299 				iores[idx]->name);
300 			return -ENOMEM;
301 		}
302 		begin[idx] = iomem[idx] - iomap[range_id[idx]].offset;
303 	}
304 	for (jdx = 0; jdx < iomap_size; jdx++) {
305 		const struct sparx5_main_io_resource *io = &iomap[jdx];
306 
307 		sparx5->regs[io->id] = begin[io->range] + io->offset;
308 	}
309 	return 0;
310 }
311 
sparx5_create_port(struct sparx5 * sparx5,struct initial_port_config * config)312 static int sparx5_create_port(struct sparx5 *sparx5,
313 			      struct initial_port_config *config)
314 {
315 	struct sparx5_port *spx5_port;
316 	const struct sparx5_ops *ops;
317 	struct net_device *ndev;
318 	struct phylink *phylink;
319 	int err;
320 
321 	ops = sparx5->data->ops;
322 
323 	ndev = sparx5_create_netdev(sparx5, config->portno);
324 	if (IS_ERR(ndev)) {
325 		dev_err(sparx5->dev, "Could not create net device: %02u\n",
326 			config->portno);
327 		return PTR_ERR(ndev);
328 	}
329 	spx5_port = netdev_priv(ndev);
330 	spx5_port->of_node = config->node;
331 	spx5_port->serdes = config->serdes;
332 	spx5_port->pvid = NULL_VID;
333 	spx5_port->signd_internal = true;
334 	spx5_port->signd_active_high = true;
335 	spx5_port->signd_enable = true;
336 	spx5_port->max_vlan_tags = SPX5_PORT_MAX_TAGS_NONE;
337 	spx5_port->vlan_type = SPX5_VLAN_PORT_TYPE_UNAWARE;
338 	spx5_port->custom_etype = 0x8880; /* Vitesse */
339 	spx5_port->phylink_pcs.poll = true;
340 	spx5_port->phylink_pcs.ops = &sparx5_phylink_pcs_ops;
341 	spx5_port->phylink_pcs.neg_mode = true;
342 	spx5_port->is_mrouter = false;
343 	INIT_LIST_HEAD(&spx5_port->tc_templates);
344 	sparx5->ports[config->portno] = spx5_port;
345 
346 	err = sparx5_port_init(sparx5, spx5_port, &config->conf);
347 	if (err) {
348 		dev_err(sparx5->dev, "port init failed\n");
349 		return err;
350 	}
351 	spx5_port->conf = config->conf;
352 
353 	/* Setup VLAN */
354 	sparx5_vlan_port_setup(sparx5, spx5_port->portno);
355 
356 	/* Create a phylink for PHY management.  Also handles SFPs */
357 	spx5_port->phylink_config.dev = &spx5_port->ndev->dev;
358 	spx5_port->phylink_config.type = PHYLINK_NETDEV;
359 	spx5_port->phylink_config.mac_capabilities = MAC_ASYM_PAUSE |
360 		MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD |
361 		MAC_2500FD | MAC_5000FD | MAC_10000FD | MAC_25000FD;
362 
363 	if (ops->is_port_rgmii(spx5_port->portno))
364 		phy_interface_set_rgmii(spx5_port->phylink_config.supported_interfaces);
365 
366 	__set_bit(PHY_INTERFACE_MODE_SGMII,
367 		  spx5_port->phylink_config.supported_interfaces);
368 	__set_bit(PHY_INTERFACE_MODE_QSGMII,
369 		  spx5_port->phylink_config.supported_interfaces);
370 	__set_bit(PHY_INTERFACE_MODE_1000BASEX,
371 		  spx5_port->phylink_config.supported_interfaces);
372 	__set_bit(PHY_INTERFACE_MODE_2500BASEX,
373 		  spx5_port->phylink_config.supported_interfaces);
374 
375 	if (spx5_port->conf.bandwidth == SPEED_5000 ||
376 	    spx5_port->conf.bandwidth == SPEED_10000 ||
377 	    spx5_port->conf.bandwidth == SPEED_25000)
378 		__set_bit(PHY_INTERFACE_MODE_5GBASER,
379 			  spx5_port->phylink_config.supported_interfaces);
380 
381 	if (spx5_port->conf.bandwidth == SPEED_10000 ||
382 	    spx5_port->conf.bandwidth == SPEED_25000)
383 		__set_bit(PHY_INTERFACE_MODE_10GBASER,
384 			  spx5_port->phylink_config.supported_interfaces);
385 
386 	if (spx5_port->conf.bandwidth == SPEED_25000)
387 		__set_bit(PHY_INTERFACE_MODE_25GBASER,
388 			  spx5_port->phylink_config.supported_interfaces);
389 
390 	phylink = phylink_create(&spx5_port->phylink_config,
391 				 of_fwnode_handle(config->node),
392 				 config->conf.phy_mode,
393 				 &sparx5_phylink_mac_ops);
394 	if (IS_ERR(phylink))
395 		return PTR_ERR(phylink);
396 
397 	spx5_port->phylink = phylink;
398 
399 	return 0;
400 }
401 
sparx5_init_ram(struct sparx5 * s5)402 static int sparx5_init_ram(struct sparx5 *s5)
403 {
404 	const struct sparx5_ram_config spx5_ram_cfg[] = {
405 		{spx5_reg_get(s5, ANA_AC_STAT_RESET), ANA_AC_STAT_RESET_RESET},
406 		{spx5_reg_get(s5, ASM_STAT_CFG), ASM_STAT_CFG_STAT_CNT_CLR_SHOT},
407 		{spx5_reg_get(s5, QSYS_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
408 		{spx5_reg_get(s5, REW_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
409 		{spx5_reg_get(s5, VOP_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
410 		{spx5_reg_get(s5, ANA_AC_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
411 		{spx5_reg_get(s5, ASM_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
412 		{spx5_reg_get(s5, EACL_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
413 		{spx5_reg_get(s5, VCAP_SUPER_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
414 		{spx5_reg_get(s5, DSM_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}
415 	};
416 	const struct sparx5_ram_config *cfg;
417 	u32 value, pending, jdx, idx;
418 
419 	for (jdx = 0; jdx < 10; jdx++) {
420 		pending = ARRAY_SIZE(spx5_ram_cfg);
421 		for (idx = 0; idx < ARRAY_SIZE(spx5_ram_cfg); idx++) {
422 			cfg = &spx5_ram_cfg[idx];
423 			if (jdx == 0) {
424 				writel(cfg->init_val, cfg->init_reg);
425 			} else {
426 				value = readl(cfg->init_reg);
427 				if ((value & cfg->init_val) != cfg->init_val)
428 					pending--;
429 			}
430 		}
431 		if (!pending)
432 			break;
433 		usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC);
434 	}
435 
436 	if (pending > 0) {
437 		/* Still initializing, should be complete in
438 		 * less than 1ms
439 		 */
440 		dev_err(s5->dev, "Memory initialization error\n");
441 		return -EINVAL;
442 	}
443 	return 0;
444 }
445 
sparx5_init_switchcore(struct sparx5 * sparx5)446 static int sparx5_init_switchcore(struct sparx5 *sparx5)
447 {
448 	u32 value;
449 	int err = 0;
450 
451 	spx5_rmw(EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(1),
452 		 EACL_POL_EACL_CFG_EACL_FORCE_INIT,
453 		 sparx5,
454 		 EACL_POL_EACL_CFG);
455 
456 	spx5_rmw(EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(0),
457 		 EACL_POL_EACL_CFG_EACL_FORCE_INIT,
458 		 sparx5,
459 		 EACL_POL_EACL_CFG);
460 
461 	/* Initialize memories, if not done already */
462 	value = spx5_rd(sparx5, HSCH_RESET_CFG);
463 	if (!(value & HSCH_RESET_CFG_CORE_ENA)) {
464 		err = sparx5_init_ram(sparx5);
465 		if (err)
466 			return err;
467 	}
468 
469 	/* Reset counters */
470 	spx5_wr(ANA_AC_STAT_RESET_RESET_SET(1), sparx5, ANA_AC_STAT_RESET);
471 	spx5_wr(ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(1), sparx5, ASM_STAT_CFG);
472 
473 	/* Enable switch-core and queue system */
474 	spx5_wr(HSCH_RESET_CFG_CORE_ENA_SET(1), sparx5, HSCH_RESET_CFG);
475 
476 	return 0;
477 }
478 
sparx5_init_coreclock(struct sparx5 * sparx5)479 static int sparx5_init_coreclock(struct sparx5 *sparx5)
480 {
481 	enum sparx5_core_clockfreq freq = sparx5->coreclock;
482 	u32 clk_div, clk_period, pol_upd_int, idx;
483 
484 	/* Verify if core clock frequency is supported on target.
485 	 * If 'VTSS_CORE_CLOCK_DEFAULT' then the highest supported
486 	 * freq. is used
487 	 */
488 	switch (sparx5->target_ct) {
489 	case SPX5_TARGET_CT_7546:
490 		if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT)
491 			freq = SPX5_CORE_CLOCK_250MHZ;
492 		else if (sparx5->coreclock != SPX5_CORE_CLOCK_250MHZ)
493 			freq = 0; /* Not supported */
494 		break;
495 	case SPX5_TARGET_CT_7549:
496 	case SPX5_TARGET_CT_7552:
497 	case SPX5_TARGET_CT_7556:
498 		if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT)
499 			freq = SPX5_CORE_CLOCK_500MHZ;
500 		else if (sparx5->coreclock != SPX5_CORE_CLOCK_500MHZ)
501 			freq = 0; /* Not supported */
502 		break;
503 	case SPX5_TARGET_CT_7558:
504 	case SPX5_TARGET_CT_7558TSN:
505 		if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT)
506 			freq = SPX5_CORE_CLOCK_625MHZ;
507 		else if (sparx5->coreclock != SPX5_CORE_CLOCK_625MHZ)
508 			freq = 0; /* Not supported */
509 		break;
510 	case SPX5_TARGET_CT_7546TSN:
511 		if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT)
512 			freq = SPX5_CORE_CLOCK_625MHZ;
513 		break;
514 	case SPX5_TARGET_CT_7549TSN:
515 	case SPX5_TARGET_CT_7552TSN:
516 	case SPX5_TARGET_CT_7556TSN:
517 		if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT)
518 			freq = SPX5_CORE_CLOCK_625MHZ;
519 		else if (sparx5->coreclock == SPX5_CORE_CLOCK_250MHZ)
520 			freq = 0; /* Not supported */
521 		break;
522 	case SPX5_TARGET_CT_LAN9694:
523 	case SPX5_TARGET_CT_LAN9691VAO:
524 	case SPX5_TARGET_CT_LAN9694TSN:
525 	case SPX5_TARGET_CT_LAN9694RED:
526 	case SPX5_TARGET_CT_LAN9696:
527 	case SPX5_TARGET_CT_LAN9692VAO:
528 	case SPX5_TARGET_CT_LAN9696TSN:
529 	case SPX5_TARGET_CT_LAN9696RED:
530 	case SPX5_TARGET_CT_LAN9698:
531 	case SPX5_TARGET_CT_LAN9693VAO:
532 	case SPX5_TARGET_CT_LAN9698TSN:
533 	case SPX5_TARGET_CT_LAN9698RED:
534 		freq = SPX5_CORE_CLOCK_328MHZ;
535 		break;
536 	default:
537 		dev_err(sparx5->dev, "Target (%#04x) not supported\n",
538 			sparx5->target_ct);
539 		return -ENODEV;
540 	}
541 
542 	if (is_sparx5(sparx5)) {
543 		switch (freq) {
544 		case SPX5_CORE_CLOCK_250MHZ:
545 			clk_div = 10;
546 			pol_upd_int = 312;
547 			break;
548 		case SPX5_CORE_CLOCK_500MHZ:
549 			clk_div = 5;
550 			pol_upd_int = 624;
551 			break;
552 		case SPX5_CORE_CLOCK_625MHZ:
553 			clk_div = 4;
554 			pol_upd_int = 780;
555 			break;
556 		default:
557 			dev_err(sparx5->dev,
558 				"%d coreclock not supported on (%#04x)\n",
559 				sparx5->coreclock, sparx5->target_ct);
560 			return -EINVAL;
561 		}
562 
563 		/* Configure the LCPLL */
564 		spx5_rmw(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(clk_div) |
565 			 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(0) |
566 			 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(0) |
567 			 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(0) |
568 			 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(0) |
569 			 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_SET(1),
570 			 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV |
571 			 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV |
572 			 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR |
573 			 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL |
574 			 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA |
575 			 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA,
576 			 sparx5, CLKGEN_LCPLL1_CORE_CLK_CFG);
577 	} else {
578 		pol_upd_int = 820; // SPX5_CORE_CLOCK_328MHZ
579 	}
580 
581 	/* Update state with chosen frequency */
582 	sparx5->coreclock = freq;
583 	clk_period = sparx5_clk_period(freq);
584 
585 	if (is_sparx5(sparx5))
586 		spx5_rmw(HSCH_SYS_CLK_PER_100PS_SET(clk_period / 100),
587 			 HSCH_SYS_CLK_PER_100PS,
588 			 sparx5,
589 			 HSCH_SYS_CLK_PER);
590 
591 	spx5_rmw(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100),
592 		 ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS,
593 		 sparx5,
594 		 ANA_AC_POL_BDLB_DLB_CTRL);
595 
596 	spx5_rmw(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100),
597 		 ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS,
598 		 sparx5,
599 		 ANA_AC_POL_SLB_DLB_CTRL);
600 
601 	spx5_rmw(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_SET(clk_period / 100),
602 		 LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS,
603 		 sparx5,
604 		 LRN_AUTOAGE_CFG_1);
605 
606 	for (idx = 0; idx < sparx5->data->consts->n_sio_clks; idx++)
607 		spx5_rmw(GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(clk_period / 100),
608 			 GCB_SIO_CLOCK_SYS_CLK_PERIOD,
609 			 sparx5,
610 			 GCB_SIO_CLOCK(idx));
611 
612 	spx5_rmw(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_SET
613 		 ((256 * 1000) / clk_period),
614 		 HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY,
615 		 sparx5,
616 		 HSCH_TAS_STATEMACHINE_CFG);
617 
618 	spx5_rmw(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(pol_upd_int),
619 		 ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT,
620 		 sparx5,
621 		 ANA_AC_POL_POL_UPD_INT_CFG);
622 
623 	return 0;
624 }
625 
qlim_wm(struct sparx5 * sparx5,int fraction)626 static u32 qlim_wm(struct sparx5 *sparx5, int fraction)
627 {
628 	return (sparx5->data->consts->buf_size / SPX5_BUFFER_CELL_SZ - 100) *
629 	       fraction / 100;
630 }
631 
sparx5_qlim_set(struct sparx5 * sparx5)632 static int sparx5_qlim_set(struct sparx5 *sparx5)
633 {
634 	const struct sparx5_consts *consts = sparx5->data->consts;
635 	u32 res, dp, prio;
636 
637 	for (res = 0; res < 2; res++) {
638 		for (prio = 0; prio < 8; prio++)
639 			spx5_wr(0xFFF, sparx5,
640 				QRES_RES_CFG(prio +
641 					     consts->qres_max_prio_idx +
642 					     res * 1024));
643 
644 		for (dp = 0; dp < 4; dp++)
645 			spx5_wr(0xFFF, sparx5,
646 				QRES_RES_CFG(dp +
647 					     consts->qres_max_colour_idx +
648 					     res * 1024));
649 	}
650 
651 	/* Set 80,90,95,100% of memory size for top watermarks */
652 	spx5_wr(qlim_wm(sparx5, 80), sparx5, XQS_QLIMIT_SHR_QLIM_CFG(0));
653 	spx5_wr(qlim_wm(sparx5, 90), sparx5, XQS_QLIMIT_SHR_CTOP_CFG(0));
654 	spx5_wr(qlim_wm(sparx5, 95), sparx5, XQS_QLIMIT_SHR_ATOP_CFG(0));
655 	spx5_wr(qlim_wm(sparx5, 100), sparx5, XQS_QLIMIT_SHR_TOP_CFG(0));
656 
657 	return 0;
658 }
659 
660 /* Some boards needs to map the SGPIO for signal detect explicitly to the
661  * port module
662  */
sparx5_board_init(struct sparx5 * sparx5)663 static void sparx5_board_init(struct sparx5 *sparx5)
664 {
665 	int idx;
666 
667 	if (!sparx5->sd_sgpio_remapping)
668 		return;
669 
670 	/* Enable SGPIO Signal Detect remapping */
671 	spx5_rmw(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL,
672 		 GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL,
673 		 sparx5,
674 		 GCB_HW_SGPIO_SD_CFG);
675 
676 	/* Refer to LOS SGPIO */
677 	for (idx = 0; idx < sparx5->data->consts->n_ports; idx++)
678 		if (sparx5->ports[idx])
679 			if (sparx5->ports[idx]->conf.sd_sgpio != ~0)
680 				spx5_wr(sparx5->ports[idx]->conf.sd_sgpio,
681 					sparx5,
682 					GCB_HW_SGPIO_TO_SD_MAP_CFG(idx));
683 }
684 
sparx5_start(struct sparx5 * sparx5)685 static int sparx5_start(struct sparx5 *sparx5)
686 {
687 	u8 broadcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
688 	const struct sparx5_consts *consts = sparx5->data->consts;
689 	const struct sparx5_ops *ops = sparx5->data->ops;
690 	char queue_name[32];
691 	u32 idx;
692 	int err;
693 
694 	/* Setup own UPSIDs */
695 	for (idx = 0; idx < consts->n_own_upsids; idx++) {
696 		spx5_wr(idx, sparx5, ANA_AC_OWN_UPSID(idx));
697 		spx5_wr(idx, sparx5, ANA_CL_OWN_UPSID(idx));
698 		spx5_wr(idx, sparx5, ANA_L2_OWN_UPSID(idx));
699 		spx5_wr(idx, sparx5, REW_OWN_UPSID(idx));
700 	}
701 
702 	/* Enable CPU ports */
703 	for (idx = consts->n_ports; idx < consts->n_ports_all; idx++)
704 		spx5_rmw(QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(1),
705 			 QFWD_SWITCH_PORT_MODE_PORT_ENA,
706 			 sparx5,
707 			 QFWD_SWITCH_PORT_MODE(idx));
708 
709 	/* Init masks */
710 	sparx5_update_fwd(sparx5);
711 
712 	/* CPU copy CPU pgids */
713 	spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1), sparx5,
714 		ANA_AC_PGID_MISC_CFG(sparx5_get_pgid(sparx5, PGID_CPU)));
715 	spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1), sparx5,
716 		ANA_AC_PGID_MISC_CFG(sparx5_get_pgid(sparx5, PGID_BCAST)));
717 
718 	/* Recalc injected frame FCS */
719 	for (idx = sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_0);
720 	     idx <= sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_1); idx++)
721 		spx5_rmw(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(1),
722 			 ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA,
723 			 sparx5, ANA_CL_FILTER_CTRL(idx));
724 
725 	/* Init MAC table, ageing */
726 	sparx5_mact_init(sparx5);
727 
728 	/* Init PGID table arbitrator */
729 	sparx5_pgid_init(sparx5);
730 
731 	/* Setup VLANs */
732 	sparx5_vlan_init(sparx5);
733 
734 	/* Add host mode BC address (points only to CPU) */
735 	sparx5_mact_learn(sparx5, sparx5_get_pgid(sparx5, PGID_CPU), broadcast,
736 			  NULL_VID);
737 
738 	/* Enable queue limitation watermarks */
739 	sparx5_qlim_set(sparx5);
740 
741 	err = sparx5_config_auto_calendar(sparx5);
742 	if (err)
743 		return err;
744 
745 	err = sparx5_config_dsm_calendar(sparx5);
746 	if (err)
747 		return err;
748 
749 	/* Init stats */
750 	err = sparx_stats_init(sparx5);
751 	if (err)
752 		return err;
753 
754 	/* Init mact_sw struct */
755 	mutex_init(&sparx5->mact_lock);
756 	INIT_LIST_HEAD(&sparx5->mact_entries);
757 	snprintf(queue_name, sizeof(queue_name), "%s-mact",
758 		 dev_name(sparx5->dev));
759 	sparx5->mact_queue = create_singlethread_workqueue(queue_name);
760 	if (!sparx5->mact_queue)
761 		return -ENOMEM;
762 
763 	INIT_DELAYED_WORK(&sparx5->mact_work, sparx5_mact_pull_work);
764 	queue_delayed_work(sparx5->mact_queue, &sparx5->mact_work,
765 			   SPX5_MACT_PULL_DELAY);
766 
767 	mutex_init(&sparx5->mdb_lock);
768 	INIT_LIST_HEAD(&sparx5->mdb_entries);
769 
770 	err = sparx5_register_netdevs(sparx5);
771 	if (err)
772 		return err;
773 
774 	sparx5_board_init(sparx5);
775 	err = sparx5_register_notifier_blocks(sparx5);
776 	if (err)
777 		return err;
778 
779 	err = sparx5_vcap_init(sparx5);
780 	if (err) {
781 		sparx5_unregister_notifier_blocks(sparx5);
782 		return err;
783 	}
784 
785 	/* Start Frame DMA with fallback to register based INJ/XTR */
786 	err = -ENXIO;
787 	if (sparx5->fdma_irq >= 0) {
788 		if (GCB_CHIP_ID_REV_ID_GET(sparx5->chip_id) > 0 ||
789 		    !is_sparx5(sparx5))
790 			err = devm_request_irq(sparx5->dev,
791 					       sparx5->fdma_irq,
792 					       sparx5_fdma_handler,
793 					       0,
794 					       "sparx5-fdma", sparx5);
795 		if (!err) {
796 			err = ops->fdma_init(sparx5);
797 			if (!err)
798 				sparx5_fdma_start(sparx5);
799 		}
800 		if (err)
801 			sparx5->fdma_irq = -ENXIO;
802 	} else {
803 		sparx5->fdma_irq = -ENXIO;
804 	}
805 	if (err && sparx5->xtr_irq >= 0) {
806 		err = devm_request_irq(sparx5->dev, sparx5->xtr_irq,
807 				       sparx5_xtr_handler, IRQF_SHARED,
808 				       "sparx5-xtr", sparx5);
809 		if (!err)
810 			err = sparx5_manual_injection_mode(sparx5);
811 		if (err)
812 			sparx5->xtr_irq = -ENXIO;
813 	} else {
814 		sparx5->xtr_irq = -ENXIO;
815 	}
816 
817 	if (sparx5->ptp_irq >= 0 &&
818 	    sparx5_has_feature(sparx5, SPX5_FEATURE_PTP)) {
819 		err = devm_request_threaded_irq(sparx5->dev, sparx5->ptp_irq,
820 						NULL, ops->ptp_irq_handler,
821 						IRQF_ONESHOT, "sparx5-ptp",
822 						sparx5);
823 		if (err)
824 			sparx5->ptp_irq = -ENXIO;
825 
826 		sparx5->ptp = 1;
827 	}
828 
829 	return err;
830 }
831 
sparx5_cleanup_ports(struct sparx5 * sparx5)832 static void sparx5_cleanup_ports(struct sparx5 *sparx5)
833 {
834 	sparx5_unregister_netdevs(sparx5);
835 	sparx5_destroy_netdevs(sparx5);
836 }
837 
mchp_sparx5_probe(struct platform_device * pdev)838 static int mchp_sparx5_probe(struct platform_device *pdev)
839 {
840 	struct initial_port_config *configs, *config;
841 	struct device_node *np = pdev->dev.of_node;
842 	struct device_node *ports, *portnp;
843 	const struct sparx5_ops *ops;
844 	struct reset_control *reset;
845 	struct sparx5 *sparx5;
846 	int idx = 0, err = 0;
847 
848 	if (!np && !pdev->dev.platform_data)
849 		return -ENODEV;
850 
851 	sparx5 = devm_kzalloc(&pdev->dev, sizeof(*sparx5), GFP_KERNEL);
852 	if (!sparx5)
853 		return -ENOMEM;
854 
855 	platform_set_drvdata(pdev, sparx5);
856 	sparx5->pdev = pdev;
857 	sparx5->dev = &pdev->dev;
858 	spin_lock_init(&sparx5->tx_lock);
859 
860 	sparx5->data = device_get_match_data(sparx5->dev);
861 	if (!sparx5->data)
862 		return -EINVAL;
863 
864 	regs = sparx5->data->regs;
865 	ops = sparx5->data->ops;
866 
867 	/* Do switch core reset if available */
868 	reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch");
869 	if (IS_ERR(reset))
870 		return dev_err_probe(&pdev->dev, PTR_ERR(reset),
871 				     "Failed to get switch reset controller.\n");
872 	reset_control_reset(reset);
873 
874 	/* Default values, some from DT */
875 	sparx5->coreclock = SPX5_CORE_CLOCK_DEFAULT;
876 
877 	sparx5->debugfs_root = debugfs_create_dir("sparx5", NULL);
878 
879 	ports = of_get_child_by_name(np, "ethernet-ports");
880 	if (!ports) {
881 		dev_err(sparx5->dev, "no ethernet-ports child node found\n");
882 		return -ENODEV;
883 	}
884 	sparx5->port_count = of_get_child_count(ports);
885 
886 	configs = kcalloc(sparx5->port_count,
887 			  sizeof(struct initial_port_config), GFP_KERNEL);
888 	if (!configs) {
889 		err = -ENOMEM;
890 		goto cleanup_pnode;
891 	}
892 
893 	for_each_available_child_of_node(ports, portnp) {
894 		struct sparx5_port_config *conf;
895 		struct phy *serdes = NULL;
896 		u32 portno;
897 
898 		err = of_property_read_u32(portnp, "reg", &portno);
899 		if (err) {
900 			dev_err(sparx5->dev, "port reg property error\n");
901 			continue;
902 		}
903 		config = &configs[idx];
904 		conf = &config->conf;
905 		conf->speed = SPEED_UNKNOWN;
906 		conf->bandwidth = SPEED_UNKNOWN;
907 		err = of_get_phy_mode(portnp, &conf->phy_mode);
908 		if (err) {
909 			dev_err(sparx5->dev, "port %u: missing phy-mode\n",
910 				portno);
911 			continue;
912 		}
913 		err = of_property_read_u32(portnp, "microchip,bandwidth",
914 					   &conf->bandwidth);
915 		if (err) {
916 			dev_err(sparx5->dev, "port %u: missing bandwidth\n",
917 				portno);
918 			continue;
919 		}
920 		err = of_property_read_u32(portnp, "microchip,sd-sgpio", &conf->sd_sgpio);
921 		if (err)
922 			conf->sd_sgpio = ~0;
923 		else
924 			sparx5->sd_sgpio_remapping = true;
925 		/* There is no SerDes node for RGMII ports. */
926 		if (!ops->is_port_rgmii(portno)) {
927 			serdes = devm_of_phy_get(sparx5->dev, portnp, NULL);
928 			if (IS_ERR(serdes)) {
929 				err = dev_err_probe(sparx5->dev,
930 						    PTR_ERR(serdes),
931 						    "port %u: missing serdes\n",
932 						    portno);
933 				of_node_put(portnp);
934 				goto cleanup_config;
935 			}
936 		}
937 		config->portno = portno;
938 		config->node = portnp;
939 		config->serdes = serdes;
940 
941 		conf->media = PHY_MEDIA_DAC;
942 		conf->serdes_reset = true;
943 		conf->portmode = conf->phy_mode;
944 		conf->power_down = true;
945 		idx++;
946 	}
947 
948 	err = sparx5_create_targets(sparx5);
949 	if (err)
950 		goto cleanup_config;
951 
952 	if (of_get_mac_address(np, sparx5->base_mac)) {
953 		dev_info(sparx5->dev, "MAC addr was not set, use random MAC\n");
954 		eth_random_addr(sparx5->base_mac);
955 		sparx5->base_mac[5] = 0;
956 	}
957 
958 	sparx5->fdma_irq = platform_get_irq_byname(sparx5->pdev, "fdma");
959 	sparx5->xtr_irq = platform_get_irq_byname(sparx5->pdev, "xtr");
960 	sparx5->ptp_irq = platform_get_irq_byname(sparx5->pdev, "ptp");
961 
962 	/* Read chip ID to check CPU interface */
963 	sparx5->chip_id = spx5_rd(sparx5, GCB_CHIP_ID);
964 
965 	sparx5->target_ct = (enum spx5_target_chiptype)
966 		GCB_CHIP_ID_PART_ID_GET(sparx5->chip_id);
967 
968 	/* Initialize the features based on the target */
969 	sparx5_init_features(sparx5);
970 
971 	/* Initialize Switchcore and internal RAMs */
972 	err = sparx5_init_switchcore(sparx5);
973 	if (err) {
974 		dev_err(sparx5->dev, "Switchcore initialization error\n");
975 		goto cleanup_config;
976 	}
977 
978 	/* Initialize the LC-PLL (core clock) and set affected registers */
979 	err = sparx5_init_coreclock(sparx5);
980 	if (err) {
981 		dev_err(sparx5->dev, "LC-PLL initialization error\n");
982 		goto cleanup_config;
983 	}
984 
985 	for (idx = 0; idx < sparx5->port_count; ++idx) {
986 		config = &configs[idx];
987 		if (!config->node)
988 			continue;
989 
990 		err = sparx5_create_port(sparx5, config);
991 		if (err) {
992 			dev_err(sparx5->dev, "port create error\n");
993 			goto cleanup_ports;
994 		}
995 	}
996 
997 	err = sparx5_start(sparx5);
998 	if (err) {
999 		dev_err(sparx5->dev, "Start failed\n");
1000 		goto cleanup_ports;
1001 	}
1002 
1003 	err = sparx5_qos_init(sparx5);
1004 	if (err) {
1005 		dev_err(sparx5->dev, "Failed to initialize QoS\n");
1006 		goto cleanup_ports;
1007 	}
1008 
1009 	err = sparx5_ptp_init(sparx5);
1010 	if (err) {
1011 		dev_err(sparx5->dev, "PTP failed\n");
1012 		goto cleanup_ports;
1013 	}
1014 
1015 	INIT_LIST_HEAD(&sparx5->mall_entries);
1016 
1017 	goto cleanup_config;
1018 
1019 cleanup_ports:
1020 	sparx5_cleanup_ports(sparx5);
1021 	if (sparx5->mact_queue)
1022 		destroy_workqueue(sparx5->mact_queue);
1023 cleanup_config:
1024 	kfree(configs);
1025 cleanup_pnode:
1026 	of_node_put(ports);
1027 	return err;
1028 }
1029 
mchp_sparx5_remove(struct platform_device * pdev)1030 static void mchp_sparx5_remove(struct platform_device *pdev)
1031 {
1032 	struct sparx5 *sparx5 = platform_get_drvdata(pdev);
1033 	const struct sparx5_ops *ops = sparx5->data->ops;
1034 
1035 	debugfs_remove_recursive(sparx5->debugfs_root);
1036 	if (sparx5->xtr_irq) {
1037 		disable_irq(sparx5->xtr_irq);
1038 		sparx5->xtr_irq = -ENXIO;
1039 	}
1040 	if (sparx5->fdma_irq) {
1041 		disable_irq(sparx5->fdma_irq);
1042 		sparx5->fdma_irq = -ENXIO;
1043 	}
1044 	sparx5_ptp_deinit(sparx5);
1045 	ops->fdma_deinit(sparx5);
1046 	sparx5_cleanup_ports(sparx5);
1047 	sparx5_vcap_destroy(sparx5);
1048 	/* Unregister netdevs */
1049 	sparx5_unregister_notifier_blocks(sparx5);
1050 	destroy_workqueue(sparx5->mact_queue);
1051 }
1052 
1053 static const struct sparx5_regs sparx5_regs = {
1054 	.tsize = sparx5_tsize,
1055 	.gaddr = sparx5_gaddr,
1056 	.gcnt = sparx5_gcnt,
1057 	.gsize = sparx5_gsize,
1058 	.raddr = sparx5_raddr,
1059 	.rcnt = sparx5_rcnt,
1060 	.fpos = sparx5_fpos,
1061 	.fsize = sparx5_fsize,
1062 };
1063 
1064 static const struct sparx5_consts sparx5_consts = {
1065 	.n_ports             = 65,
1066 	.n_ports_all         = 70,
1067 	.n_hsch_l1_elems     = 64,
1068 	.n_hsch_queues       = 8,
1069 	.n_lb_groups         = 10,
1070 	.n_pgids             = 2113, /* (2048 + n_ports) */
1071 	.n_sio_clks          = 3,
1072 	.n_own_upsids        = 3,
1073 	.n_auto_cals         = 7,
1074 	.n_filters           = 1024,
1075 	.n_gates             = 1024,
1076 	.n_sdlbs             = 4096,
1077 	.n_dsm_cal_taxis     = 8,
1078 	.buf_size            = 4194280,
1079 	.qres_max_prio_idx   = 630,
1080 	.qres_max_colour_idx = 638,
1081 	.tod_pin             = 4,
1082 	.vcaps               = sparx5_vcaps,
1083 	.vcaps_cfg           = sparx5_vcap_inst_cfg,
1084 	.vcap_stats          = &sparx5_vcap_stats,
1085 };
1086 
1087 static const struct sparx5_ops sparx5_ops = {
1088 	.is_port_2g5             = &sparx5_port_is_2g5,
1089 	.is_port_5g              = &sparx5_port_is_5g,
1090 	.is_port_10g             = &sparx5_port_is_10g,
1091 	.is_port_25g             = &sparx5_port_is_25g,
1092 	.is_port_rgmii           = &sparx5_port_is_rgmii,
1093 	.get_port_dev_index      = &sparx5_port_dev_mapping,
1094 	.get_port_dev_bit        = &sparx5_port_dev_mapping,
1095 	.get_hsch_max_group_rate = &sparx5_get_hsch_max_group_rate,
1096 	.get_sdlb_group          = &sparx5_get_sdlb_group,
1097 	.set_port_mux            = &sparx5_port_mux_set,
1098 	.ptp_irq_handler         = &sparx5_ptp_irq_handler,
1099 	.dsm_calendar_calc       = &sparx5_dsm_calendar_calc,
1100 	.fdma_init               = &sparx5_fdma_init,
1101 	.fdma_deinit             = &sparx5_fdma_deinit,
1102 	.fdma_poll               = &sparx5_fdma_napi_callback,
1103 	.fdma_xmit               = &sparx5_fdma_xmit,
1104 };
1105 
1106 static const struct sparx5_match_data sparx5_desc = {
1107 	.iomap = sparx5_main_iomap,
1108 	.iomap_size = ARRAY_SIZE(sparx5_main_iomap),
1109 	.ioranges = 3,
1110 	.regs = &sparx5_regs,
1111 	.consts = &sparx5_consts,
1112 	.ops = &sparx5_ops,
1113 };
1114 
1115 static const struct of_device_id mchp_sparx5_match[] = {
1116 	{ .compatible = "microchip,sparx5-switch", .data = &sparx5_desc },
1117 #ifdef CONFIG_LAN969X_SWITCH
1118 	{ .compatible = "microchip,lan9691-switch", .data = &lan969x_desc },
1119 #endif
1120 	{ }
1121 };
1122 MODULE_DEVICE_TABLE(of, mchp_sparx5_match);
1123 
1124 static struct platform_driver mchp_sparx5_driver = {
1125 	.probe = mchp_sparx5_probe,
1126 	.remove = mchp_sparx5_remove,
1127 	.driver = {
1128 		.name = "sparx5-switch",
1129 		.of_match_table = mchp_sparx5_match,
1130 	},
1131 };
1132 
1133 module_platform_driver(mchp_sparx5_driver);
1134 
1135 MODULE_DESCRIPTION("Microchip Sparx5 switch driver");
1136 MODULE_AUTHOR("Steen Hegelund <steen.hegelund@microchip.com>");
1137 MODULE_LICENSE("Dual MIT/GPL");
1138