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Searched refs:m_offset (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_hdmi_ddc_clk.c19 u8 m_offset; member
30 const u8 m_offset, in sun4i_ddc_calc_divider() argument
41 (_m + m_offset); in sun4i_ddc_calc_divider()
68 ddc->m_offset, NULL, NULL); in sun4i_ddc_round_rate()
83 (m + ddc->m_offset); in sun4i_ddc_recalc_rate()
93 ddc->m_offset, &div_m, &div_n); in sun4i_ddc_set_rate()
135 ddc->m_offset = hdmi->variant->ddc_clk_m_offset; in sun4i_ddc_create()
/linux/drivers/clk/ingenic/
H A Dx1830-cgu.c120 .m_offset = 1,
143 .m_offset = 1,
166 .m_offset = 1,
189 .m_offset = 1,
H A Djz4760-cgu.c100 .m_offset = 0,
125 .m_offset = 0,
H A Djz4770-cgu.c110 .m_offset = 1,
134 .m_offset = 1,
H A Dcgu.h56 u8 m_shift, m_bits, m_offset; member
H A Dx1000-cgu.c225 .m_offset = 1,
248 .m_offset = 1,
H A Djz4740-cgu.c77 .m_offset = 2,
H A Djz4725b-cgu.c62 .m_offset = 2,
H A Dcgu.c96 m += pll_info->m_offset; in ingenic_pll_recalc_rate()
146 m = max_t(unsigned int, m, pll_info->m_offset); in ingenic_pll_calc_m_n_od()
223 ctl |= (m - pll_info->m_offset) << pll_info->m_shift; in ingenic_pll_set_rate()
H A Djz4755-cgu.c59 .m_offset = 2,
H A Djz4780-cgu.c278 .m_offset = 1, \
/linux/drivers/pmdomain/rockchip/
H A Dpm-domains.c132 #define DOMAIN_M_O_R(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idl… argument
139 .mem_offset = m_offset, \
150 #define DOMAIN_M_O_R_G(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, i… argument
157 .mem_offset = m_offset, \
306 #define DOMAIN_RK3588(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idl… argument
307 …DOMAIN_M_O_R(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, idle,…
/linux/mm/
H A Dzsmalloc.c1307 unsigned long m_offset; in obj_malloc() local
1315 m_offset = offset_in_page(offset); in obj_malloc()
1322 link = (struct link_free *)vaddr + m_offset / sizeof(*link); in obj_malloc()