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Searched refs:lower_32_bits (Results 1 – 25 of 517) sorted by relevance

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/linux/drivers/firmware/smccc/
H A Dkvm_guest.c30 val[0] = lower_32_bits(res.a0); in kvm_init_hyp_services()
31 val[1] = lower_32_bits(res.a1); in kvm_init_hyp_services()
32 val[2] = lower_32_bits(res.a2); in kvm_init_hyp_services()
33 val[3] = lower_32_bits(res.a3); in kvm_init_hyp_services()
71 ver = lower_32_bits(res.a1); in kvm_arm_target_impl_cpu_init()
/linux/drivers/pci/controller/mobiveil/
H A Dpcie-mobiveil.c151 (lower_32_bits(size64) & WIN_SIZE_MASK); in program_ib_windows()
157 mobiveil_csr_writel(pcie, lower_32_bits(cpu_addr), in program_ib_windows()
162 mobiveil_csr_writel(pcie, lower_32_bits(pci_addr), in program_ib_windows()
192 (lower_32_bits(size64) & WIN_SIZE_MASK); in program_ob_windows()
203 lower_32_bits(cpu_addr) & (~AXI_WINDOW_ALIGN_MASK), in program_ob_windows()
208 mobiveil_csr_writel(pcie, lower_32_bits(pci_addr), in program_ob_windows()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v2_0.c400 lower_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v2_0_mc_resume()
412 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); in vcn_v2_0_mc_resume()
420 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_0_mc_resume()
428 lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr)); in vcn_v2_0_mc_resume()
468 lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
489 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
509 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
521 lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
975 lower_32_bits(ring->gpu_addr)); in vcn_v2_0_start_dpg_mode()
986 lower_32_bits(ring->wptr)); in vcn_v2_0_start_dpg_mode()
[all …]
H A Dsdma_v7_0.c149 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v7_0_ring_init_cond_exec()
217 lower_32_bits(ring->wptr << 2), in sdma_v7_0_ring_set_wptr()
230 lower_32_bits(ring->wptr << 2), in sdma_v7_0_ring_set_wptr()
236 lower_32_bits(ring->wptr << 2)); in sdma_v7_0_ring_set_wptr()
283 sdma_v7_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); in sdma_v7_0_ring_emit_ib()
288 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v7_0_ring_emit_ib()
291 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); in sdma_v7_0_ring_emit_ib()
367 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v7_0_ring_emit_fence()
369 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v7_0_ring_emit_fence()
378 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v7_0_ring_emit_fence()
[all …]
H A Dsdma_v6_0.c150 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v6_0_ring_init_cond_exec()
216 lower_32_bits(ring->wptr << 2), in sdma_v6_0_ring_set_wptr()
229 lower_32_bits(ring->wptr << 2), in sdma_v6_0_ring_set_wptr()
234 lower_32_bits(ring->wptr << 2)); in sdma_v6_0_ring_set_wptr()
280 sdma_v6_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); in sdma_v6_0_ring_emit_ib()
285 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v6_0_ring_emit_ib()
288 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); in sdma_v6_0_ring_emit_ib()
364 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v6_0_ring_emit_fence()
366 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v6_0_ring_emit_fence()
375 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v6_0_ring_emit_fence()
[all …]
H A Dsdma_v7_1.c143 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v7_1_ring_init_cond_exec()
211 lower_32_bits(ring->wptr << 2), in sdma_v7_1_ring_set_wptr()
224 lower_32_bits(ring->wptr << 2), in sdma_v7_1_ring_set_wptr()
230 lower_32_bits(ring->wptr << 2)); in sdma_v7_1_ring_set_wptr()
277 sdma_v7_1_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); in sdma_v7_1_ring_emit_ib()
282 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v7_1_ring_emit_ib()
285 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); in sdma_v7_1_ring_emit_ib()
335 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v7_1_ring_emit_fence()
337 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v7_1_ring_emit_fence()
346 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v7_1_ring_emit_fence()
[all …]
H A Dvcn_v3_0.c537 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v3_0_mc_resume()
548 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v3_0_mc_resume()
556 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v3_0_mc_resume()
564 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); in vcn_v3_0_mc_resume()
603 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
624 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
644 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
656 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
1161 lower_32_bits(ring->gpu_addr)); in vcn_v3_0_start_dpg_mode()
1172 lower_32_bits(ring->wptr)); in vcn_v3_0_start_dpg_mode()
[all …]
H A Dvcn_v2_5.c609 lower_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v2_5_mc_resume()
620 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset)); in vcn_v2_5_mc_resume()
628 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_5_mc_resume()
636 lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); in vcn_v2_5_mc_resume()
675 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
696 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
716 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
728 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
1130 lower_32_bits(ring->gpu_addr)); in vcn_v2_5_start_dpg_mode()
1141 lower_32_bits(ring->wptr)); in vcn_v2_5_start_dpg_mode()
[all …]
H A Damdgpu_cper.c306 reg_data.status_lo = lower_32_bits(bank->regs[ACA_REG_IDX_STATUS]); in amdgpu_cper_generate_ue_record()
308 reg_data.addr_lo = lower_32_bits(bank->regs[ACA_REG_IDX_ADDR]); in amdgpu_cper_generate_ue_record()
310 reg_data.ipid_lo = lower_32_bits(bank->regs[ACA_REG_IDX_IPID]); in amdgpu_cper_generate_ue_record()
312 reg_data.synd_lo = lower_32_bits(bank->regs[ACA_REG_IDX_SYND]); in amdgpu_cper_generate_ue_record()
400 reg_data[CPER_ACA_REG_CTL_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_CTL]); in amdgpu_cper_generate_ce_records()
402 reg_data[CPER_ACA_REG_STATUS_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_STATUS]); in amdgpu_cper_generate_ce_records()
404 reg_data[CPER_ACA_REG_ADDR_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_ADDR]); in amdgpu_cper_generate_ce_records()
406 reg_data[CPER_ACA_REG_MISC0_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_MISC0]); in amdgpu_cper_generate_ce_records()
408 reg_data[CPER_ACA_REG_CONFIG_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_CONFIG]); in amdgpu_cper_generate_ce_records()
410 reg_data[CPER_ACA_REG_IPID_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_IPID]); in amdgpu_cper_generate_ce_records()
[all …]
H A Dumsch_mm_v4_0.c90 lower_32_bits(adev->umsch_mm.irq_start_addr >> 2)); in umsch_mm_v4_0_load_microcode()
95 lower_32_bits(adev->umsch_mm.uc_start_addr >> 2)); in umsch_mm_v4_0_load_microcode()
103 WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_INSTR_MASK_LO, lower_32_bits(data)); in umsch_mm_v4_0_load_microcode()
108 WREG32_SOC15_UMSCH(regVCN_MES_IC_BASE_LO, lower_32_bits(data)); in umsch_mm_v4_0_load_microcode()
114 lower_32_bits(adev->umsch_mm.data_start_addr)); in umsch_mm_v4_0_load_microcode()
124 WREG32_SOC15_UMSCH(regVCN_MES_DC_BASE_LO, lower_32_bits(data)); in umsch_mm_v4_0_load_microcode()
147 WREG32_SOC15_UMSCH(regVCN_MES_GP0_LO, lower_32_bits(umsch->log_gpu_addr)); in umsch_mm_v4_0_load_microcode()
228 WREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_BASE_LO, lower_32_bits(ring->gpu_addr)); in umsch_mm_v4_0_ring_start()
H A Dlsdma_v7_0.c47 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_SRC_ADDR_LO, lower_32_bits(src_addr)); in lsdma_v7_0_copy_mem()
50 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_LO, lower_32_bits(dst_addr)); in lsdma_v7_0_copy_mem()
82 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_LO, lower_32_bits(dst_addr)); in lsdma_v7_0_fill_mem()
H A Dlsdma_v6_0.c47 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_SRC_ADDR_LO, lower_32_bits(src_addr)); in lsdma_v6_0_copy_mem()
50 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_LO, lower_32_bits(dst_addr)); in lsdma_v6_0_copy_mem()
82 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_LO, lower_32_bits(dst_addr)); in lsdma_v6_0_fill_mem()
/linux/drivers/tee/tstee/
H A Dcore.c37 args[0] = lower_32_bits(data->data0); in arg_list_from_ffa_data()
38 args[1] = lower_32_bits(data->data1); in arg_list_from_ffa_data()
39 args[2] = lower_32_bits(data->data2); in arg_list_from_ffa_data()
40 args[3] = lower_32_bits(data->data3); in arg_list_from_ffa_data()
41 args[4] = lower_32_bits(data->data4); in arg_list_from_ffa_data()
190 shm_id = lower_32_bits(param[0].u.value.a); in tstee_invoke_func()
191 req_len = lower_32_bits(param[0].u.value.b); in tstee_invoke_func()
212 ffa_args[TS_RPC_SERVICE_MEM_HANDLE_LSW] = lower_32_bits(handle); in tstee_invoke_func()
281 lower_32_bits(shm->sec_world_id); in tstee_shm_register()
319 lower_32_bits(shm->sec_world_id); in tstee_shm_unregister()
/linux/drivers/iio/test/
H A Diio-test-format.c211 values[0] = lower_32_bits(value); in iio_test_iio_format_value_integer_64()
217 values[0] = lower_32_bits(value); in iio_test_iio_format_value_integer_64()
223 values[0] = lower_32_bits(value); in iio_test_iio_format_value_integer_64()
229 values[0] = lower_32_bits(value); in iio_test_iio_format_value_integer_64()
235 values[0] = lower_32_bits(value); in iio_test_iio_format_value_integer_64()
241 values[0] = lower_32_bits(value); in iio_test_iio_format_value_integer_64()
247 values[0] = lower_32_bits(value); in iio_test_iio_format_value_integer_64()
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/
H A Dgm20b.c73 hdr.code_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_pmu_acr_bld_patch()
76 hdr.data_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_pmu_acr_bld_patch()
79 hdr.overlay_dma_base = lower_32_bits((addr + adjust) << 8); in gm20b_pmu_acr_bld_patch()
95 .code_dma_base = lower_32_bits(code), in gm20b_pmu_acr_bld_write()
99 .data_dma_base = lower_32_bits(data), in gm20b_pmu_acr_bld_write()
101 .overlay_dma_base = lower_32_bits(code), in gm20b_pmu_acr_bld_write()
/linux/drivers/pci/controller/
H A Dpci-xgene.c288 val = (val32 & 0x0000ffff) | (lower_32_bits(mask) << 16); in xgene_pcie_set_ib_mask()
292 val = (val32 & 0xffff0000) | (lower_32_bits(mask) >> 16); in xgene_pcie_set_ib_mask()
385 xgene_pcie_writel(port, offset, lower_32_bits(cpu_addr)); in xgene_pcie_setup_ob_reg()
387 xgene_pcie_writel(port, offset + 0x08, lower_32_bits(mask)); in xgene_pcie_setup_ob_reg()
389 xgene_pcie_writel(port, offset + 0x10, lower_32_bits(pci_addr)); in xgene_pcie_setup_ob_reg()
397 xgene_pcie_writel(port, CFGBARL, lower_32_bits(addr)); in xgene_pcie_setup_cfg_reg()
446 xgene_pcie_writel(port, pim_reg, lower_32_bits(pim)); in xgene_pcie_setup_pims()
449 xgene_pcie_writel(port, pim_reg + 0x10, lower_32_bits(size)); in xgene_pcie_setup_pims()
512 xgene_pcie_writel(port, IR2MSK, lower_32_bits(mask)); in xgene_pcie_setup_ib_reg()
518 xgene_pcie_writel(port, IR3MSKL, lower_32_bits(mask)); in xgene_pcie_setup_ib_reg()
H A Dpcie-rcar.c91 rcar_pci_write_reg(pcie, lower_32_bits(res_start) & ~0x7F, in rcar_pcie_set_outbound()
110 rcar_pci_write_reg(pcie, lower_32_bits(pci_addr), in rcar_pcie_set_inbound()
112 rcar_pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx)); in rcar_pcie_set_inbound()
/linux/drivers/media/pci/pt3/
H A Dpt3_dma.c52 iowrite32(lower_32_bits(adap->desc_buf[0].b_addr), in pt3_start_dma()
184 d->next_l = lower_32_bits(desc_addr); in pt3_alloc_dmabuf()
190 d->addr_l = lower_32_bits(data_addr); in pt3_alloc_dmabuf()
195 d->next_l = lower_32_bits(desc_addr); in pt3_alloc_dmabuf()
204 d->next_l = lower_32_bits(desc_addr); in pt3_alloc_dmabuf()
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dgm20b.c41 hdr.code_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
44 hdr.data_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
60 .code_dma_base = lower_32_bits(code), in gm20b_gr_acr_bld_write()
64 .data_dma_base = lower_32_bits(data), in gm20b_gr_acr_bld_write()
/linux/drivers/accel/habanalabs/common/
H A Dmemory_mgr.c25 buf = idr_find(&mmg->handles, lower_32_bits(handle >> PAGE_SHIFT)); in hl_mmap_mem_buf_get()
67 idr_remove(&buf->mmg->handles, lower_32_bits(buf->handle >> PAGE_SHIFT)); in hl_mmap_mem_buf_release()
86 idr_remove(&buf->mmg->handles, lower_32_bits(buf->handle >> PAGE_SHIFT)); in hl_mmap_mem_buf_remove_idr_locked()
118 buf = idr_find(&mmg->handles, lower_32_bits(handle >> PAGE_SHIFT)); in hl_mmap_mem_buf_put_handle()
185 idr_remove(&mmg->handles, lower_32_bits(buf->handle >> PAGE_SHIFT)); in hl_mmap_mem_buf_alloc()
/linux/include/linux/
H A Dwordpart.h20 #define lower_32_bits(n) ((u32)((n) & 0xffffffff)) macro
48 #define REPEAT_BYTE_U32(x) lower_32_bits(REPEAT_BYTE(x))
H A Dgoldfish.h23 gf_iowrite32(lower_32_bits(addr), portl); in gf_write_ptr()
33 gf_iowrite32(lower_32_bits(addr), portl); in gf_write_dma_addr()
/linux/drivers/gpu/drm/tegra/
H A Driscv.c79 riscv_writel(riscv, lower_32_bits(addr >> 8), RISCV_BCR_DMAADDR_PKCPARAM_LO); in tegra_drm_riscv_boot_bootrom()
83 riscv_writel(riscv, lower_32_bits(addr >> 8), RISCV_BCR_DMAADDR_FMCCODE_LO); in tegra_drm_riscv_boot_bootrom()
87 riscv_writel(riscv, lower_32_bits(addr >> 8), RISCV_BCR_DMAADDR_FMCDATA_LO); in tegra_drm_riscv_boot_bootrom()
/linux/drivers/pci/controller/dwc/
H A Dpcie-tegra194-acpi.c52 atu_reg_write(pcie_ecam, index, lower_32_bits(cpu_addr), in program_outbound_atu()
56 atu_reg_write(pcie_ecam, index, lower_32_bits(pci_addr), in program_outbound_atu()
58 atu_reg_write(pcie_ecam, index, lower_32_bits(cpu_addr + size - 1), in program_outbound_atu()
/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_bo74c1.c49 0x030c, lower_32_bits(mem->vma[0].addr), in nv84_bo_move_exec()
51 0x0314, lower_32_bits(mem->vma[1].addr), in nv84_bo_move_exec()

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