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Searched refs:hwsq (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/nouveau/nvkm/subdev/bus/
H A Dhwsq.c37 hwsq_cmd(struct nvkm_hwsq *hwsq, int size, u8 data[]) in hwsq_cmd() argument
39 memcpy(&hwsq->c.data[hwsq->c.size], data, size * sizeof(data[0])); in hwsq_cmd()
40 hwsq->c.size += size; in hwsq_cmd()
46 struct nvkm_hwsq *hwsq; in nvkm_hwsq_init() local
48 hwsq = *phwsq = kmalloc(sizeof(*hwsq), GFP_KERNEL); in nvkm_hwsq_init()
49 if (hwsq) { in nvkm_hwsq_init()
50 hwsq->subdev = subdev; in nvkm_hwsq_init()
51 hwsq->addr = ~0; in nvkm_hwsq_init()
52 hwsq->data = ~0; in nvkm_hwsq_init()
53 memset(hwsq->c.data, 0x7f, sizeof(hwsq->c.data)); in nvkm_hwsq_init()
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H A Dhwsq.h6 struct hwsq { struct
8 struct nvkm_hwsq *hwsq; member
61 hwsq_init(struct hwsq *ram, struct nvkm_subdev *subdev) in hwsq_init()
65 ret = nvkm_hwsq_init(subdev, &ram->hwsq); in hwsq_init()
75 hwsq_exec(struct hwsq *ram, bool exec) in hwsq_exec()
79 ret = nvkm_hwsq_fini(&ram->hwsq, exec); in hwsq_exec()
86 hwsq_rd32(struct hwsq *ram, struct hwsq_reg *reg) in hwsq_rd32()
95 hwsq_wr32(struct hwsq *ram, struct hwsq_reg *reg, u32 data) in hwsq_wr32()
104 nvkm_hwsq_wr32(ram->hwsq, reg->addr+off, reg->data); in hwsq_wr32()
111 hwsq_nuke(struct hwsq *ram, struct hwsq_reg *reg) in hwsq_nuke()
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H A DKbuild3 nvkm-y += nvkm/subdev/bus/hwsq.o
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dramnv50.c39 struct hwsq base;
68 struct nv50_ramseq hwsq; member
183 nvkm_sddr2_dll_reset(struct nv50_ramseq *hwsq) in nvkm_sddr2_dll_reset() argument
185 ram_mask(hwsq, mr[0], 0x100, 0x100); in nvkm_sddr2_dll_reset()
186 ram_mask(hwsq, mr[0], 0x100, 0x000); in nvkm_sddr2_dll_reset()
187 ram_nsec(hwsq, 24000); in nvkm_sddr2_dll_reset()
191 nv50_ram_gpio(struct nv50_ramseq *hwsq, u8 tag, u32 val) in nv50_ram_gpio() argument
193 struct nvkm_gpio *gpio = hwsq->base.subdev->device->gpio; in nv50_ram_gpio()
205 gpio_val = ram_rd32(hwsq, gpio[reg]); in nv50_ram_gpio()
212 ram_mask(hwsq, gpio[reg], (0x3 << sh), ((val | 0x2) << sh)); in nv50_ram_gpio()
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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dnv50.c372 struct nv50_clk_hwsq *hwsq = &clk->hwsq; in nv50_clk_calc() local
385 out = clk_init(hwsq, subdev); in nv50_clk_calc()
389 clk_wr32(hwsq, fifo, 0x00000001); /* block fifo */ in nv50_clk_calc()
390 clk_nsec(hwsq, 8000); in nv50_clk_calc()
391 clk_setf(hwsq, 0x10, 0x00); /* disable fb */ in nv50_clk_calc()
392 clk_wait(hwsq, 0x00, 0x01); /* wait for fb disabled */ in nv50_clk_calc()
447 clk_mask(hwsq, mast, mastm, 0x00000000); in nv50_clk_calc()
448 clk_mask(hwsq, divs, divsm, divsv); in nv50_clk_calc()
449 clk_mask(hwsq, mast, mastm, mastv); in nv50_clk_calc()
455 clk_mask(hwsq, mast, 0x001000b0, 0x00100080); in nv50_clk_calc()
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H A Dnv50.h10 struct hwsq base;
20 struct nv50_clk_hwsq hwsq; member