Searched refs:hard_min_level (Results 1 – 7 of 7) sorted by relevance
490 dpm_state->hard_min_level = 0x0; in vega12_init_dpm_state()1184 min_freq = data->dpm_table.mem_table.dpm_state.hard_min_level; in vega12_upload_dpm_min_level()1236 min_freq = data->dpm_table.dcef_table.dpm_state.hard_min_level; in vega12_upload_dpm_min_level()2014 uint32_t soft_min_level, soft_max_level, hard_min_level; in vega12_force_clock_level() local2088 hard_min_level = mask ? (ffs(mask) - 1) : 0; in vega12_force_clock_level()2090 if (hard_min_level >= data->dpm_table.dcef_table.count) { in vega12_force_clock_level()2092 hard_min_level, in vega12_force_clock_level()2097 data->dpm_table.dcef_table.dpm_state.hard_min_level = in vega12_force_clock_level()2098 data->dpm_table.dcef_table.dpm_levels[hard_min_level].value; in vega12_force_clock_level()2378 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; in vega12_apply_clocks_adjust_rules()[all …]
532 dpm_state->hard_min_level = 0x0; in vega20_init_dpm_state()1908 min_freq = data->dpm_table.dcef_table.dpm_state.hard_min_level; in vega20_upload_dpm_min_level()2380 dpm_table->dpm_state.hard_min_level = min_clocks.memoryClock / 100; in vega20_notify_smc_display_config_after_ps_adjustment()2383 (PPCLK_UCLK << 16) | dpm_table->dpm_state.hard_min_level, in vega20_notify_smc_display_config_after_ps_adjustment()2571 uint32_t soft_min_level, soft_max_level, hard_min_level; in vega20_force_clock_level() local2687 hard_min_level = mask ? (ffs(mask) - 1) : 0; in vega20_force_clock_level()2689 if (hard_min_level >= data->dpm_table.dcef_table.count) { in vega20_force_clock_level()2691 hard_min_level, in vega20_force_clock_level()2696 data->dpm_table.dcef_table.dpm_state.hard_min_level = in vega20_force_clock_level()2697 data->dpm_table.dcef_table.dpm_levels[hard_min_level].value; in vega20_force_clock_level()[all …]
102 uint32_t hard_min_level; member
129 uint32_t hard_min_level; member
155 uint32_t hard_min_level; member
42 uint32_t hard_min_level; member