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Searched refs:gvt (Results 1 – 24 of 24) sorted by relevance

/linux/drivers/gpu/drm/i915/gvt/
H A DMakefile4 gvt/aperture_gm.o \
5 gvt/cfg_space.o \
6 gvt/cmd_parser.o \
7 gvt/debugfs.o \
8 gvt/display.o \
9 gvt/dmabuf.o \
10 gvt/edid.o \
11 gvt/execlist.o \
12 gvt/fb_decoder.o \
13 gvt/firmware.o \
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H A Daperture_gm.c44 struct intel_gvt *gvt = vgpu->gvt; in alloc_gm() local
45 struct intel_gt *gt = gvt->gt; in alloc_gm()
54 start = ALIGN(gvt_hidden_gmadr_base(gvt), I915_GTT_PAGE_SIZE); in alloc_gm()
55 end = ALIGN(gvt_hidden_gmadr_end(gvt), I915_GTT_PAGE_SIZE); in alloc_gm()
60 start = ALIGN(gvt_aperture_gmadr_base(gvt), I915_GTT_PAGE_SIZE); in alloc_gm()
61 end = ALIGN(gvt_aperture_gmadr_end(gvt), I915_GTT_PAGE_SIZE); in alloc_gm()
82 struct intel_gvt *gvt = vgpu->gvt; in alloc_vgpu_gm() local
83 struct intel_gt *gt = gvt->gt; in alloc_vgpu_gm()
110 struct intel_gvt *gvt = vgpu->gvt; in free_vgpu_gm() local
111 struct intel_gt *gt = gvt->gt; in free_vgpu_gm()
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H A Dsched_policy.c42 for_each_engine(engine, vgpu->gvt->gt, i) { in vgpu_has_pending_workload()
68 struct intel_gvt *gvt; member
80 if (!vgpu || vgpu == vgpu->gvt->idle_vgpu) in vgpu_update_timeslice()
132 static void try_to_schedule_next_vgpu(struct intel_gvt *gvt) in try_to_schedule_next_vgpu() argument
134 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; in try_to_schedule_next_vgpu()
155 for_each_engine(engine, gvt->gt, i) { in try_to_schedule_next_vgpu()
172 for_each_engine(engine, gvt->gt, i) in try_to_schedule_next_vgpu()
213 struct intel_gvt *gvt = sched_data->gvt; in tbs_sched_func() local
214 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; in tbs_sched_func()
233 scheduler->next_vgpu = gvt->idle_vgpu; in tbs_sched_func()
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H A Dgvt.h184 struct intel_gvt *gvt; member
382 static inline void intel_gvt_request_service(struct intel_gvt *gvt, in intel_gvt_request_service() argument
385 set_bit(service, (void *)&gvt->service_request); in intel_gvt_request_service()
386 wake_up(&gvt->service_thread_wq); in intel_gvt_request_service()
389 void intel_gvt_free_firmware(struct intel_gvt *gvt);
390 int intel_gvt_load_firmware(struct intel_gvt *gvt);
400 #define gvt_to_ggtt(gvt) ((gvt)->gt->ggtt) argument
403 #define gvt_aperture_sz(gvt) gvt_to_ggtt(gvt)->mappable_end argument
404 #define gvt_aperture_pa_base(gvt) gvt_to_ggtt(gvt)->gmadr.start argument
406 #define gvt_ggtt_gm_sz(gvt) gvt_to_ggtt(gvt)->vm.total argument
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H A Ddebugfs.c58 static inline int mmio_diff_handler(struct intel_gvt *gvt, in mmio_diff_handler() argument
65 preg = intel_uncore_read_notrace(gvt->gt->uncore, _MMIO(offset)); in mmio_diff_handler()
87 struct intel_gvt *gvt = vgpu->gvt; in vgpu_mmio_diff_show() local
97 mutex_lock(&gvt->lock); in vgpu_mmio_diff_show()
98 spin_lock_bh(&gvt->scheduler.mmio_context_lock); in vgpu_mmio_diff_show()
100 mmio_hw_access_pre(gvt->gt); in vgpu_mmio_diff_show()
102 intel_gvt_for_each_tracked_mmio(gvt, mmio_diff_handler, &param); in vgpu_mmio_diff_show()
103 mmio_hw_access_post(gvt->gt); in vgpu_mmio_diff_show()
105 spin_unlock_bh(&gvt->scheduler.mmio_context_lock); in vgpu_mmio_diff_show()
106 mutex_unlock(&gvt->lock); in vgpu_mmio_diff_show()
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H A Dkvmgt.c180 struct device *dev = vgpu->gvt->gt->i915->drm.dev; in gvt_dma_map_page()
203 struct device *dev = vgpu->gvt->gt->i915->drm.dev; in gvt_dma_unmap_page()
647 mutex_lock(&vgpu->gvt->lock); in __kvmgt_vgpu_exist()
648 for_each_active_vgpu(vgpu->gvt, itr, id) { in __kvmgt_vgpu_exist()
658 mutex_unlock(&vgpu->gvt->lock); in __kvmgt_vgpu_exist()
783 aperture_va = io_mapping_map_wc(&vgpu->gvt->gt->ggtt->iomap, in intel_vgpu_aperture_rw()
850 struct intel_gvt *gvt = vgpu->gvt; in gtt_entry() local
860 return (offset >= gvt->device_info.gtt_start_offset && in gtt_entry()
861 offset < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt)) ? in gtt_entry()
1046 pgoff = (gvt_aperture_pa_base(vgpu->gvt) >> PAGE_SHIFT) + pgoff; in intel_vgpu_mmap()
[all …]
H A Dmmio.h71 intel_gvt_render_mmio_to_engine(struct intel_gvt *gvt, unsigned int reg);
72 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt);
74 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt);
75 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt);
76 int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt,
77 int (*handler)(struct intel_gvt *gvt, u32 offset, void *data),
80 struct intel_gvt_mmio_info *intel_gvt_find_mmio_info(struct intel_gvt *gvt,
99 bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
108 void intel_gvt_restore_fence(struct intel_gvt *gvt);
109 void intel_gvt_restore_mmio(struct intel_gvt *gvt);
H A Dinterrupt.c166 struct intel_gvt *gvt, in regbase_to_irq_info() argument
169 struct intel_gvt_irq *irq = &gvt->irq; in regbase_to_irq_info()
197 struct intel_gvt *gvt = vgpu->gvt; in intel_vgpu_reg_imr_handler() local
198 const struct intel_gvt_irq_ops *ops = gvt->irq.ops; in intel_vgpu_reg_imr_handler()
227 struct intel_gvt *gvt = vgpu->gvt; in intel_vgpu_reg_master_irq_handler() local
228 const struct intel_gvt_irq_ops *ops = gvt->irq.ops; in intel_vgpu_reg_master_irq_handler()
266 struct intel_gvt *gvt = vgpu->gvt; in intel_vgpu_reg_ier_handler() local
267 struct drm_i915_private *i915 = gvt->gt->i915; in intel_vgpu_reg_ier_handler()
268 const struct intel_gvt_irq_ops *ops = gvt->irq.ops; in intel_vgpu_reg_ier_handler()
277 info = regbase_to_irq_info(gvt, ier_to_regbase(reg)); in intel_vgpu_reg_ier_handler()
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H A Dsched_policy.h41 int (*init)(struct intel_gvt *gvt);
42 void (*clean)(struct intel_gvt *gvt);
49 void intel_gvt_schedule(struct intel_gvt *gvt);
51 int intel_gvt_init_sched_policy(struct intel_gvt *gvt);
53 void intel_gvt_clean_sched_policy(struct intel_gvt *gvt);
63 void intel_gvt_kick_schedule(struct intel_gvt *gvt);
H A Dmmio_context.c176 struct intel_gvt *gvt = engine->i915->gvt; in load_render_mocs() local
178 u32 cnt = gvt->engine_mmio_list.mocs_mmio_offset_list_cnt; in load_render_mocs()
179 u32 *regs = gvt->engine_mmio_list.mocs_mmio_offset_list; in load_render_mocs()
215 struct intel_gvt *gvt = vgpu->gvt; in restore_context_mmio_for_inhibit() local
217 int count = gvt->engine_mmio_list.ctx_mmio_count[ring_id]; in restore_context_mmio_for_inhibit()
231 for (mmio = gvt->engine_mmio_list.mmio; in restore_context_mmio_for_inhibit()
366 u32 *regs = vgpu->gvt->engine_mmio_list.tlb_mmio_offset_list; in handle_tlb_pending_event()
367 u32 cnt = vgpu->gvt->engine_mmio_list.tlb_mmio_offset_list_cnt; in handle_tlb_pending_event()
493 for (mmio = engine->i915->gvt->engine_mmio_list.mmio; in switch_mmio()
592 void intel_gvt_init_engine_mmio_context(struct intel_gvt *gvt) in intel_gvt_init_engine_mmio_context() argument
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H A Dcfg_space.c120 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in intel_vgpu_emulate_cfg_read()
126 offset + bytes > vgpu->gvt->device_info.cfg_space_size)) in intel_vgpu_emulate_cfg_read()
259 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in intel_vgpu_emulate_cfg_write()
266 offset + bytes > vgpu->gvt->device_info.cfg_space_size)) in intel_vgpu_emulate_cfg_write()
322 struct intel_gvt *gvt = vgpu->gvt; in intel_vgpu_init_cfg_space() local
323 struct pci_dev *pdev = to_pci_dev(gvt->gt->i915->drm.dev); in intel_vgpu_init_cfg_space()
324 const struct intel_gvt_device_info *info = &gvt->device_info; in intel_vgpu_init_cfg_space()
328 memcpy(vgpu_cfg_space(vgpu), gvt->firmware.cfg_space, in intel_vgpu_init_cfg_space()
343 gvt_aperture_pa_base(gvt), true); in intel_vgpu_init_cfg_space()
H A Dcmd_parser.h46 void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt);
48 int intel_gvt_init_cmd_parser(struct intel_gvt *gvt);
H A Dgtt.h223 int intel_gvt_init_gtt(struct intel_gvt *gvt);
224 void intel_gvt_clean_gtt(struct intel_gvt *gvt);
291 void intel_gvt_restore_ggtt(struct intel_gvt *gvt);
H A Dedid.c143 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in gmbus0_mmio_write()
284 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in gmbus3_mmio_write()
381 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in intel_gvt_i2c_handle_gmbus_read()
411 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in intel_gvt_i2c_handle_gmbus_write()
483 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in intel_gvt_i2c_handle_aux_ch_write()
H A Dscheduler.h139 int intel_gvt_init_workload_scheduler(struct intel_gvt *gvt);
141 void intel_gvt_clean_workload_scheduler(struct intel_gvt *gvt);
H A Dfb_decoder.c156 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; in intel_vgpu_get_stride()
212 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; in intel_vgpu_decode_primary_plane()
342 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; in intel_vgpu_decode_cursor_plane()
H A Dmmio_context.h53 void intel_gvt_init_engine_mmio_context(struct intel_gvt *gvt);
H A Dtrace.h40 #define TRACE_SYSTEM gvt
381 #define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/i915/gvt
H A Dinterrupt.h193 int intel_gvt_init_irq(struct intel_gvt *gvt);
H A Dexeclist.c529 for_each_engine_masked(engine, vgpu->gvt->gt, engine_mask, tmp) { in clean_execlist()
542 for_each_engine_masked(engine, vgpu->gvt->gt, engine_mask, tmp) in reset_execlist()
H A Ddmabuf.c405 struct drm_device *dev = &vgpu->gvt->gt->i915->drm; in intel_vgpu_query_plane()
503 struct drm_device *dev = &vgpu->gvt->gt->i915->drm; in intel_vgpu_get_dmabuf()
/linux/drivers/gpu/drm/i915/
H A Dintel_gvt.c185 if (dev_priv->gvt) in intel_gvt_clean_device()
278 if (dev_priv->gvt) in intel_gvt_resume()
H A Di915_drv.h209 struct intel_gvt *gvt; member
/linux/
H A DMAINTAINERS11547 L: intel-gvt-dev@lists.freedesktop.org
11550 W: https://github.com/intel/gvt-linux/wiki
11551 T: git https://github.com/intel/gvt-linux.git
11552 F: drivers/gpu/drm/i915/gvt/