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Searched refs:gpu_write (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/msm/adreno/
H A Da3xx_gpu.c123 gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010); in a3xx_hw_init()
124 gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF1, 0x10101010); in a3xx_hw_init()
125 gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x10101010); in a3xx_hw_init()
126 gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x10101010); in a3xx_hw_init()
127 gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303); in a3xx_hw_init()
128 gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x10101010); in a3xx_hw_init()
129 gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF1, 0x10101010); in a3xx_hw_init()
131 gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x0000ff); in a3xx_hw_init()
133 gpu_write(gpu, REG_A3XX_VBIF_ARB_CTL, 0x00000030); in a3xx_hw_init()
135 gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003c); in a3xx_hw_init()
[all …]
H A Da2xx_gpu.c124 gpu_write(gpu, REG_AXXX_CP_ME_CNTL, AXXX_CP_ME_CNTL_HALT); in a2xx_hw_init()
126 gpu_write(gpu, REG_A2XX_RBBM_PM_OVERRIDE1, 0xfffffffe); in a2xx_hw_init()
127 gpu_write(gpu, REG_A2XX_RBBM_PM_OVERRIDE2, 0xffffffff); in a2xx_hw_init()
130 gpu_write(gpu, REG_A2XX_RBBM_SOFT_RESET, 0xffffffff); in a2xx_hw_init()
132 gpu_write(gpu, REG_A2XX_RBBM_SOFT_RESET, 0x00000000); in a2xx_hw_init()
135 gpu_write(gpu, REG_A2XX_SQ_FLOW_CONTROL, 0x18000000); in a2xx_hw_init()
138 gpu_write(gpu, REG_A2XX_RBBM_CNTL, 0x00004442); in a2xx_hw_init()
141 gpu_write(gpu, REG_A2XX_MH_MMU_MPU_BASE, 0x00000000); in a2xx_hw_init()
142 gpu_write(gpu, REG_A2XX_MH_MMU_MPU_END, 0xfffff000); in a2xx_hw_init()
144 gpu_write(gpu, REG_A2XX_MH_MMU_CONFIG, A2XX_MH_MMU_CONFIG_MMU_ENABLE | in a2xx_hw_init()
[all …]
H A Da8xx_gpu.c30 gpu_write(gpu, REG_A8XX_CP_APERTURE_CNTL_HOST, val); in a8xx_aperture_slice_set()
66 gpu_write(gpu, offset, data); in a8xx_write_pipe()
204 gpu_write(gpu, REG_A8XX_RBBM_CGC_0_PC, 0x00000702); in a8xx_set_hwcg()
213 gpu_write(gpu, REG_A8XX_RBBM_CLOCK_CNTL_GLOBAL, 1); in a8xx_set_hwcg()
214 gpu_write(gpu, REG_A8XX_RBBM_CGC_GLOBAL_LOAD_CMD, !!state); in a8xx_set_hwcg()
217 gpu_write(gpu, REG_A8XX_RBBM_CGC_P2S_TRIG_CMD, 1); in a8xx_set_hwcg()
225 gpu_write(gpu, REG_A8XX_RBBM_CLOCK_CNTL_GLOBAL, 0); in a8xx_set_hwcg()
259 gpu_write(gpu, REG_A8XX_CP_PROTECT_GLOBAL(i), protect->regs[i]); in a8xx_set_cp_protect()
352 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, in a8xx_set_ubwc_config()
360 gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, in a8xx_set_ubwc_config()
[all …]
H A Da2xx_gpummu.c56 gpu_write(gpummu->gpu, REG_A2XX_MH_MMU_INVALIDATE, in a2xx_gpummu_map()
71 gpu_write(gpummu->gpu, REG_A2XX_MH_MMU_INVALIDATE, in a2xx_gpummu_unmap()
H A Da5xx_preempt.c52 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in update_wptr()
168 gpu_write(gpu, REG_A5XX_CP_CONTEXT_SWITCH_CNTL, 1); in a5xx_preempt_trigger()
/linux/drivers/gpu/drm/etnaviv/
H A Detnaviv_iommu.c100 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_RA, context->global->memory_base); in etnaviv_iommuv1_restore()
101 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_FE, context->global->memory_base); in etnaviv_iommuv1_restore()
102 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_TX, context->global->memory_base); in etnaviv_iommuv1_restore()
103 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PEZ, context->global->memory_base); in etnaviv_iommuv1_restore()
104 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PE, context->global->memory_base); in etnaviv_iommuv1_restore()
109 gpu_write(gpu, VIVS_MC_MMU_FE_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
110 gpu_write(gpu, VIVS_MC_MMU_TX_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
111 gpu_write(gpu, VIVS_MC_MMU_PE_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
112 gpu_write(gpu, VIVS_MC_MMU_PEZ_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
113 gpu_write(gpu, VIVS_MC_MMU_RA_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
H A Detnaviv_iommu_v2.c186 gpu_write(gpu, VIVS_MMUv2_CONTROL, VIVS_MMUv2_CONTROL_ENABLE); in etnaviv_iommuv2_restore_nonsec()
203 gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_LOW, in etnaviv_iommuv2_restore_sec()
205 gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_HIGH, in etnaviv_iommuv2_restore_sec()
207 gpu_write(gpu, VIVS_MMUv2_PTA_CONTROL, VIVS_MMUv2_PTA_CONTROL_ENABLE); in etnaviv_iommuv2_restore_sec()
209 gpu_write(gpu, VIVS_MMUv2_NONSEC_SAFE_ADDR_LOW, in etnaviv_iommuv2_restore_sec()
211 gpu_write(gpu, VIVS_MMUv2_SEC_SAFE_ADDR_LOW, in etnaviv_iommuv2_restore_sec()
213 gpu_write(gpu, VIVS_MMUv2_SAFE_ADDRESS_CONFIG, in etnaviv_iommuv2_restore_sec()
228 gpu_write(gpu, VIVS_MMUv2_SEC_CONTROL, VIVS_MMUv2_SEC_CONTROL_ENABLE); in etnaviv_iommuv2_restore_sec()
H A Detnaviv_gpu.c504 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock | in etnaviv_gpu_load_clock()
506 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); in etnaviv_gpu_load_clock()
563 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
566 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, in etnaviv_hw_reset()
571 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
579 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
583 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
606 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
698 gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address); in etnaviv_gpu_start_fe()
699 gpu_write(gpu, VIVS_FE_COMMAND_CONTROL, in etnaviv_gpu_start_fe()
[all …]
H A Detnaviv_sched.c59 gpu_write(gpu, VIVS_MC_PROFILE_CONFIG0, in etnaviv_sched_timedout_job()
H A Detnaviv_gpu.h170 static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data) in gpu_write() function
/linux/drivers/gpu/drm/msm/
H A Dmsm_gpu.h595 static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data) in gpu_write() function
/linux/drivers/gpu/drm/i915/gem/selftests/
H A Dhuge_pages.c1055 static int gpu_write(struct intel_context *ce, in gpu_write() function
1175 err = gpu_write(ce, vma, dword, val); in __igt_write_huge()
1891 err = gpu_write(ce, vma, n++, 0xdeadbeaf); in igt_shrink_thp()
/linux/drivers/gpu/drm/panthor/
H A Dpanthor_mmu.c529 gpu_write(ptdev, AS_COMMAND(as_nr), cmd); in as_send_cmd_and_wait()
762 gpu_write(ptdev, MMU_INT_CLEAR, fault_mask); in panthor_vm_active()
1766 gpu_write(ptdev, MMU_INT_CLEAR, mask); in panthor_mmu_irq_handler()
H A Dpanthor_sched.c3373 gpu_write(ptdev, CSF_DOORBELL(queue->doorbell_id), 1); in queue_run_job()