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Searched refs:gpu_write (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/gpu/drm/msm/adreno/
H A Da3xx_gpu.c125 gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010); in a3xx_hw_init()
126 gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF1, 0x10101010); in a3xx_hw_init()
127 gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x10101010); in a3xx_hw_init()
128 gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x10101010); in a3xx_hw_init()
129 gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303); in a3xx_hw_init()
130 gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x10101010); in a3xx_hw_init()
131 gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF1, 0x10101010); in a3xx_hw_init()
133 gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x0000ff); in a3xx_hw_init()
135 gpu_write(gpu, REG_A3XX_VBIF_ARB_CTL, 0x00000030); in a3xx_hw_init()
137 gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003c); in a3xx_hw_init()
[all …]
H A Da5xx_gpu.c63 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in a5xx_flush()
465 gpu_write(gpu, regs[i].offset, in a5xx_set_hwcg()
469 gpu_write(gpu, REG_A5XX_RBBM_CLOCK_DELAY_GPMU, state ? 0x00000770 : 0); in a5xx_set_hwcg()
470 gpu_write(gpu, REG_A5XX_RBBM_CLOCK_HYST_GPMU, state ? 0x00000004 : 0); in a5xx_set_hwcg()
473 gpu_write(gpu, REG_A5XX_RBBM_CLOCK_CNTL, state ? 0xAAA8AA00 : 0); in a5xx_set_hwcg()
474 gpu_write(gpu, REG_A5XX_RBBM_ISDB_CNT, state ? 0x182 : 0x180); in a5xx_set_hwcg()
702 gpu_write(gpu, REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003); in a5xx_hw_init()
706 gpu_write(gpu, REG_A5XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009); in a5xx_hw_init()
709 gpu_write(gpu, REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xFFFFFFFF); in a5xx_hw_init()
712 gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL0, 0x00000001); in a5xx_hw_init()
[all …]
H A Da8xx_gpu.c30 gpu_write(gpu, REG_A8XX_CP_APERTURE_CNTL_HOST, val); in a8xx_aperture_slice_set()
66 gpu_write(gpu, offset, data); in a8xx_write_pipe()
204 gpu_write(gpu, REG_A8XX_RBBM_CGC_0_PC, 0x00000702); in a8xx_set_hwcg()
213 gpu_write(gpu, REG_A8XX_RBBM_CLOCK_CNTL_GLOBAL, 1); in a8xx_set_hwcg()
214 gpu_write(gpu, REG_A8XX_RBBM_CGC_GLOBAL_LOAD_CMD, !!state); in a8xx_set_hwcg()
217 gpu_write(gpu, REG_A8XX_RBBM_CGC_P2S_TRIG_CMD, 1); in a8xx_set_hwcg()
225 gpu_write(gpu, REG_A8XX_RBBM_CLOCK_CNTL_GLOBAL, 0); in a8xx_set_hwcg()
259 gpu_write(gpu, REG_A8XX_CP_PROTECT_GLOBAL(i), protect->regs[i]); in a8xx_set_cp_protect()
348 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, in a8xx_set_ubwc_config()
356 gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, in a8xx_set_ubwc_config()
[all …]
H A Da6xx_gpu.c49 gpu_write(gpu, offset, value); in fence_status_check()
65 gpu_write(gpu, offset, value); in fenced_write()
81 gpu_write(gpu, offset, value); in fenced_write()
685 gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 1); in a6xx_set_hwcg()
686 gpu_write(gpu, REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD, state ? 1 : 0); in a6xx_set_hwcg()
689 gpu_write(gpu, REG_A7XX_RBBM_CGC_P2S_TRIG_CMD, 1); in a6xx_set_hwcg()
697 gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 0); in a6xx_set_hwcg()
714 gpu_write(gpu, reg->offset, state ? reg->value : 0); in a6xx_set_hwcg()
720 gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0); in a6xx_set_hwcg()
734 gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, in a6xx_set_cp_protect()
[all …]
H A Da6xx_gpu_state.c165 gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 1); in a6xx_crashdumper_run()
170 gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 0); in a6xx_crashdumper_run()
189 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_A, reg); in debugbus_read()
190 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_B, reg); in debugbus_read()
191 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_C, reg); in debugbus_read()
192 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_D, reg); in debugbus_read()
243 gpu_write(gpu, ctrl0, reg); in vbif_debugbus_read()
246 gpu_write(gpu, ctrl1, i); in vbif_debugbus_read()
280 gpu_write(gpu, REG_A6XX_VBIF_CLKON, in a6xx_get_vbif_debugbus_block()
284 gpu_write(gpu, REG_A6XX_VBIF_TEST_BUS1_CTRL0, 0); in a6xx_get_vbif_debugbus_block()
[all …]
H A Da2xx_gpummu.c56 gpu_write(gpummu->gpu, REG_A2XX_MH_MMU_INVALIDATE, in a2xx_gpummu_map()
71 gpu_write(gpummu->gpu, REG_A2XX_MH_MMU_INVALIDATE, in a2xx_gpummu_unmap()
H A Da5xx_preempt.c52 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in update_wptr()
168 gpu_write(gpu, REG_A5XX_CP_CONTEXT_SWITCH_CNTL, 1); in a5xx_preempt_trigger()
H A Da6xx_gmu.c1033 gpu_write(gpu, gbif_cx[i].offset, gbif_cx[i].value); in a6xx_gmu_fw_start()
1036 gpu_write(gpu, REG_A6XX_GBIF_CX_CONFIG, 0x20023000); in a6xx_gmu_fw_start()
H A Dadreno_gpu.c749 gpu_write(gpu, reg, wptr); in adreno_flush()
/linux/drivers/gpu/drm/etnaviv/
H A Detnaviv_iommu.c100 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_RA, context->global->memory_base); in etnaviv_iommuv1_restore()
101 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_FE, context->global->memory_base); in etnaviv_iommuv1_restore()
102 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_TX, context->global->memory_base); in etnaviv_iommuv1_restore()
103 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PEZ, context->global->memory_base); in etnaviv_iommuv1_restore()
104 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PE, context->global->memory_base); in etnaviv_iommuv1_restore()
109 gpu_write(gpu, VIVS_MC_MMU_FE_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
110 gpu_write(gpu, VIVS_MC_MMU_TX_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
111 gpu_write(gpu, VIVS_MC_MMU_PE_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
112 gpu_write(gpu, VIVS_MC_MMU_PEZ_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
113 gpu_write(gpu, VIVS_MC_MMU_RA_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
H A Detnaviv_iommu_v2.c186 gpu_write(gpu, VIVS_MMUv2_CONTROL, VIVS_MMUv2_CONTROL_ENABLE); in etnaviv_iommuv2_restore_nonsec()
203 gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_LOW, in etnaviv_iommuv2_restore_sec()
205 gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_HIGH, in etnaviv_iommuv2_restore_sec()
207 gpu_write(gpu, VIVS_MMUv2_PTA_CONTROL, VIVS_MMUv2_PTA_CONTROL_ENABLE); in etnaviv_iommuv2_restore_sec()
209 gpu_write(gpu, VIVS_MMUv2_NONSEC_SAFE_ADDR_LOW, in etnaviv_iommuv2_restore_sec()
211 gpu_write(gpu, VIVS_MMUv2_SEC_SAFE_ADDR_LOW, in etnaviv_iommuv2_restore_sec()
213 gpu_write(gpu, VIVS_MMUv2_SAFE_ADDRESS_CONFIG, in etnaviv_iommuv2_restore_sec()
228 gpu_write(gpu, VIVS_MMUv2_SEC_CONTROL, VIVS_MMUv2_SEC_CONTROL_ENABLE); in etnaviv_iommuv2_restore_sec()
H A Detnaviv_gpu.c503 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock | in etnaviv_gpu_load_clock()
505 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); in etnaviv_gpu_load_clock()
562 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
565 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, in etnaviv_hw_reset()
570 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
578 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
582 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
622 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
714 gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address); in etnaviv_gpu_start_fe()
715 gpu_write(gpu, VIVS_FE_COMMAND_CONTROL, in etnaviv_gpu_start_fe()
[all …]
/linux/drivers/gpu/drm/panthor/
H A Dpanthor_device.h529 gpu_write(pirq->iomem, INT_MASK, 0); \
564 gpu_write(pirq->iomem, INT_MASK, pirq->mask); \
574 gpu_write(pirq->iomem, INT_MASK, 0); \
585 gpu_write(pirq->iomem, INT_CLEAR, pirq->mask); \
586 gpu_write(pirq->iomem, INT_MASK, pirq->mask); \
599 gpu_write(pirq->iomem, INT_MASK, 0); \
619 gpu_write(pirq->iomem, INT_MASK, pirq->mask); \
633 gpu_write(pirq->iomem, INT_MASK, pirq->mask); \
638 static inline void gpu_write(void __iomem *iomem, u32 reg, u32 data) in gpu_write() function
655 gpu_write(iomem, reg, lower_32_bits(data)); in gpu_write64()
[all …]
H A Dpanthor_gpu.c62 gpu_write(ptdev->gpu->iomem, GPU_COHERENCY_PROTOCOL, in panthor_gpu_coherency_set()
82 gpu_write(gpu->iomem, GPU_ASN_HASH(i), data->asn_hash[i]); in panthor_gpu_l2_config_set()
86 gpu_write(gpu->iomem, GPU_L2_CONFIG, l2_config); in panthor_gpu_l2_config_set()
93 gpu_write(gpu->irq.iomem, INT_CLEAR, status); in panthor_gpu_irq_handler()
342 gpu_write(gpu->iomem, GPU_CMD, GPU_FLUSH_CACHES(l2, lsc, other)); in panthor_gpu_flush_caches()
387 gpu_write(gpu->irq.iomem, INT_CLEAR, GPU_IRQ_RESET_COMPLETED); in panthor_gpu_soft_reset()
388 gpu_write(gpu->iomem, GPU_CMD, GPU_SOFT_RESET); in panthor_gpu_soft_reset()
H A Dpanthor_pwr.c64 gpu_write(pwr->irq.iomem, INT_CLEAR, status); in panthor_pwr_irq_handler()
87 gpu_write(pwr->iomem, PWR_COMMAND, command); in panthor_pwr_write_command()
111 gpu_write(pwr->irq.iomem, INT_CLEAR, PWR_IRQ_RESET_COMPLETED); in panthor_pwr_reset()
H A Dpanthor_fw.c1106 gpu_write(ptdev->fw->irq.iomem, INT_CLEAR, status); in panthor_job_irq_handler()
1135 gpu_write(fw->iomem, MCU_CONTROL, MCU_CONTROL_AUTO); in panthor_fw_start()
1167 gpu_write(fw->iomem, MCU_CONTROL, MCU_CONTROL_DISABLE); in panthor_fw_stop()
1439 gpu_write(ptdev->iomem, CSF_DOORBELL(doorbell_id), 1); in panthor_fw_ring_doorbell()
H A Dpanthor_mmu.c563 gpu_write(ptdev->mmu->iomem, AS_COMMAND(as_nr), cmd); in as_send_cmd_and_wait()
809 gpu_write(ptdev->mmu->irq.iomem, INT_CLEAR, fault_mask); in panthor_vm_active()
1909 gpu_write(mmu->irq.iomem, INT_CLEAR, mask); in panthor_mmu_irq_handler()
/linux/drivers/gpu/drm/msm/
H A Dmsm_gpu.h648 static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data) in gpu_write() function
/linux/drivers/gpu/drm/i915/gem/selftests/
H A Dhuge_pages.c1055 static int gpu_write(struct intel_context *ce, in gpu_write() function
1175 err = gpu_write(ce, vma, dword, val); in __igt_write_huge()
1891 err = gpu_write(ce, vma, n++, 0xdeadbeaf); in igt_shrink_thp()