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Searched refs:flushing (Results 1 – 25 of 48) sorted by relevance

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/linux/Documentation/admin-guide/hw-vuln/
H A Dl1tf.rst148 'L1D vulnerable' L1D flushing is disabled
191 The conditional mode avoids L1D flushing after VMEXITs which execute
373 the hypervisors, i.e. unconditional L1D flushing
386 mitigation, i.e. conditional L1D flushing
395 i.e. conditional L1D flushing.
413 The default is 'flush'. For details about L1D flushing see :ref:`l1d_flush`.
421 The KVM hypervisor mitigation mechanism, flushing the L1D cache when
466 To avoid the overhead of the default L1D flushing on VMENTER the
467 administrator can disable the flushing via the kernel command line and
479 the kernel, it's only required to enforce L1D flushing on VMENTER.
[all …]
H A Dl1d_flush.rst38 If the underlying CPU supports L1D flushing in hardware, the hardware
66 **NOTE** : The opt-in of a task for L1D flushing works only when the task's
68 requested L1D flushing is scheduled on a SMT-enabled core the kernel sends
H A Drsb.rst52 * All attack vectors can potentially be mitigated by flushing out any
59 **FIXME**: Currently we're flushing 32 entries. However, some CPU
232 .. [#amd-sbpb] IBPB without flushing of branch type predictions. Only exists for AMD.
/linux/Documentation/core-api/
H A Dcachetlb.rst7 This document describes the cache/tlb flushing interfaces called
17 thinking SMP cache/tlb flushing must be so inefficient, this is in
23 First, the TLB flushing interfaces, since they are the simplest. The
56 Here we are flushing a specific range of (user) virtual
108 Next, we have the cache flushing interfaces. In general, when Linux
130 The cache flushing routines below need only deal with cache flushing
165 Here we are flushing a specific range of (user) virtual
215 Here in these two interfaces we are flushing a specific range
343 Any necessary cache flushing or other coherency operations
380 coherency. It must do this by flushing the vmap range before doing
/linux/fs/xfs/
H A Dxfs_trans_ail.c473 int *flushing) in xfsaild_process_logitem() argument
513 (*flushing)++; in xfsaild_process_logitem()
546 int flushing = 0; in xfsaild_push() local
587 xfsaild_process_logitem(ailp, lip, &stuck, &flushing); in xfsaild_push()
631 } else if (((stuck + flushing) * 100) / count > 90) { in xfsaild_push()
/linux/drivers/infiniband/hw/mlx4/
H A Dmcg.c686 } else if (method == IB_SA_METHOD_DELETE_RESP && group->demux->flushing) in mlx4_ib_mcg_work_handler()
941 if (ctx->flushing) in mlx4_ib_mcg_multiplex_handler()
1065 ctx->flushing = 0; in mlx4_ib_mcg_port_init()
1134 cw->ctx->flushing = 0; in mcg_clean_task()
1142 if (ctx->flushing) in mlx4_ib_mcg_port_cleanup()
1145 ctx->flushing = 1; in mlx4_ib_mcg_port_cleanup()
1149 ctx->flushing = 0; in mlx4_ib_mcg_port_cleanup()
1155 ctx->flushing = 0; in mlx4_ib_mcg_port_cleanup()
/linux/drivers/accessibility/speakup/
H A Dthread.c35 (speakup_info.flushing || in speakup_thread()
H A Dspeakup_apollo.c163 if (speakup_info.flushing) { in do_catch_up()
164 speakup_info.flushing = 0; in do_catch_up()
H A Dspeakup_decext.c174 if (speakup_info.flushing) { in do_catch_up()
175 speakup_info.flushing = 0; in do_catch_up()
H A Dspeakup_keypc.c196 if (speakup_info.flushing) { in do_catch_up()
197 speakup_info.flushing = 0; in do_catch_up()
H A Dspeakup_acntpc.c195 if (speakup_info.flushing) { in do_catch_up()
196 speakup_info.flushing = 0; in do_catch_up()
H A Dspeakup_dectlk.c249 if (speakup_info.flushing) { in do_catch_up()
250 speakup_info.flushing = 0; in do_catch_up()
H A Dspeakup_dtlk.c209 if (speakup_info.flushing) { in do_catch_up()
210 speakup_info.flushing = 0; in do_catch_up()
/linux/Documentation/arch/x86/
H A Dpti.rst94 allows us to skip flushing the entire TLB when switching page
117 h. INVPCID is a TLB-flushing instruction which allows flushing
121 flushing a kernel address, we need to flush all PCIDs, so a
122 single kernel address flush will require a TLB-flushing CR3
/linux/Documentation/ABI/testing/
H A Dprocfs-diskstats40 20 time spent flushing
/linux/drivers/char/xillybus/
H A Dxillyusb.c142 unsigned int flushing; member
916 chan->flushing = 0; in process_in_opcode()
1140 if (chan->flushing) { in flush_downstream()
1169 chan->flushing = 1; in flush_downstream()
1187 while (chan->flushing) { in flush_downstream()
1189 !chan->flushing || in flush_downstream()
1201 while (chan->flushing) { in flush_downstream()
1208 !chan->flushing || in flush_downstream()
/linux/Documentation/block/
H A Dwriteback_cache_control.rst45 worry if the underlying devices need any explicit cache flushing and how
58 that it supports flushing caches by setting the
/linux/include/trace/events/
H A Djbd2.h261 __field( unsigned long, flushing )
275 __entry->flushing = stats->rs_flushing;
290 jiffies_to_msecs(__entry->flushing),
/linux/fs/ceph/
H A Dcaps.c1425 int flushing, u64 flush_tid, u64 oldest_flush_tid) in __prep_cap() argument
1461 arg->follows = flushing ? ci->i_head_snapc->seq : 0; in __prep_cap()
1474 if (flushing & CEPH_CAP_XATTR_EXCL) { in __prep_cap()
1492 arg->dirty = flushing; in __prep_cap()
1953 int flushing; in __mark_caps_flushing() local
1960 flushing = ci->i_dirty_caps; in __mark_caps_flushing()
1962 ceph_cap_string(flushing), in __mark_caps_flushing()
1964 ceph_cap_string(ci->i_flushing_caps | flushing)); in __mark_caps_flushing()
1965 ci->i_flushing_caps |= flushing; in __mark_caps_flushing()
1971 cf->caps = flushing; in __mark_caps_flushing()
[all …]
/linux/Documentation/driver-api/cxl/allocation/
H A Ddax.rst11 If the capacity is shared across hosts or persistent, appropriate flushing
/linux/Documentation/arch/riscv/
H A Dcmodx.rst55 userspace. The syscall performs a one-off icache flushing operation. The prctl
56 changes the Linux ABI to allow userspace to emit icache flushing operations.
/linux/Documentation/admin-guide/device-mapper/
H A Dlog-writes.rst20 to make it easier to detect improper waiting/flushing.
39 Any REQ_FUA requests bypass this flushing mechanism and are logged as soon as
/linux/arch/arm/mm/
H A Dcache-v7.S105 bne start_flush_levels @ LoU != 0, start flushing
113 beq start_flush_levels @ start flushing cache levels
/linux/drivers/net/wireless/ath/ath6kl/
H A Dtxrx.c692 bool flushing[ATH6KL_VIF_MAX] = {false}; in ath6kl_tx_complete() local
763 flushing[if_idx] = true; in ath6kl_tx_complete()
780 flushing[if_idx] = false; in ath6kl_tx_complete()
801 !flushing[vif->fw_vif_idx]) { in ath6kl_tx_complete()
/linux/Documentation/networking/devlink/
H A Dmlx5.rst272 Recover by flushing the tx queue and reset it.
275 Recover by flushing and re-creating all PTP channels.
305 Recover (if needed) by flushing the related queue and reset it.

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