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Searched refs:dwbc (Results 1 – 25 of 25) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Ddwb.h156 struct dwbc { struct
177 struct dwbc *dwbc, argument
181 struct dwbc *dwbc,
184 bool (*disable)(struct dwbc *dwbc);
187 struct dwbc *dwbc,
191 struct dwbc *dwbc);
194 struct dwbc *dwbc,
198 struct dwbc *dwbc,
202 struct dwbc *dwbc,
206 struct dwbc *dwbc,
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/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dwb.c50 static bool dwb2_get_caps(struct dwbc *dwbc, struct dwb_caps *caps) in dwb2_get_caps() argument
52 struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc); in dwb2_get_caps()
72 void dwb2_config_dwb_cnv(struct dwbc *dwbc, struct dc_dwb_params *params) in dwb2_config_dwb_cnv() argument
74 struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc); in dwb2_config_dwb_cnv()
99 static bool dwb2_enable(struct dwbc *dwbc, struct dc_dwb_params *params) in dwb2_enable() argument
101 struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc); in dwb2_enable()
121 dwb2_config_dwb_cnv(dwbc, params); in dwb2_enable()
124 dwb2_set_scaler(dwbc, params); in dwb2_enable()
135 bool dwb2_disable(struct dwbc *dwbc) in dwb2_disable() argument
137 struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc); in dwb2_disable()
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H A Ddcn20_dwb.h389 struct dwbc base;
402 bool dwb2_disable(struct dwbc *dwbc);
404 bool dwb2_is_enabled(struct dwbc *dwbc);
406 void dwb2_set_stereo(struct dwbc *dwbc,
409 void dwb2_set_new_content(struct dwbc *dwbc,
412 void dwb2_config_dwb_cnv(struct dwbc *dwbc,
415 void dwb2_set_scaler(struct dwbc *dwbc, struct dc_dwb_params *params);
/linux/drivers/gpu/drm/amd/display/dc/dwb/dcn30/
H A Ddcn30_dwb_cm.c273 struct dwbc *dwbc, in dwb3_ogam_set_input_transfer_func() argument
276 struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc); in dwb3_ogam_set_input_transfer_func()
286 cm_helper_translate_curve_to_hw_format(dwbc->ctx, in dwb3_ogam_set_input_transfer_func()
301 struct dwbc *dwbc, in dwb3_program_gamut_remap() argument
306 struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc); in dwb3_program_gamut_remap()
356 struct dwbc *dwbc, in dwb3_set_gamut_remap() argument
359 struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc); in dwb3_set_gamut_remap()
365 dwb3_program_gamut_remap(dwbc, NULL, adjust.gamut_coef_format, CM_GAMUT_REMAP_MODE_BYPASS); in dwb3_set_gamut_remap()
379 dwb3_program_gamut_remap(dwbc, arr_reg_val, in dwb3_set_gamut_remap()
382 dwb3_program_gamut_remap(dwbc, arr_reg_val, in dwb3_set_gamut_remap()
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H A Ddcn30_dwb.h871 struct dwbc base;
884 bool dwb3_enable(struct dwbc *dwbc, struct dc_dwb_params *params);
886 bool dwb3_disable(struct dwbc *dwbc);
888 bool dwb3_update(struct dwbc *dwbc, struct dc_dwb_params *params);
890 bool dwb3_is_enabled(struct dwbc *dwbc);
892 void dwb3_set_fc_enable(struct dwbc *dwbc, enum dwb_frame_capture_enable enable);
894 void dwb3_set_stereo(struct dwbc *dwbc,
897 void dwb3_set_new_content(struct dwbc *dwbc,
900 void dwb3_config_fc(struct dwbc *dwbc,
903 void dwb3_set_denorm(struct dwbc *dwbc, struct dc_dwb_params *params);
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/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_stream.c557 struct dwbc *dwb; in dc_stream_add_writeback()
578 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
599 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
611 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
629 struct dwbc *dwb = dc->res_pool->dwbc[dwb_pipe_inst]; in dc_stream_fc_disable_writeback()
709 struct dwbc *dwb = dc->res_pool->dwbc[dwb_pipe_inst]; in dc_stream_remove_writeback()
H A Ddc_hw_sequencer.c2731 struct dwbc *dwb = params->dwbc_enable_params.dwb; in hwss_dwbc_enable()
2740 struct dwbc *dwb = params->dwbc_disable_params.dwb; in hwss_dwbc_disable()
2748 struct dwbc *dwb = params->dwbc_update_params.dwb; in hwss_dwbc_update()
3423 struct dwbc *dwb, in hwss_add_dwbc_update()
3507 struct dwbc *dwb, in hwss_add_dwbc_enable()
3519 struct dwbc *dwb) in hwss_add_dwbc_disable()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/
H A Ddcn303_resource.c715 pool->dwbc[i] = &dwbc30->base; in dcn303_dwbc_create()
1044 if (pool->dwbc[i] != NULL) { in dcn303_resource_destruct()
1045 kfree(TO_DCN30_DWBC(pool->dwbc[i])); in dcn303_resource_destruct()
1046 pool->dwbc[i] = NULL; in dcn303_resource_destruct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/
H A Ddcn302_resource.c754 pool->dwbc[i] = &dwbc30->base; in dcn302_dwbc_create()
1100 if (pool->dwbc[i] != NULL) { in dcn302_resource_destruct()
1101 kfree(TO_DCN30_DWBC(pool->dwbc[i])); in dcn302_resource_destruct()
1102 pool->dwbc[i] = NULL; in dcn302_resource_destruct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn301/
H A Ddcn301_resource.c1147 if (pool->base.dwbc[i] != NULL) { in dcn301_destruct()
1148 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn301_destruct()
1149 pool->base.dwbc[i] = NULL; in dcn301_destruct()
1230 pool->dwbc[i] = &dwbc30->base; in dcn301_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_dwb.h254 struct dwbc base;
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/
H A Ddcn314_resource.c1533 if (pool->base.dwbc[i] != NULL) { in dcn314_resource_destruct()
1534 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn314_resource_destruct()
1535 pool->base.dwbc[i] = NULL; in dcn314_resource_destruct()
1624 pool->dwbc[i] = &dwbc30->base; in dcn31_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/
H A Ddcn316_resource.c1471 if (pool->base.dwbc[i] != NULL) { in dcn316_resource_destruct()
1472 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn316_resource_destruct()
1473 pool->base.dwbc[i] = NULL; in dcn316_resource_destruct()
1559 pool->dwbc[i] = &dwbc30->base; in dcn31_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/
H A Ddcn21_resource.c748 if (pool->base.dwbc[i] != NULL) { in dcn21_resource_destruct()
749 kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); in dcn21_resource_destruct()
750 pool->base.dwbc[i] = NULL; in dcn21_resource_destruct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.c1542 if (pool->base.dwbc[i] != NULL) { in dcn35_resource_destruct()
1543 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn35_resource_destruct()
1544 pool->base.dwbc[i] = NULL; in dcn35_resource_destruct()
1658 pool->dwbc[i] = &dwbc30->base; in dcn35_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/
H A Ddcn31_resource.c1475 if (pool->base.dwbc[i] != NULL) { in dcn31_resource_destruct()
1476 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn31_resource_destruct()
1477 pool->base.dwbc[i] = NULL; in dcn31_resource_destruct()
1566 pool->dwbc[i] = &dwbc30->base; in dcn31_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/
H A Ddcn315_resource.c1476 if (pool->base.dwbc[i] != NULL) { in dcn315_resource_destruct()
1477 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn315_resource_destruct()
1478 pool->base.dwbc[i] = NULL; in dcn315_resource_destruct()
1567 pool->dwbc[i] = &dwbc30->base; in dcn31_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn36/
H A Ddcn36_resource.c1529 if (pool->base.dwbc[i] != NULL) { in dcn36_resource_destruct()
1530 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn36_resource_destruct()
1531 pool->base.dwbc[i] = NULL; in dcn36_resource_destruct()
1645 pool->dwbc[i] = &dwbc30->base; in dcn35_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/
H A Ddcn321_resource.c1458 if (pool->base.dwbc[i] != NULL) { in dcn321_resource_destruct()
1459 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn321_resource_destruct()
1460 pool->base.dwbc[i] = NULL; in dcn321_resource_destruct()
1543 pool->dwbc[i] = &dwbc30->base; in dcn321_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/
H A Ddcn351_resource.c1522 if (pool->base.dwbc[i] != NULL) { in dcn351_resource_destruct()
1523 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn351_resource_destruct()
1524 pool->base.dwbc[i] = NULL; in dcn351_resource_destruct()
1638 pool->dwbc[i] = &dwbc30->base; in dcn35_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c3135 struct dwbc *dwb; in dcn401_program_all_writeback_pipes_in_tree_sequence()
3170 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn401_program_all_writeback_pipes_in_tree_sequence()
3193 struct dwbc *dwb; in dcn401_enable_writeback_sequence()
3199 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn401_enable_writeback_sequence()
3226 struct dwbc *dwb; in dcn401_disable_writeback_sequence()
3232 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn401_disable_writeback_sequence()
3252 struct dwbc *dwb; in dcn401_update_writeback_sequence()
3258 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn401_update_writeback_sequence()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c1176 if (pool->base.dwbc[i] != NULL) { in dcn30_resource_destruct()
1177 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn30_resource_destruct()
1178 pool->base.dwbc[i] = NULL; in dcn30_resource_destruct()
1270 pool->dwbc[i] = &dwbc30->base; in dcn30_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.c1185 if (pool->base.dwbc[i] != NULL) { in dcn20_resource_destruct()
1186 kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); in dcn20_resource_destruct()
1187 pool->base.dwbc[i] = NULL; in dcn20_resource_destruct()
2307 pool->dwbc[i] = &dwbc20->base; in dcn20_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.c1478 if (pool->base.dwbc[i] != NULL) { in dcn32_resource_destruct()
1479 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn32_resource_destruct()
1480 pool->base.dwbc[i] = NULL; in dcn32_resource_destruct()
1563 pool->dwbc[i] = &dwbc30->base; in dcn32_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_hwseq.c334 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i]; in dcn201_init_hw()