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Searched refs:dwbc (Results 1 – 25 of 25) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Ddwb.h156 struct dwbc { struct
177 struct dwbc *dwbc, argument
181 struct dwbc *dwbc,
184 bool (*disable)(struct dwbc *dwbc);
187 struct dwbc *dwbc,
191 struct dwbc *dwbc);
194 struct dwbc *dwbc,
198 struct dwbc *dwbc,
202 struct dwbc *dwbc,
206 struct dwbc *dwbc,
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/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dwb.c50 static bool dwb2_get_caps(struct dwbc *dwbc, struct dwb_caps *caps) in dwb2_get_caps() argument
52 struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc); in dwb2_get_caps()
72 void dwb2_config_dwb_cnv(struct dwbc *dwbc, struct dc_dwb_params *params) in dwb2_config_dwb_cnv() argument
74 struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc); in dwb2_config_dwb_cnv()
99 static bool dwb2_enable(struct dwbc *dwbc, struct dc_dwb_params *params) in dwb2_enable() argument
101 struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc); in dwb2_enable()
121 dwb2_config_dwb_cnv(dwbc, params); in dwb2_enable()
124 dwb2_set_scaler(dwbc, params); in dwb2_enable()
135 bool dwb2_disable(struct dwbc *dwbc) in dwb2_disable() argument
137 struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc); in dwb2_disable()
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H A Ddcn20_dwb.h389 struct dwbc base;
402 bool dwb2_disable(struct dwbc *dwbc);
404 bool dwb2_is_enabled(struct dwbc *dwbc);
406 void dwb2_set_stereo(struct dwbc *dwbc,
409 void dwb2_set_new_content(struct dwbc *dwbc,
412 void dwb2_config_dwb_cnv(struct dwbc *dwbc,
415 void dwb2_set_scaler(struct dwbc *dwbc, struct dc_dwb_params *params);
/linux/drivers/gpu/drm/amd/display/dc/dwb/dcn30/
H A Ddcn30_dwb_cm.c273 struct dwbc *dwbc, in dwb3_ogam_set_input_transfer_func() argument
276 struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc); in dwb3_ogam_set_input_transfer_func()
286 cm_helper_translate_curve_to_hw_format(dwbc->ctx, in dwb3_ogam_set_input_transfer_func()
301 struct dwbc *dwbc, in dwb3_program_gamut_remap() argument
306 struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc); in dwb3_program_gamut_remap()
356 struct dwbc *dwbc, in dwb3_set_gamut_remap() argument
359 struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc); in dwb3_set_gamut_remap()
365 dwb3_program_gamut_remap(dwbc, NULL, adjust.gamut_coef_format, CM_GAMUT_REMAP_MODE_BYPASS); in dwb3_set_gamut_remap()
379 dwb3_program_gamut_remap(dwbc, arr_reg_val, in dwb3_set_gamut_remap()
382 dwb3_program_gamut_remap(dwbc, arr_reg_val, in dwb3_set_gamut_remap()
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H A Ddcn30_dwb.h871 struct dwbc base;
884 bool dwb3_enable(struct dwbc *dwbc, struct dc_dwb_params *params);
886 bool dwb3_disable(struct dwbc *dwbc);
888 bool dwb3_update(struct dwbc *dwbc, struct dc_dwb_params *params);
890 bool dwb3_is_enabled(struct dwbc *dwbc);
892 void dwb3_set_fc_enable(struct dwbc *dwbc, enum dwb_frame_capture_enable enable);
894 void dwb3_set_stereo(struct dwbc *dwbc,
897 void dwb3_set_new_content(struct dwbc *dwbc,
900 void dwb3_config_fc(struct dwbc *dwbc,
903 void dwb3_set_denorm(struct dwbc *dwbc, struct dc_dwb_params *params);
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/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_stream.c598 struct dwbc *dwb; in dc_stream_add_writeback()
619 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
640 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_fc_disable_writeback()
652 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_fc_disable_writeback()
670 struct dwbc *dwb = dc->res_pool->dwbc[dwb_pipe_inst]; in dc_stream_remove_writeback()
750 struct dwbc *dwb = dc->res_pool->dwbc[dwb_pipe_inst]; in dc_stream_send_dp_sdp()
H A Ddc_hw_sequencer.c3129 struct dwbc *dwb = params->dwbc_enable_params.dwb; in hwss_set_cursor_position()
3138 struct dwbc *dwb = params->dwbc_disable_params.dwb; in hwss_set_cursor_sdr_white_level()
3146 struct dwbc *dwb = params->dwbc_update_params.dwb; in hwss_program_output_csc()
4103 struct dwbc *dwb, in hwss_add_tg_get_frame_count()
4187 struct dwbc *dwb,
4199 struct dwbc *dwb)
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/
H A Ddcn303_resource.c803 pool->dwbc[i] = &dwbc30->base;
1150 if (pool->dwbc[i] != NULL) {
1151 kfree(TO_DCN30_DWBC(pool->dwbc[i]));
1152 pool->dwbc[i] = NULL;
1533 dm_error("DC: failed to create dwbc!\n");
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/
H A Ddcn302_resource.c842 pool->dwbc[i] = &dwbc30->base;
1206 if (pool->dwbc[i] != NULL) {
1207 kfree(TO_DCN30_DWBC(pool->dwbc[i]));
1208 pool->dwbc[i] = NULL;
1601 dm_error("DC: failed to create dwbc!\n");
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn301/
H A Ddcn301_resource.c1148 if (pool->base.dwbc[i] != NULL) { in dcn301_destruct()
1149 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn301_destruct()
1150 pool->base.dwbc[i] = NULL; in dcn301_destruct()
1231 pool->dwbc[i] = &dwbc30->base; in dcn301_dwbc_create()
1713 dm_error("DC: failed to create dwbc!\n"); in dcn301_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_dwb.h254 struct dwbc base;
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/
H A Ddcn314_resource.c1658 if (pool->base.dwbc[i] != NULL) { in dcn314_dsc_create()
1659 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn314_dsc_create()
1660 pool->base.dwbc[i] = NULL; in dcn314_dsc_create()
1749 pool->dwbc[i] = &dwbc30->base; in dcn314_validate_bandwidth()
2251 dm_error("DC: failed to create dwbc!\n");
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/
H A Ddcn316_resource.c1594 if (pool->base.dwbc[i] != NULL) { in dcn31_dsc_create()
1595 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn31_dsc_create()
1596 pool->base.dwbc[i] = NULL; in dcn31_dsc_create()
1682 pool->dwbc[i] = &dwbc30->base; in dcn316_populate_dml_pipes_from_context()
2149 dm_error("DC: failed to create dwbc!\n");
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/
H A Ddcn21_resource.c748 if (pool->base.dwbc[i] != NULL) { in dcn21_resource_destruct()
749 kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); in dcn21_resource_destruct()
750 pool->base.dwbc[i] = NULL; in dcn21_resource_destruct()
1719 dm_error("DC: failed to create dwbc!\n"); in dcn21_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/
H A Ddcn351_resource.c1640 if (pool->base.dwbc[i] != NULL) { in dcn35_dwbc_create()
1641 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn35_dwbc_create()
1642 pool->base.dwbc[i] = NULL; in dcn35_dwbc_create()
1756 pool->dwbc[i] = &dwbc30->base; in dcn351_validate_bandwidth()
2273 dm_error("DC: failed to create dwbc!\n");
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.c1660 if (pool->base.dwbc[i] != NULL) { in dcn35_dwbc_create()
1661 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn35_dwbc_create()
1662 pool->base.dwbc[i] = NULL; in dcn35_dwbc_create()
1776 pool->dwbc[i] = &dwbc30->base; in dcn35_validate_bandwidth()
2301 dm_error("DC: failed to create dwbc!\n");
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/
H A Ddcn31_resource.c1599 if (pool->base.dwbc[i] != NULL) { in dcn31_dsc_create()
1600 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn31_dsc_create()
1601 pool->base.dwbc[i] = NULL; in dcn31_dsc_create()
1690 pool->dwbc[i] = &dwbc30->base; in dcn31_populate_dml_pipes_from_context()
2333 dm_error("DC: failed to create dwbc!\n");
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/
H A Ddcn315_resource.c1601 if (pool->base.dwbc[i] != NULL) { in dcn31_dsc_create()
1602 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn31_dsc_create()
1603 pool->base.dwbc[i] = NULL; in dcn31_dsc_create()
1692 pool->dwbc[i] = &dwbc30->base; in allow_pixel_rate_crb()
2285 dm_error("DC: failed to create dwbc!\n");
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn36/
H A Ddcn36_resource.c1647 if (pool->base.dwbc[i] != NULL) { in dcn35_dwbc_create()
1648 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn35_dwbc_create()
1649 pool->base.dwbc[i] = NULL; in dcn35_dwbc_create()
1763 pool->dwbc[i] = &dwbc30->base; in dcn35_validate_bandwidth()
2271 dm_error("DC: failed to create dwbc!\n");
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/
H A Ddcn321_resource.c1585 if (pool->base.dwbc[i] != NULL) { in dcn321_dsc_create()
1586 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn321_dsc_create()
1587 pool->base.dwbc[i] = NULL; in dcn321_dsc_create()
1670 pool->dwbc[i] = &dwbc30->base; in dcn321_resource_construct()
2135 dm_error("DC: failed to create dwbc!\n");
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c3311 struct dwbc *dwb; in dcn401_setup_gsl_group_as_lock_sequence()
3347 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn401_setup_gsl_group_as_lock_sequence()
3370 struct dwbc *dwb; in dcn401_disable_plane_sequence()
3376 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn401_disable_plane_sequence()
3403 struct dwbc *dwb; in dcn401_disable_plane_sequence()
3409 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn401_post_unlock_reset_opp_sequence()
3429 struct dwbc *dwb; in dcn401_post_unlock_reset_opp_sequence()
3435 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn401_post_unlock_reset_opp_sequence()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c1299 if (pool->base.dwbc[i] != NULL) { in dcn30_dsc_create()
1300 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn30_dsc_create()
1301 pool->base.dwbc[i] = NULL; in dcn30_dsc_create()
1393 pool->dwbc[i] = &dwbc30->base; in dcn30_calc_max_scaled_time()
2722 dm_error("DC: failed to create dwbc!\n");
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.c1185 if (pool->base.dwbc[i] != NULL) { in dcn20_resource_destruct()
1186 kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); in dcn20_resource_destruct()
1187 pool->base.dwbc[i] = NULL; in dcn20_resource_destruct()
2310 pool->dwbc[i] = &dwbc20->base; in dcn20_dwbc_create()
2767 dm_error("DC: failed to create dwbc!\n"); in dcn20_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.c1611 if (pool->base.dwbc[i] != NULL) { in dcn32_dsc_create()
1612 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn32_dsc_create()
1613 pool->base.dwbc[i] = NULL; in dcn32_dsc_create()
1696 pool->dwbc[i] = &dwbc30->base; in dcn32_enable_phantom_plane()
2647 dm_error("DC: failed to create dwbc!\n");
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_hwseq.c334 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i]; in dcn201_init_hw()