Searched refs:dpll_hw_state (Results 1 – 10 of 10) sorted by relevance
70 const struct intel_dpll_hw_state *dpll_hw_state);87 struct intel_dpll_hw_state *dpll_hw_state);95 const struct intel_dpll_hw_state *dpll_hw_state);114 const struct intel_dpll_hw_state *dpll_hw_state);359 const struct intel_dpll_hw_state *dpll_hw_state, in intel_find_shared_dpll() argument386 if (memcmp(dpll_hw_state, in intel_find_shared_dpll()388 sizeof(*dpll_hw_state)) == 0) { in intel_find_shared_dpll()437 const struct intel_dpll_hw_state *dpll_hw_state) in intel_reference_shared_dpll() argument444 shared_dpll[pll->index].hw_state = *dpll_hw_state; in intel_reference_shared_dpll()526 struct intel_dpll_hw_state *dpll_hw_state) in ibx_pch_dpll_get_hw_state() argument[all …]
418 const struct intel_dpll_hw_state *dpll_hw_state);421 struct intel_dpll_hw_state *dpll_hw_state);432 const struct intel_dpll_hw_state *dpll_hw_state);
377 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in i9xx_pll_refclk()390 struct intel_dpll_hw_state *dpll_hw_state) in i9xx_dpll_get_hw_state() argument393 struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx; in i9xx_dpll_get_hw_state()426 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in i9xx_crtc_clock_get()520 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in vlv_crtc_clock_get()548 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in chv_crtc_clock_get()1080 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in i9xx_compute_dpll()1149 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in i8xx_compute_dpll()1234 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); in mtl_crtc_compute_clock()1352 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in ilk_compute_dpll()[all …]
27 struct intel_dpll_hw_state *dpll_hw_state);
2040 struct intel_cx0pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll; in intel_c10pll_update_pll()2072 crtc_state->dpll_hw_state.cx0pll.c10 = *tables[i]; in intel_c10pll_calc_state()2074 crtc_state->dpll_hw_state.cx0pll.use_c10 = true; in intel_c10pll_calc_state()2113 const struct intel_c10pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll.c10; in intel_c10_pll_program()2179 struct intel_c20pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll.c20; in intel_c20_compute_hdmi_tmds_pll()2324 crtc_state->dpll_hw_state.cx0pll.c20 = *tables[i]; in intel_c20pll_calc_state()2325 crtc_state->dpll_hw_state.cx0pll.use_c10 = false; in intel_c20pll_calc_state()2593 const struct intel_c20pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll.c20; in intel_c20_pll_program()2750 val |= crtc_state->dpll_hw_state.cx0pll.ssc_enabled ? XELPDP_SSC_ENABLE_PLLA : 0; in intel_program_port_clock_ctl()2752 val |= crtc_state->dpll_hw_state.cx0pll.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0; in intel_program_port_clock_ctl()[all …]
536 &crtc_state->dpll_hw_state); in ilk_pch_get_config()539 tmp = crtc_state->dpll_hw_state.i9xx.dpll; in ilk_pch_get_config()
334 intel_dpll_dump_hw_state(i915, &p, &pipe_config->dpll_hw_state); in intel_crtc_state_dump()
1815 crtc_state->dpll_hw_state.mpllb = *tables[i]; in intel_mpllb_calc_state()1827 const struct intel_mpllb_state *pll_state = &crtc_state->dpll_hw_state.mpllb; in intel_mpllb_enable()2006 const struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->dpll_hw_state.mpllb; in intel_mpllb_state_verify()
4247 &crtc_state->dpll_hw_state); in intel_ddi_get_clock()4253 intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll); in mtl_ddi_get_config()4255 if (crtc_state->dpll_hw_state.cx0pll.tbt_mode) in mtl_ddi_get_config()4258 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); in mtl_ddi_get_config()4266 intel_mpllb_readout_hw_state(encoder, &crtc_state->dpll_hw_state.mpllb); in dg2_ddi_get_config()4267 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->dpll_hw_state.mpllb); in dg2_ddi_get_config()4360 &crtc_state->dpll_hw_state); in icl_ddi_tc_get_clock()
1080 struct intel_dpll_hw_state dpll_hw_state; member