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Searched refs:dev_priv (Results 1 – 25 of 214) sorted by relevance

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/linux/drivers/gpu/drm/xe/compat-i915-headers/
H A Di915_drv.h26 #define INTEL_INFO(dev_priv) (&((dev_priv)->info)) argument
27 #define IS_I830(dev_priv) (dev_priv && 0) argument
28 #define IS_I845G(dev_priv) (dev_priv && 0) argument
29 #define IS_I85X(dev_priv) (dev_priv && 0) argument
30 #define IS_I865G(dev_priv) (dev_priv && 0) argument
31 #define IS_I915G(dev_priv) (dev_priv && 0) argument
32 #define IS_I915GM(dev_priv) (dev_priv && 0) argument
33 #define IS_I945G(dev_priv) (dev_priv && 0) argument
34 #define IS_I945GM(dev_priv) (dev_priv && 0) argument
35 #define IS_I965G(dev_priv) (dev_priv && 0) argument
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/linux/drivers/gpu/drm/i915/
H A Di915_irq.c134 struct drm_i915_private *dev_priv = in ivb_parity_work() local
135 container_of(work, typeof(*dev_priv), l3_parity.error_work); in ivb_parity_work()
136 struct intel_gt *gt = to_gt(dev_priv); in ivb_parity_work()
146 mutex_lock(&dev_priv->drm.struct_mutex); in ivb_parity_work()
149 if (drm_WARN_ON(&dev_priv->drm, !dev_priv->l3_parity.which_slice)) in ivb_parity_work()
152 misccpctl = intel_uncore_rmw(&dev_priv->uncore, GEN7_MISCCPCTL, in ivb_parity_work()
154 intel_uncore_posting_read(&dev_priv->uncore, GEN7_MISCCPCTL); in ivb_parity_work()
156 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { in ivb_parity_work()
160 if (drm_WARN_ON_ONCE(&dev_priv->drm, in ivb_parity_work()
161 slice >= NUM_L3_SLICES(dev_priv))) in ivb_parity_work()
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H A Di915_driver.c116 static int i915_workqueues_init(struct drm_i915_private *dev_priv) in i915_workqueues_init() argument
132 dev_priv->wq = alloc_ordered_workqueue("i915", 0); in i915_workqueues_init()
133 if (dev_priv->wq == NULL) in i915_workqueues_init()
136 dev_priv->display.hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0); in i915_workqueues_init()
137 if (dev_priv->display.hotplug.dp_wq == NULL) in i915_workqueues_init()
146 dev_priv->unordered_wq = alloc_workqueue("i915-unordered", 0, 0); in i915_workqueues_init()
147 if (dev_priv->unordered_wq == NULL) in i915_workqueues_init()
153 destroy_workqueue(dev_priv->display.hotplug.dp_wq); in i915_workqueues_init()
155 destroy_workqueue(dev_priv->wq); in i915_workqueues_init()
157 drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n"); in i915_workqueues_init()
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H A Dintel_gvt.c52 static bool is_supported_device(struct drm_i915_private *dev_priv) in is_supported_device() argument
54 if (IS_BROADWELL(dev_priv)) in is_supported_device()
56 if (IS_SKYLAKE(dev_priv)) in is_supported_device()
58 if (IS_KABYLAKE(dev_priv)) in is_supported_device()
60 if (IS_BROXTON(dev_priv)) in is_supported_device()
62 if (IS_COFFEELAKE(dev_priv)) in is_supported_device()
64 if (IS_COMETLAKE(dev_priv)) in is_supported_device()
70 static void free_initial_hw_state(struct drm_i915_private *dev_priv) in free_initial_hw_state() argument
72 struct i915_virtual_gpu *vgpu = &dev_priv->vgpu; in free_initial_hw_state()
84 struct drm_i915_private *dev_priv = iter->i915; in save_mmio() local
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_display_irq.c30 intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe) in intel_handle_vblank() argument
32 struct intel_display *display = &dev_priv->display; in intel_handle_vblank()
44 void ilk_update_display_irq(struct drm_i915_private *dev_priv, in ilk_update_display_irq() argument
49 lockdep_assert_held(&dev_priv->irq_lock); in ilk_update_display_irq()
50 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask); in ilk_update_display_irq()
52 new_val = dev_priv->irq_mask; in ilk_update_display_irq()
56 if (new_val != dev_priv->irq_mask && in ilk_update_display_irq()
57 !drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) { in ilk_update_display_irq()
58 dev_priv->irq_mask = new_val; in ilk_update_display_irq()
59 intel_uncore_write(&dev_priv->uncore, DEIMR, dev_priv->irq_mask); in ilk_update_display_irq()
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H A Dintel_pch_refclk.c14 static void lpt_fdi_reset_mphy(struct drm_i915_private *dev_priv) in lpt_fdi_reset_mphy() argument
16 intel_de_rmw(dev_priv, SOUTH_CHICKEN2, 0, FDI_MPHY_IOSFSB_RESET_CTL); in lpt_fdi_reset_mphy()
18 if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) & in lpt_fdi_reset_mphy()
20 drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n"); in lpt_fdi_reset_mphy()
22 intel_de_rmw(dev_priv, SOUTH_CHICKEN2, FDI_MPHY_IOSFSB_RESET_CTL, 0); in lpt_fdi_reset_mphy()
24 if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) & in lpt_fdi_reset_mphy()
26 drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n"); in lpt_fdi_reset_mphy()
30 static void lpt_fdi_program_mphy(struct drm_i915_private *dev_priv) in lpt_fdi_program_mphy() argument
34 lpt_fdi_reset_mphy(dev_priv); in lpt_fdi_program_mphy()
36 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); in lpt_fdi_program_mphy()
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H A Dintel_fifo_underrun.c61 struct drm_i915_private *dev_priv = to_i915(dev); in ivb_can_enable_err_int() local
65 lockdep_assert_held(&dev_priv->irq_lock); in ivb_can_enable_err_int()
67 for_each_pipe(dev_priv, pipe) { in ivb_can_enable_err_int()
80 struct drm_i915_private *dev_priv = to_i915(dev); in cpt_can_enable_serr_int() local
84 lockdep_assert_held(&dev_priv->irq_lock); in cpt_can_enable_serr_int()
86 for_each_pipe(dev_priv, pipe) { in cpt_can_enable_serr_int()
99 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_check_fifo_underruns() local
100 i915_reg_t reg = PIPESTAT(dev_priv, crtc->pipe); in i9xx_check_fifo_underruns()
103 lockdep_assert_held(&dev_priv->irq_lock); in i9xx_check_fifo_underruns()
105 if ((intel_de_read(dev_priv, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0) in i9xx_check_fifo_underruns()
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H A Dintel_pch_display.c40 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, in assert_pch_dp_disabled() argument
44 struct intel_display *display = &dev_priv->display; in assert_pch_dp_disabled()
48 state = g4x_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe); in assert_pch_dp_disabled()
55 HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, in assert_pch_dp_disabled()
60 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, in assert_pch_hdmi_disabled() argument
64 struct intel_display *display = &dev_priv->display; in assert_pch_hdmi_disabled()
68 state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe); in assert_pch_hdmi_disabled()
75 HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, in assert_pch_hdmi_disabled()
80 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, in assert_pch_ports_disabled() argument
83 struct intel_display *display = &dev_priv->display; in assert_pch_ports_disabled()
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H A Dintel_fdi.c27 static void assert_fdi_tx(struct drm_i915_private *dev_priv, in assert_fdi_tx() argument
30 struct intel_display *display = &dev_priv->display; in assert_fdi_tx()
61 static void assert_fdi_rx(struct drm_i915_private *dev_priv, in assert_fdi_rx() argument
64 struct intel_display *display = &dev_priv->display; in assert_fdi_rx()
127 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_fdi_link_train() local
129 dev_priv->display.funcs.fdi->fdi_link_train(crtc, crtc_state); in intel_fdi_link_train()
194 struct drm_i915_private *dev_priv = to_i915(dev); in ilk_check_fdi_lanes() local
201 drm_dbg_kms(&dev_priv->drm, in ilk_check_fdi_lanes()
205 drm_dbg_kms(&dev_priv->drm, in ilk_check_fdi_lanes()
211 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { in ilk_check_fdi_lanes()
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H A Dintel_combo_phy.c56 icl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy) in icl_get_procmon_ref_values() argument
60 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy)); in icl_get_procmon_ref_values()
78 static void icl_set_procmon_ref_values(struct drm_i915_private *dev_priv, in icl_set_procmon_ref_values() argument
83 procmon = icl_get_procmon_ref_values(dev_priv, phy); in icl_set_procmon_ref_values()
85 intel_de_rmw(dev_priv, ICL_PORT_COMP_DW1(phy), in icl_set_procmon_ref_values()
88 intel_de_write(dev_priv, ICL_PORT_COMP_DW9(phy), procmon->dw9); in icl_set_procmon_ref_values()
89 intel_de_write(dev_priv, ICL_PORT_COMP_DW10(phy), procmon->dw10); in icl_set_procmon_ref_values()
92 static bool check_phy_reg(struct drm_i915_private *dev_priv, in check_phy_reg() argument
96 u32 val = intel_de_read(dev_priv, reg); in check_phy_reg()
99 drm_dbg(&dev_priv->drm, in check_phy_reg()
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H A Dintel_hotplug.c92 enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv, in intel_hpd_pin_default() argument
148 static bool intel_hpd_irq_storm_detect(struct drm_i915_private *dev_priv, in intel_hpd_irq_storm_detect() argument
151 struct intel_hotplug *hpd = &dev_priv->display.hotplug; in intel_hpd_irq_storm_detect()
159 (!long_hpd && !dev_priv->display.hotplug.hpd_short_storm_enabled)) in intel_hpd_irq_storm_detect()
170 drm_dbg_kms(&dev_priv->drm, in intel_hpd_irq_storm_detect()
174 drm_dbg_kms(&dev_priv->drm, in intel_hpd_irq_storm_detect()
224 intel_hpd_irq_storm_switch_to_polling(struct drm_i915_private *dev_priv) in intel_hpd_irq_storm_switch_to_polling() argument
230 lockdep_assert_held(&dev_priv->irq_lock); in intel_hpd_irq_storm_switch_to_polling()
232 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); in intel_hpd_irq_storm_switch_to_polling()
241 dev_priv->display.hotplug.stats[pin].state != HPD_MARK_DISABLED) in intel_hpd_irq_storm_switch_to_polling()
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H A Dintel_lpe_audio.c80 #define HAS_LPE_AUDIO(dev_priv) ((dev_priv)->display.audio.lpe.platdev != NULL) argument
83 lpe_audio_platdev_create(struct drm_i915_private *dev_priv) in lpe_audio_platdev_create() argument
85 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in lpe_audio_platdev_create()
101 rsc[0].start = rsc[0].end = dev_priv->display.audio.lpe.irq; in lpe_audio_platdev_create()
112 pinfo.parent = dev_priv->drm.dev; in lpe_audio_platdev_create()
121 pdata->num_pipes = INTEL_NUM_PIPES(dev_priv); in lpe_audio_platdev_create()
122 pdata->num_ports = IS_CHERRYVIEW(dev_priv) ? 3 : 2; /* B,C,D or B,C */ in lpe_audio_platdev_create()
133 drm_err(&dev_priv->drm, in lpe_audio_platdev_create()
143 static void lpe_audio_platdev_destroy(struct drm_i915_private *dev_priv) in lpe_audio_platdev_destroy() argument
153 platform_device_unregister(dev_priv->display.audio.lpe.platdev); in lpe_audio_platdev_destroy()
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H A Dintel_pipe_crc.c78 static void i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv, in i9xx_pipe_crc_auto_source() argument
88 drm_modeset_lock_all(&dev_priv->drm); in i9xx_pipe_crc_auto_source()
89 for_each_intel_encoder(&dev_priv->drm, encoder) { in i9xx_pipe_crc_auto_source()
116 drm_WARN(&dev_priv->drm, 1, "nonexisting DP port %c\n", in i9xx_pipe_crc_auto_source()
125 drm_modeset_unlock_all(&dev_priv->drm); in i9xx_pipe_crc_auto_source()
128 static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, in vlv_pipe_crc_ctl_reg() argument
136 i9xx_pipe_crc_auto_source(dev_priv, pipe, source); in vlv_pipe_crc_ctl_reg()
151 if (!IS_CHERRYVIEW(dev_priv)) in vlv_pipe_crc_ctl_reg()
173 u32 tmp = intel_de_read(dev_priv, PORT_DFT2_G4X(dev_priv)); in vlv_pipe_crc_ctl_reg()
189 intel_de_write(dev_priv, PORT_DFT2_G4X(dev_priv), tmp); in vlv_pipe_crc_ctl_reg()
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H A Dintel_hotplug_irq.c134 static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) in intel_hpd_init_pins() argument
136 struct intel_hotplug *hpd = &dev_priv->display.hotplug; in intel_hpd_init_pins()
138 if (HAS_GMCH(dev_priv)) { in intel_hpd_init_pins()
139 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || in intel_hpd_init_pins()
140 IS_CHERRYVIEW(dev_priv)) in intel_hpd_init_pins()
147 if (DISPLAY_VER(dev_priv) >= 14) in intel_hpd_init_pins()
149 else if (DISPLAY_VER(dev_priv) >= 11) in intel_hpd_init_pins()
151 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in intel_hpd_init_pins()
153 else if (DISPLAY_VER(dev_priv) == 9) in intel_hpd_init_pins()
155 else if (DISPLAY_VER(dev_priv) >= 8) in intel_hpd_init_pins()
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H A Di9xx_plane.c112 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv, in i9xx_plane_has_fbc() argument
115 if (!HAS_FBC(dev_priv)) in i9xx_plane_has_fbc()
118 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) in i9xx_plane_has_fbc()
120 else if (IS_IVYBRIDGE(dev_priv)) in i9xx_plane_has_fbc()
123 else if (DISPLAY_VER(dev_priv) >= 4) in i9xx_plane_has_fbc()
129 static struct intel_fbc *i9xx_plane_fbc(struct drm_i915_private *dev_priv, in i9xx_plane_fbc() argument
132 if (i9xx_plane_has_fbc(dev_priv, i9xx_plane)) in i9xx_plane_fbc()
133 return dev_priv->display.fbc[INTEL_FBC_A]; in i9xx_plane_fbc()
140 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in i9xx_plane_has_windowing() local
143 if (IS_CHERRYVIEW(dev_priv)) in i9xx_plane_has_windowing()
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H A Di9xx_wm.c106 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable) in chv_set_memory_dvfs() argument
110 vlv_punit_get(dev_priv); in chv_set_memory_dvfs()
112 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); in chv_set_memory_dvfs()
119 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); in chv_set_memory_dvfs()
121 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & in chv_set_memory_dvfs()
123 drm_err(&dev_priv->drm, in chv_set_memory_dvfs()
126 vlv_punit_put(dev_priv); in chv_set_memory_dvfs()
129 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable) in chv_set_memory_pm5() argument
133 vlv_punit_get(dev_priv); in chv_set_memory_pm5()
135 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in chv_set_memory_pm5()
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H A Dintel_vrr_regs.h16 #define TRANS_VRR_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A) argument
30 #define TRANS_VRR_VMAX(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMAX_A) argument
37 #define TRANS_VRR_VMIN(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMIN_A) argument
44 #define TRANS_VRR_VMAXSHIFT(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \ argument
54 #define TRANS_VRR_STATUS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A) argument
74 #define TRANS_VRR_VTOTAL_PREV(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \ argument
85 #define TRANS_VRR_FLIPLINE(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \ argument
93 #define TRANS_VRR_STATUS2(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS2_A) argument
100 #define TRANS_PUSH(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_PUSH_A) argument
105 #define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A) argument
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H A Dintel_dpll.c392 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_dpll_get_hw_state() local
395 if (DISPLAY_VER(dev_priv) >= 4) { in i9xx_dpll_get_hw_state()
399 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) in i9xx_dpll_get_hw_state()
400 tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe]; in i9xx_dpll_get_hw_state()
402 tmp = intel_de_read(dev_priv, in i9xx_dpll_get_hw_state()
403 DPLL_MD(dev_priv, crtc->pipe)); in i9xx_dpll_get_hw_state()
408 hw_state->dpll = intel_de_read(dev_priv, DPLL(dev_priv, crtc->pipe)); in i9xx_dpll_get_hw_state()
410 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { in i9xx_dpll_get_hw_state()
411 hw_state->fp0 = intel_de_read(dev_priv, FP0(crtc->pipe)); in i9xx_dpll_get_hw_state()
412 hw_state->fp1 = intel_de_read(dev_priv, FP1(crtc->pipe)); in i9xx_dpll_get_hw_state()
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/linux/drivers/gpu/drm/vmwgfx/
H A Dvmwgfx_drv.c366 static void vmw_print_sm_type(struct vmw_private *dev_priv) in vmw_print_sm_type() argument
377 drm_info(&dev_priv->drm, "Available shader model: %s.\n", in vmw_print_sm_type()
378 names[dev_priv->sm_type]); in vmw_print_sm_type()
394 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) in vmw_dummy_query_bo_create() argument
415 ret = vmw_bo_create(dev_priv, &bo_params, &vbo); in vmw_dummy_query_bo_create()
434 dev_priv->dummy_query_bo = vbo; in vmw_dummy_query_bo_create()
439 static int vmw_device_init(struct vmw_private *dev_priv) in vmw_device_init() argument
443 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE); in vmw_device_init()
444 dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE); in vmw_device_init()
445 dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES); in vmw_device_init()
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H A Dvmwgfx_irq.c57 struct vmw_private *dev_priv = vmw_priv(dev); in vmw_thread_fn() local
61 dev_priv->irqthread_pending)) { in vmw_thread_fn()
62 vmw_fences_update(dev_priv->fman); in vmw_thread_fn()
63 wake_up_all(&dev_priv->fence_queue); in vmw_thread_fn()
68 dev_priv->irqthread_pending)) { in vmw_thread_fn()
69 vmw_cmdbuf_irqthread(dev_priv->cman); in vmw_thread_fn()
90 struct vmw_private *dev_priv = vmw_priv(dev); in vmw_irq_handler() local
94 status = vmw_irq_status_read(dev_priv); in vmw_irq_handler()
95 masked_status = status & READ_ONCE(dev_priv->irq_mask); in vmw_irq_handler()
98 vmw_irq_status_write(dev_priv, status); in vmw_irq_handler()
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/linux/drivers/gpu/drm/gma500/
H A Dpsb_drv.c103 static void psb_spank(struct drm_psb_private *dev_priv) in psb_spank() argument
124 PSB_WSGX32(dev_priv->gtt.gatt_start, PSB_CR_BIF_TWOD_REQ_BASE); in psb_spank()
129 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); in psb_do_init() local
130 struct psb_gtt *pg = &dev_priv->gtt; in psb_do_init()
143 dev_priv->gatt_free_offset = pg->mmu_gatt_start + in psb_do_init()
146 spin_lock_init(&dev_priv->irqmask_lock); in psb_do_init()
157 psb_spank(dev_priv); in psb_do_init()
168 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); in psb_driver_unload() local
177 if (dev_priv->ops->chip_teardown) in psb_driver_unload()
178 dev_priv->ops->chip_teardown(dev); in psb_driver_unload()
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H A Dintel_bios.c46 parse_edp(struct drm_psb_private *dev_priv, struct bdb_header *bdb) in parse_edp() argument
55 dev_priv->edp.bpp = 18; in parse_edp()
57 if (dev_priv->edp.support) { in parse_edp()
59 dev_priv->edp.bpp); in parse_edp()
64 panel_type = dev_priv->panel_type; in parse_edp()
67 dev_priv->edp.bpp = 18; in parse_edp()
70 dev_priv->edp.bpp = 24; in parse_edp()
73 dev_priv->edp.bpp = 30; in parse_edp()
81 dev_priv->edp.pps = *edp_pps; in parse_edp()
84 dev_priv->edp.pps.t1_t3, dev_priv->edp.pps.t8, in parse_edp()
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H A Dpsb_irq.c46 void gma_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask) in gma_enable_pipestat() argument
48 if ((dev_priv->pipestat[pipe] & mask) != mask) { in gma_enable_pipestat()
50 dev_priv->pipestat[pipe] |= mask; in gma_enable_pipestat()
52 if (gma_power_begin(&dev_priv->dev, false)) { in gma_enable_pipestat()
57 gma_power_end(&dev_priv->dev); in gma_enable_pipestat()
62 void gma_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask) in gma_disable_pipestat() argument
64 if ((dev_priv->pipestat[pipe] & mask) != 0) { in gma_disable_pipestat()
66 dev_priv->pipestat[pipe] &= ~mask; in gma_disable_pipestat()
67 if (gma_power_begin(&dev_priv->dev, false)) { in gma_disable_pipestat()
72 gma_power_end(&dev_priv->dev); in gma_disable_pipestat()
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H A Dbacklight.c22 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); in gma_backlight_enable() local
24 dev_priv->backlight_enabled = true; in gma_backlight_enable()
25 dev_priv->ops->backlight_set(dev, dev_priv->backlight_level); in gma_backlight_enable()
30 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); in gma_backlight_disable() local
32 dev_priv->backlight_enabled = false; in gma_backlight_disable()
33 dev_priv->ops->backlight_set(dev, 0); in gma_backlight_disable()
38 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); in gma_backlight_set() local
40 dev_priv->backlight_level = v; in gma_backlight_set()
41 if (dev_priv->backlight_enabled) in gma_backlight_set()
42 dev_priv->ops->backlight_set(dev, v); in gma_backlight_set()
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/linux/drivers/gpu/drm/i915/soc/
H A Dintel_pch.h66 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type) argument
67 #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id) argument
68 #define HAS_PCH_DG2(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG2) argument
69 #define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP) argument
70 #define HAS_PCH_DG1(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG1) argument
71 #define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP) argument
72 #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP) argument
73 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP) argument
74 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT) argument
75 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT) argument
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