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Searched refs:cs_mask (Results 1 – 25 of 35) sorted by relevance

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/linux/sound/pci/ice1712/
H A Dak4xxx.c56 if (priv->cs_mask == priv->cs_addr) { in snd_ice1712_akm4xxx_write()
58 tmp |= priv->cs_mask; /* start without chip select */ in snd_ice1712_akm4xxx_write()
60 tmp &= ~priv->cs_mask; /* chip select low */ in snd_ice1712_akm4xxx_write()
66 tmp &= ~priv->cs_mask; in snd_ice1712_akm4xxx_write()
93 if (priv->cs_mask == priv->cs_addr) { in snd_ice1712_akm4xxx_write()
96 tmp &= ~priv->cs_mask; in snd_ice1712_akm4xxx_write()
100 tmp |= priv->cs_mask; /* chip select high to trigger */ in snd_ice1712_akm4xxx_write()
102 tmp &= ~priv->cs_mask; in snd_ice1712_akm4xxx_write()
H A Ddelta.c246 priv->cs_mask = in delta_ak4524_lock()
260 priv->cs_mask = ICE1712_DELTA_1010LT_CS; in delta1010lt_ak4524_lock()
273 priv->cs_mask = in delta66e_ak4524_lock()
287 priv->cs_mask = in vx442_ak4524_lock()
439 .cs_mask = ICE1712_DELTA_AP_CS_CODEC,
460 .cs_mask = ICE1712_DELTA_AP_CS_CODEC,
482 .cs_mask = 0,
504 .cs_mask = 0,
527 .cs_mask = 0,
549 .cs_mask = 0,
H A Drevo.c238 .cs_mask = VT1724_REVO_CS0 | VT1724_REVO_CS1 | VT1724_REVO_CS2,
260 .cs_mask = VT1724_REVO_CS0 | VT1724_REVO_CS1 | VT1724_REVO_CS2,
281 .cs_mask = VT1724_REVO_CS0 | VT1724_REVO_CS1,
299 .cs_mask = VT1724_REVO_CS0 | VT1724_REVO_CS1,
349 .cs_mask = VT1724_REVO_CS0 | VT1724_REVO_CS3,
H A Dews.c205 tmp = priv->cs_mask = priv->cs_addr = (1 << chip) & ICE1712_6FIRE_AK4524_CS_MASK; in dmx6fire_ak4524_lock()
343 .cs_mask = 0,
364 .cs_mask = ICE1712_EWX2496_AK4524_CS,
385 .cs_mask = 0,
H A Dhoontech.c288 .cs_mask = ICE1712_STDSP24_AK4524_CS, in snd_ice1712_value_init()
H A Dice1712.h256 unsigned int cs_mask; /* bit mask for select/deselect address */ member
H A Dphase.c102 .cs_mask = 1 << 10,
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_clock_source.c54 clk_src->cs_shift->field_name, clk_src->cs_mask->field_name
830 if (clk_src->cs_mask->PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE) in dce112_program_pixel_clk_resync()
997 if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL) in dcn31_program_pix_clk()
1015 if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL) in dcn31_program_pix_clk()
1424 if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)
1744 const struct dce110_clk_src_mask *cs_mask) in dce110_clk_src_construct()
1756 clk_src->cs_mask = cs_mask; in dce110_clk_src_construct()
1769 clk_src->cs_mask->PLL_POST_DIV_PIXCLK; in dce112_clk_src_construct()
1771 calc_pll_cs_init_data.max_pll_ref_divider = clk_src->cs_mask in dce112_clk_src_construct()
1673 dce110_clk_src_construct(struct dce110_clk_src * clk_src,struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,const struct dce110_clk_src_shift * cs_shift,const struct dce110_clk_src_mask * cs_mask) dce110_clk_src_construct() argument
1773 dce112_clk_src_construct(struct dce110_clk_src * clk_src,struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,const struct dce110_clk_src_shift * cs_shift,const struct dce110_clk_src_mask * cs_mask) dce112_clk_src_construct() argument
1801 dcn20_clk_src_construct(struct dce110_clk_src * clk_src,struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,const struct dce110_clk_src_shift * cs_shift,const struct dce110_clk_src_mask * cs_mask) dcn20_clk_src_construct() argument
1817 dcn3_clk_src_construct(struct dce110_clk_src * clk_src,struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,const struct dce110_clk_src_shift * cs_shift,const struct dce110_clk_src_mask * cs_mask) dcn3_clk_src_construct() argument
1833 dcn31_clk_src_construct(struct dce110_clk_src * clk_src,struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,const struct dce110_clk_src_shift * cs_shift,const struct dce110_clk_src_mask * cs_mask) dcn31_clk_src_construct() argument
1849 dcn401_clk_src_construct(struct dce110_clk_src * clk_src,struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,const struct dce110_clk_src_shift * cs_shift,const struct dce110_clk_src_mask * cs_mask) dcn401_clk_src_construct() argument
1864 dcn301_clk_src_construct(struct dce110_clk_src * clk_src,struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,const struct dce110_clk_src_shift * cs_shift,const struct dce110_clk_src_mask * cs_mask) dcn301_clk_src_construct() argument
[all...]
/linux/drivers/usb/host/
H A Dehci-sched.c202 ps->usecs, ps->c_usecs, ps->cs_mask); in bandwidth_dbg()
238 if (qh->ps.cs_mask & m) in reserve_release_intr_bandwidth()
890 qh->ps.cs_mask = qh->ps.period ? in qh_schedule()
896 hw->hw_info2 |= cpu_to_hc32(ehci, qh->ps.cs_mask); in qh_schedule()
1092 stream->ps.cs_mask = 1; in iso_stream_init()
1096 stream->ps.cs_mask |= tmp << (8 + 2); in iso_stream_init()
1098 stream->ps.cs_mask = smask_out[hs_transfers - 1]; in iso_stream_init()
1329 s_mask = stream->ps.cs_mask; in reserve_release_iso_bandwidth()
1394 mask = stream->ps.cs_mask << (uframe & 7); in sitd_slot_ok()
1397 if (((stream->ps.cs_mask & 0xff) << (uframe & 7)) >= (1 << 7)) in sitd_slot_ok()
[all …]
/linux/arch/mips/include/asm/octeon/
H A Dcvmx-lmcx-defs.h1625 uint64_t cs_mask:8; member
1627 uint64_t cs_mask:8;
1639 uint64_t cs_mask:8; member
1641 uint64_t cs_mask:8;
1986 uint64_t cs_mask:8; member
1988 uint64_t cs_mask:8;
2003 uint64_t cs_mask:8; member
2005 uint64_t cs_mask:8;
/linux/drivers/gpu/drm/amd/display/dc/resource/dce100/
H A Ddce100_resource.c343 static const struct dce110_clk_src_mask cs_mask = { variable
766 regs, &cs_shift, &cs_mask)) { in dce100_clock_source_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dce120/
H A Ddce120_resource.c422 static const struct dce110_clk_src_mask cs_mask = { variable
550 regs, &cs_shift, &cs_mask)) { in dce120_clock_source_create()
/linux/kernel/cgroup/
H A Dcpuset.c4096 const struct cpumask *cs_mask; in cpuset_cpus_allowed_fallback()
4100 cs_mask = task_cs(tsk)->cpus_allowed; in cpuset_cpus_allowed_fallback()
4101 if (is_in_v2_mode() && cpumask_subset(cs_mask, possible_mask)) { in cpuset_cpus_allowed_fallback()
4102 set_cpus_allowed_force(tsk, cs_mask); in cpuset_cpus_allowed_fallback()
4093 const struct cpumask *cs_mask; cpuset_cpus_allowed_fallback() local
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/
H A Ddcn201_resource.c320 static const struct dce110_clk_src_mask cs_mask = { variable
859 regs, &cs_shift, &cs_mask)) { in dcn201_clock_source_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dce80/
H A Ddce80_resource.c369 static const struct dce110_clk_src_mask cs_mask = { variable
801 regs, &cs_shift, &cs_mask)) { in dce80_clock_source_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dce60/
H A Ddce60_resource.c369 static const struct dce110_clk_src_mask cs_mask = { variable
794 regs, &cs_shift, &cs_mask)) { in dce60_clock_source_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dce112/
H A Ddce112_resource.c384 static const struct dce110_clk_src_mask cs_mask = { variable
766 regs, &cs_shift, &cs_mask)) { in dce112_clock_source_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/
H A Ddcn314_resource.c243 static const struct dce110_clk_src_mask cs_mask = {
1816 regs, &cs_shift, &cs_mask)) {
1962 regs, &cs_shift, &cs_mask)) { in dcn314_resource_construct()
241 static const struct dce110_clk_src_mask cs_mask = { global() variable
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/
H A Ddcn31_resource.c234 static const struct dce110_clk_src_mask cs_mask = {
1757 regs, &cs_shift, &cs_mask)) {
2034 regs, &cs_shift, &cs_mask)) { in dcn31_resource_construct()
232 static const struct dce110_clk_src_mask cs_mask = { global() variable
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/
H A Ddcn303_resource.c541 static const struct dce110_clk_src_mask cs_mask = {
553 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) { in dcn303_dpp_create()
453 static const struct dce110_clk_src_mask cs_mask = { global() variable
/linux/drivers/gpu/drm/amd/display/dc/resource/dce110/
H A Ddce110_resource.c376 static const struct dce110_clk_src_mask cs_mask = { variable
790 regs, &cs_shift, &cs_mask)) { in dce110_clock_source_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/
H A Ddcn302_resource.c557 static const struct dce110_clk_src_mask cs_mask = {
569 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) { in dcn302_dpp_create()
469 static const struct dce110_clk_src_mask cs_mask = { global() variable
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn10/
H A Ddcn10_resource.c513 static const struct dce110_clk_src_mask cs_mask = { variable
821 regs, &cs_shift, &cs_mask)) { in dcn10_clock_source_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/
H A Ddcn21_resource.c165 static const struct dce110_clk_src_mask cs_mask = { variable
1002 regs, &cs_shift, &cs_mask)) { in dcn21_clock_source_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn301/
H A Ddcn301_resource.c215 static const struct dce110_clk_src_mask cs_mask = { variable
1299 regs, &cs_shift, &cs_mask)) { in dcn301_clock_source_create()

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