| /linux/drivers/accel/rocket/ |
| H A D | rocket_drv.c | 89 rocket_priv->domain = rocket_iommu_domain_create(rdev->cores[0].dev); in rocket_open()
177 rdev->cores[core].rdev = rdev; in rocket_probe()
178 rdev->cores[core].dev = &pdev->dev; in rocket_probe()
179 rdev->cores[core].index = core; in rocket_probe()
183 ret = rocket_core_init(&rdev->cores[core]); in rocket_probe()
206 rocket_core_fini(&rdev->cores[core]); in rocket_remove()
227 if (dev == rdev->cores[core].dev) in find_core_for_dev()
243 err = clk_bulk_prepare_enable(ARRAY_SIZE(rdev->cores[core].clks), rdev->cores[core].clks); in rocket_device_runtime_resume()
260 if (!rocket_job_is_idle(&rdev->cores[core])) in rocket_device_runtime_suspend()
263 clk_bulk_disable_unprepare(ARRAY_SIZE(rdev->cores[core].clks), rdev->cores[core].clks); in rocket_device_runtime_suspend()
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| /linux/Documentation/networking/device_drivers/can/freescale/ |
| H A D | flexcan.rst | 13 For most flexcan IP cores the driver supports 2 RX modes:
18 The older flexcan cores (integrated into the i.MX25, i.MX28, i.MX35
28 cores come up in a mode where RTR reception is possible.
39 On some IP cores the controller cannot receive RTR frames in the
45 Waive ability to receive RTR frames. (not supported on all IP cores)
48 some IP cores RTR frames cannot be received anymore.
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| /linux/Documentation/devicetree/bindings/media/xilinx/ |
| H A D | video.txt | 1 DT bindings for Xilinx video IP cores
4 Xilinx video IP cores process video streams by acting as video sinks and/or
10 cores are represented as defined in ../video-interfaces.txt.
18 The following properties are common to all Xilinx video IP cores.
21 AXI bus between video IP cores, using its VF code as defined in "AXI4-Stream
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| H A D | xlnx,video.txt | 8 video IP cores. Each video IP core is represented as documented in video.txt
11 mappings between DMAs and the video IP cores.
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| /linux/Documentation/devicetree/bindings/bus/ |
| H A D | brcm,bus-axi.txt | 9 The cores on the AXI bus are automatically detected by bcma with the
12 BCM47xx/BCM53xx ARM SoCs. To assign IRQ numbers to the cores, provide
17 The top-level axi bus may contain children representing attached cores
19 detected (e.g. IRQ numbers). Also some of the cores may be responsible
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| /linux/Documentation/arch/x86/ |
| H A D | amd-hfi.rst | 16 architectural class and CPUs are comprised of cores of various efficiency and
17 power capabilities: performance-oriented *classic cores* and power-efficient
18 *dense cores*. As such, power management strategies must be designed to
26 sending background threads to the dense cores while sending high priority
27 threads to the classic cores. From a performance perspective, sending
28 background threads to dense cores can free up power headroom and allow the
29 classic cores to optimally service demanding threads. Furthermore, the area
30 optimized nature of the dense cores allows for an increasing number of
31 physical cores. This improved core density will have positive multithreaded
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| /linux/arch/riscv/ |
| H A D | Kconfig.errata | 9 here if your platform uses Andes CPU cores.
20 non-standard handling on non-coherent operations on Andes cores.
30 here if your platform uses MIPS CPU cores.
53 here if your platform uses SiFive CPU cores.
105 here if your platform uses T-HEAD CPU cores.
138 The T-Head C9xx cores implement a PMU overflow extension very
151 The T-Head C9xx cores have a vulnerability in the xtheadvector
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| /linux/drivers/bcma/ |
| H A D | main.c | 92 list_for_each_entry(core, &bus->cores, list) { in bcma_find_core_unit()
272 INIT_LIST_HEAD(&bus->cores); in bcma_init_bus()
296 list_for_each_entry(core, &bus->cores, list) { in bcma_register_devices()
372 list_for_each_entry_safe(core, tmp, &bus->cores, list) { in bcma_unregister_cores()
382 list_for_each_entry_safe(core, tmp, &bus->cores, list) { in bcma_unregister_cores()
418 list_for_each_entry(core, &bus->cores, list) { in bcma_bus_register()
543 list_for_each_entry(core, &bus->cores, list) { in bcma_bus_suspend()
564 list_for_each_entry(core, &bus->cores, list) { in bcma_bus_resume()
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| H A D | driver_mips.c | 122 list_for_each_entry(core, &bus->cores, list) { in bcma_core_mips_set_irq()
172 list_for_each_entry(core, &bus->cores, list) { in bcma_core_mips_dump_irq()
343 list_for_each_entry(core, &bus->cores, list) { in bcma_core_mips_init()
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| /linux/sound/soc/sof/ |
| H A D | ipc4-mtrace.c | 31 * The first page contains descriptors for the remaining 15 cores
113 struct sof_mtrace_core_data cores[]; member
397 debugfs_create_file(dfs_name, 0444, dfs_root, &priv->cores[i], in mtrace_debugfs_create()
477 struct sof_mtrace_core_data *core_data = &priv->cores[i]; in ipc4_mtrace_disable()
488 * and map them to cores. in ipc4_mtrace_disable()
513 core_data = &priv->cores[core]; in sof_mtrace_find_core_slots()
550 priv = devm_kzalloc(sdev->dev, struct_size(priv, cores, sdev->num_cores), in ipc4_mtrace_init()
564 struct sof_mtrace_core_data *core_data = &priv->cores[i]; in ipc4_mtrace_init()
619 core_data = &priv->cores[core]; in sof_ipc4_mtrace_update_pos()
645 * cores an in sof_ipc4_mtrace_update_pos()
[all...] |
| /linux/drivers/net/ethernet/airoha/ |
| H A D | airoha_npu.c | 176 spin_lock_bh(&npu->cores[core].lock); in airoha_npu_send_msg()
192 spin_unlock_bh(&npu->cores[core].lock); in airoha_npu_send_msg()
308 c = core - &npu->cores[0]; in airoha_npu_wdt_work()
320 int c = core - &npu->cores[0]; in airoha_npu_wdt_handler()
742 for (i = 0; i < ARRAY_SIZE(npu->cores); i++) { in airoha_npu_probe()
743 struct airoha_npu_core *core = &npu->cores[i]; in airoha_npu_probe()
762 irq = platform_get_irq(pdev, i + ARRAY_SIZE(npu->cores) + 1); in airoha_npu_probe()
809 for (i = 0; i < ARRAY_SIZE(npu->cores); i++) in airoha_npu_remove()
810 cancel_work_sync(&npu->cores[i].wdt_work); in airoha_npu_remove()
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| /linux/arch/arm/boot/dts/arm/ |
| H A D | vexpress-v2p-ca15-tc1.dts | 199 regulator-cores {
210 amp-cores {
211 /* Total current for the two cores */
224 power-cores {
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| H A D | vexpress-v2p-ca15_a7.dts | 360 /* Total current for the two A15 cores */
367 /* Total current for the three A7 cores */
381 /* Total power for the two A15 cores */
388 /* Total power for the three A7 cores */
395 /* Total energy for the two A15 cores */
402 /* Total energy for the three A7 cores */
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| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-bus-bcma | 14 There are a few types of BCMA cores, they can be identified by
22 BCMA cores of the same type can still slightly differ depending
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| /linux/Documentation/admin-guide/device-mapper/ |
| H A D | unstriped.rst | 85 Intel NVMe drives contain two cores on the physical device.
88 in a 256k stripe across the two cores::
100 are striped across the two cores. When we unstripe this hardware RAID 0
113 unstriped on top of Intel NVMe device that has 2 cores
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| /linux/Documentation/admin-guide/perf/ |
| H A D | arm_dsu_pmu.rst | 5 ARM DynamIQ Shared Unit integrates one or more cores with an L3 memory system,
11 cores connected to the same DSU. Like most of the other uncore PMUs, DSU
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| /linux/arch/arm/boot/dts/samsung/ |
| H A D | exynos5422-odroidxu3-lite.dts | 39 * than Odroid XU3/XU4 boards: 1.8 GHz for A15 cores & 1.3 GHz for A7 cores.
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| /linux/drivers/cpuidle/ |
| H A D | Kconfig.arm | 56 define different C-states for little and big cores through the
131 CPU and L2 cores. It interface with various system drivers to put
132 the cores in low power modes.
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| /linux/drivers/net/can/esd/ |
| H A D | esdacc.c | 144 void acc_init_bm_ptr(struct acc_ov *ov, struct acc_core *cores, const void *mem) in acc_init_bm_ptr() argument
166 struct acc_core *core = &cores[u]; in acc_init_bm_ptr()
716 irqreturn_t acc_card_interrupt(struct acc_ov *ov, struct acc_core *cores) in acc_card_interrupt() argument
733 struct acc_core *core = &cores[i]; in acc_card_interrupt()
757 struct acc_core *core = &cores[i]; in acc_card_interrupt()
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| /linux/tools/perf/tests/ |
| H A D | make | 32 …cores := $(shell (getconf _NPROCESSORS_ONLN || grep -E -c '^processor|^CPU[0-9]' /proc/cpuinfo) 2>…
33 ifeq ($(cores),0)
34 cores := 1
37 cores=$(JOBS)
39 PARALLEL_OPT="-j$(cores)"
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| /linux/Documentation/devicetree/bindings/arc/ |
| H A D | axs103.txt | 5 HS38x cores.
|
| /linux/Documentation/admin-guide/hw-vuln/ |
| H A D | l1d_flush.rst | 63 cores or by disabling SMT. See the relevant chapter in the L1TF mitigation
67 affinity is limited to cores running in non-SMT mode. If a task which
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| /linux/drivers/irqchip/ |
| H A D | irq-loongson-eiointc.c | 202 int i, bit, cores, index, node; in eiointc_router_init() local
222 cores = CORES_PER_EIO_NODE; in eiointc_router_init()
224 cores = CORES_PER_VEIO_NODE; in eiointc_router_init()
226 if ((cpu_logical_map(cpu) % cores) == 0) { in eiointc_router_init()
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| /linux/arch/arm/boot/dts/intel/socfpga/ |
| H A D | socfpga_arria5.dtsi | 7 /* First 4KB has trampoline code for secondary cores. */
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| H A D | socfpga_cyclone5.dtsi | 7 /* First 4KB has trampoline code for secondary cores. */
|