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Searched refs:base_reg (Results 1 – 18 of 18) sorted by relevance

/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_clk_pll.c105 uint32_t base_reg; member
220 .base_reg = PLLM_BASE,
231 .base_reg = PLLX_BASE,
244 .base_reg = PLLC_BASE,
257 .base_reg = PLLC2_BASE,
268 .base_reg = PLLC3_BASE,
279 .base_reg = PLLC4_BASE,
292 .base_reg = PLLP_BASE,
302 .base_reg = PLLA_BASE,
312 .base_reg = PLLU_BASE,
[all …]
H A Dtegra124_clk_super.c46 uint32_t base_reg; member
60 .base_reg = r, \
97 uint32_t base_reg; member
159 RD4(sc, sc->base_reg, &reg); in super_mux_init()
197 RD4(sc, sc->base_reg, &reg); in super_mux_set_mux()
210 WR4(sc, sc->base_reg, reg); in super_mux_set_mux()
211 RD4(sc, sc->base_reg, &dummy); in super_mux_set_mux()
214 WR4(sc, sc->base_reg, reg); in super_mux_set_mux()
215 RD4(sc, sc->base_reg, &dummy); in super_mux_set_mux()
221 WR4(sc, sc->base_reg, reg); in super_mux_set_mux()
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H A Dtegra124_clk_per.c61 uint32_t base_reg; member
397 .base_reg = r, \
522 uint32_t base_reg; member
554 MD4(sc, sc->base_reg, PERLCK_ENA_MASK, PERLCK_ENA_MASK); in periph_init()
556 RD4(sc, sc->base_reg, &reg); in periph_init()
596 RD4(sc, sc->base_reg, &reg); in periph_set_mux()
611 WR4(sc, sc->base_reg, reg); in periph_set_mux()
627 RD4(sc, sc->base_reg, &reg); in periph_recalc()
661 MD4(sc, sc->base_reg, sc->div_mask, in periph_set_freq()
683 sc->base_reg = clkdef->base_reg; in periph_register()
[all …]
/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_clk_pll.c132 uint32_t base_reg; member
274 .base_reg = PLLM_BASE,
286 .base_reg = PLLMB_BASE,
298 .base_reg = PLLX_BASE,
310 .base_reg = PLLC_BASE,
321 .base_reg = PLLC2_BASE,
332 .base_reg = PLLC3_BASE,
344 .base_reg = PLLC4_BASE,
361 .base_reg = PLLP_BASE,
372 .base_reg = PLLA_BASE,
[all …]
H A Dtegra210_clk_super.c44 uint32_t base_reg; member
56 .base_reg = r, \
90 uint32_t base_reg; member
149 RD4(sc, sc->base_reg, &reg); in super_mux_init()
177 RD4(sc, sc->base_reg, &reg); in super_mux_set_mux()
190 WR4(sc, sc->base_reg, reg); in super_mux_set_mux()
191 RD4(sc, sc->base_reg, &dummy); in super_mux_set_mux()
210 sc->base_reg = clkdef->base_reg; in super_mux_register()
H A Dtegra210_clk_per.c56 uint32_t base_reg; member
506 .base_reg = r, \
635 uint32_t base_reg; member
667 MD4(sc, sc->base_reg, PERLCK_ENA_MASK, PERLCK_ENA_MASK); in periph_init()
669 RD4(sc, sc->base_reg, &reg); in periph_init()
710 RD4(sc, sc->base_reg, &reg); in periph_set_mux()
725 WR4(sc, sc->base_reg, reg); in periph_set_mux()
741 RD4(sc, sc->base_reg, &reg); in periph_recalc()
775 MD4(sc, sc->base_reg, sc->div_mask, in periph_set_freq()
797 sc->base_reg = clkdef->base_reg; in periph_register()
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/freebsd/contrib/llvm-project/lldb/include/lldb/Core/
H A DEmulateInstruction.h200 RegisterInfo base_reg; // base register number member
206 RegisterInfo base_reg; // base register for address calculation member
211 RegisterInfo base_reg; // base register for address calculation member
250 void SetRegisterPlusOffset(RegisterInfo base_reg, int64_t signed_offset) { in SetRegisterPlusOffset()
252 info.RegisterPlusOffset.reg = base_reg; in SetRegisterPlusOffset()
256 void SetRegisterPlusIndirectOffset(RegisterInfo base_reg, in SetRegisterPlusIndirectOffset()
259 info.RegisterPlusIndirectOffset.base_reg = base_reg; in SetRegisterPlusIndirectOffset()
264 RegisterInfo base_reg, in SetRegisterToRegisterPlusOffset()
268 info.RegisterToRegisterPlusOffset.base_reg = base_reg; in SetRegisterToRegisterPlusOffset()
272 void SetRegisterToRegisterPlusIndirectOffset(RegisterInfo base_reg, in SetRegisterToRegisterPlusIndirectOffset()
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/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp4518 std::optional<RegisterInfo> base_reg = in EmulateLDRRtRnImm() local
4527 ctx.SetRegisterPlusOffset(*base_reg, (int32_t)(offset_addr - base)); in EmulateLDRRtRnImm()
4530 ctx.SetRegisterPlusOffset(*base_reg, (int32_t)(offset_addr - base)); in EmulateLDRRtRnImm()
4541 context.SetRegisterPlusOffset(*base_reg, (int32_t)(offset_addr - base)); in EmulateLDRRtRnImm()
4654 std::optional<RegisterInfo> base_reg = in EmulateSTM() local
4678 context.SetRegisterToRegisterPlusOffset(*data_reg, *base_reg, offset); in EmulateSTM()
4776 std::optional<RegisterInfo> base_reg = in EmulateSTMDA() local
4799 context.SetRegisterToRegisterPlusOffset(*data_reg, *base_reg, in EmulateSTMDA()
4924 std::optional<RegisterInfo> base_reg = in EmulateSTMDB() local
4948 context.SetRegisterToRegisterPlusOffset(*data_reg, *base_reg, in EmulateSTMDB()
[all …]
/freebsd/sys/x86/iommu/
H A Damd_event.c266 uint64_t base_reg; in amdiommu_init_event() local
287 base_reg = pmap_kextract((vm_offset_t)unit->event_log) | in amdiommu_init_event()
296 amdiommu_write8(unit, AMDIOMMU_EVNTLOG_BASE, base_reg); in amdiommu_init_event()
/freebsd/contrib/llvm-project/lldb/source/Plugins/SymbolFile/NativePDB/
H A DPdbUtil.cpp772 RegisterId base_reg = RegisterId::NONE; in GetVariableLocationInfo() local
798 if (base_reg == RegisterId::NONE) { in GetVariableLocationInfo()
807 base_reg = in GetVariableLocationInfo()
809 if (base_reg == RegisterId::NONE) in GetVariableLocationInfo()
813 if (base_reg == RegisterId::VFRAME) { in GetVariableLocationInfo()
822 expr = MakeRegRelLocationExpression(base_reg, loc.Hdr.Offset, module); in GetVariableLocationInfo()
/freebsd/contrib/llvm-project/lldb/source/Core/
H A DEmulateInstruction.cpp462 info.RegisterPlusIndirectOffset.base_reg.name, in Dump()
468 info.RegisterToRegisterPlusOffset.base_reg.name, in Dump()
475 info.RegisterToRegisterPlusIndirectOffset.base_reg.name, in Dump()
/freebsd/sys/dev/ntb/ntb_hw/
H A Dntb_hw_intel.c2177 uint32_t base_reg, lmt_reg; in xeon_set_sbar_base_and_limit() local
2179 bar_get_xlat_params(ntb, idx, &base_reg, NULL, &lmt_reg); in xeon_set_sbar_base_and_limit()
2188 intel_ntb_reg_write(4, base_reg, bar_addr); in xeon_set_sbar_base_and_limit()
2189 reg_val = intel_ntb_reg_read(4, base_reg); in xeon_set_sbar_base_and_limit()
2196 intel_ntb_reg_write(8, base_reg, bar_addr); in xeon_set_sbar_base_and_limit()
2197 reg_val = intel_ntb_reg_read(8, base_reg); in xeon_set_sbar_base_and_limit()
3601 uint32_t base_reg, xlat_reg, limit_reg; in intel_ntb_mw_set_trans() local
3624 bar_get_xlat_params(ntb, bar_num, &base_reg, &xlat_reg, &limit_reg); in intel_ntb_mw_set_trans()
3631 base = intel_ntb_reg_read(8, base_reg) & BAR_HIGH_MASK; in intel_ntb_mw_set_trans()
3664 base = intel_ntb_reg_read(4, base_reg) & BAR_HIGH_MASK; in intel_ntb_mw_set_trans()
/freebsd/sys/dev/bxe/
H A Decore_init_ops.h904 uint32_t base_reg, uint32_t reg) in ecore_qm_set_ptr_table() argument
909 REG_WR(sc, base_reg + i*4, in ecore_qm_set_ptr_table()
/freebsd/sys/contrib/dev/iwlwifi/fw/
H A Dfile.h671 __le32 base_reg; member
/freebsd/sys/contrib/dev/iwlwifi/pcie/gen1_2/
H A Dtrans.c887 iwl_write_prph(trans, le32_to_cpu(dest->base_reg), in iwl_pcie_apply_destination()
3410 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); in iwl_trans_pcie_dump_pointers()
3502 cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg); in iwl_trans_get_fw_monitor_len()
3514 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); in iwl_trans_get_fw_monitor_len()
/freebsd/sys/contrib/dev/iwlwifi/
H A Diwl-drv.c1753 dest_tlv->base_reg = pieces->dbg_dest_tlv->cfg_reg; in iwl_req_fw_callback()
/freebsd/sys/dev/iwx/
H A Dif_iwx.c933 uint32_t base_reg, end_reg; in iwx_apply_debug_destination()
938 base_reg = le32toh(dest_v1->base_reg); in iwx_apply_debug_destination()
999 iwx_write_prph(sc, le32toh(base_reg), in iwx_apply_debug_destination()
H A Dif_iwxreg.h2515 uint32_t base_reg; member