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Searched refs:assigned (Results 1 – 25 of 699) sorted by relevance

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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-nominal.dtsi7 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
13 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
19 assigned-clock-rates = <0>, <0>,
28 assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>;
29 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
30 assigned-clock-rates = <800000000>;
34 assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>,
36 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
38 assigned-clock-rates = <800000000>, <800000000>;
42 assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>,
[all …]
H A Dimx8mm-overdrive.dtsi4 assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>,
6 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
7 assigned-clock-rates = <0>, <1000000000>;
11 assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>,
13 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
14 assigned-clock-rates = <0>, <1000000000>;
18 assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>,
22 assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>,
25 assigned-clock-rates = <750000000>,
H A Dimx8-ss-dma.dtsi34 assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>;
35 assigned-clock-rates = <60000000>;
52 assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>;
53 assigned-clock-rates = <60000000>;
70 assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>;
71 assigned-clock-rates = <60000000>;
88 assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>;
89 assigned-clock-rates = <60000000>;
102 assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>;
103 assigned-clock-rates = <80000000>;
[all …]
H A Dimx8mq-mnt-reform2.dts105 assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
106 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>;
107 assigned-clock-rates = <25000000>;
175 assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
176 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>;
177 /delete-property/assigned-clock-rates;
235 assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
236 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
237 assigned-clock-rates = <25000000>;
274 assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
[all …]
H A Dimx8mm-beacon-baseboard.dtsi200 assigned-clocks = <&clk IMX8MM_CLK_CLKO1>;
201 assigned-clock-parents = <&clk IMX8MM_CLK_24M>;
202 assigned-clock-rates = <24000000>;
273 assigned-clocks = <&clk IMX8MM_CLK_PDM>;
274 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
275 assigned-clock-rates = <49152000>;
307 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
309 assigned-clock-rates = <10000000>, <250000000>;
310 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
319 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
[all …]
H A Dimx8mq.dtsi745 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
749 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
752 assigned-clock-rates = <0>, <0>, <0>, <594000000>;
856 assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>,
864 assigned-clock-rates = <0>, <0>,
871 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
954 assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
958 assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
962 assigned-clock-rates = <600000000>,
1258 assigned
[all...]
H A Dimx8-ss-conn.dtsi80 assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>;
81 assigned-clock-rates = <400000000>;
95 assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>;
96 assigned-clock-rates = <200000000>;
110 assigned-clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>;
111 assigned-clock-rates = <200000000>;
130 assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
132 assigned-clock-rates = <250000000>, <125000000>;
151 assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
153 assigned-clock-rates = <250000000>, <125000000>;
[all …]
H A Dimx8mp-msc-sm2s-ep1.dts72 assigned-clocks = <&clk IMX8MP_CLK_CLKOUT1_SEL>;
73 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
74 assigned-clock-rates = <24000000>;
89 assigned-clocks = <&clk IMX8MP_CLK_SAI2>;
90 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
91 assigned-clock-rates = <12288000>;
H A Dimx8-ss-lvds1.dtsi80 assigned-clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>;
81 assigned-clock-rates = <24000000>;
96 assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>;
97 assigned-clock-rates = <24000000>;
109 assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>;
110 assigned-clock-rates = <24000000>;
/linux/Documentation/devicetree/bindings/sound/
H A Dbrcm,cygnus-audio.txt13 - assigned-clocks: PLL and leaf clocks
14 - assigned-clock-parents: parent clocks of the assigned clocks
16 - assigned-clock-rates: List of clock frequencies of the
17 assigned clocks
36 assigned-clocks = <&audiopll BCM_CYGNUS_AUDIOPLL>,
40 assigned-clock-parents = <&audiopll BCM_CYGNUS_AUDIOPLL>;
41 assigned-clock-rates = <1769470191>,
/linux/arch/arm/boot/dts/samsung/
H A Dexynos4412-odroid-common.dtsi129 assigned-clocks = <&clock CLK_FOUT_EPLL>;
130 assigned-clock-rates = <45158401>;
134 assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
140 assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
143 assigned-clock-rates = <0>, <0>,
211 assigned-clocks = <&clock CLK_MOUT_FIMC0>,
213 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
214 assigned-clock-rates = <0>, <176000000>;
219 assigned-clocks = <&clock CLK_MOUT_FIMC1>,
221 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
[all …]
/linux/arch/mips/boot/dts/img/
H A Dpistachio.dtsi51 assigned-clocks = <&clk_periph PERIPH_CLK_I2C0_PRE_DIV>,
53 assigned-clock-rates = <100000000>, <33333334>;
69 assigned-clocks = <&clk_periph PERIPH_CLK_I2C1_PRE_DIV>,
71 assigned-clock-rates = <100000000>, <33333334>;
87 assigned-clocks = <&clk_periph PERIPH_CLK_I2C2_PRE_DIV>,
89 assigned-clock-rates = <100000000>, <33333334>;
105 assigned-clocks = <&clk_periph PERIPH_CLK_I2C3_PRE_DIV>,
107 assigned-clock-rates = <100000000>, <33333334>;
141 assigned-clocks = <&clk_core CLK_I2S_DIV>;
142 assigned-clock-rates = <12288000>;
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-j721e-mcu-wakeup.dtsi116 assigned-clocks = <&k3_clks 35 1>;
117 assigned-clock-parents = <&k3_clks 35 2>;
131 assigned-clocks = <&k3_clks 71 1>, <&k3_clks 322 0>;
132 assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 322 1>;
145 assigned-clocks = <&k3_clks 72 1>;
146 assigned-clock-parents = <&k3_clks 72 2>;
159 assigned-clocks = <&k3_clks 73 1>, <&k3_clks 323 0>;
160 assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 323 1>;
173 assigned-clocks = <&k3_clks 74 1>;
174 assigned-clock-parents = <&k3_clks 74 2>;
[all …]
H A Dk3-am62-main.dtsi66 assigned-clocks = <&k3_clks 157 0>;
67 assigned-clock-parents = <&k3_clks 157 8>;
75 assigned-clocks = <&k3_clks 157 10>;
76 assigned-clock-parents = <&k3_clks 157 18>;
269 assigned-clocks = <&k3_clks 36 2>;
270 assigned-clock-parents = <&k3_clks 36 3>;
281 assigned-clocks = <&k3_clks 37 2>;
282 assigned-clock-parents = <&k3_clks 37 3>;
293 assigned-clocks = <&k3_clks 38 2>;
294 assigned-clock-parents = <&k3_clks 38 3>;
[all …]
H A Dk3-am62a-main.dtsi67 assigned-clocks = <&k3_clks 157 0>;
68 assigned-clock-parents = <&k3_clks 157 8>;
76 assigned-clocks = <&k3_clks 157 10>;
77 assigned-clock-parents = <&k3_clks 157 18>;
300 assigned-clocks = <&k3_clks 36 2>;
301 assigned-clock-parents = <&k3_clks 36 3>;
313 assigned-clocks = <&k3_clks 37 2>;
314 assigned-clock-parents = <&k3_clks 37 3>;
325 assigned-clocks = <&k3_clks 38 2>;
326 assigned-clock-parents = <&k3_clks 38 3>;
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7d-pico.dtsi105 assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
107 assigned-clock-parents = <&clks IMX7D_CKIL>;
108 assigned-clock-rates = <0>, <32768>;
129 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
131 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
132 assigned-clock-rates = <0>, <100000000>;
286 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
288 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
289 assigned-clock-rates = <0>, <24576000>;
321 assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
[all …]
H A Dimx7d-zii-rpu2.dts189 assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
190 assigned-clock-rates = <884736000>;
211 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
213 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
214 assigned-clock-rates = <0>, <100000000>;
294 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
296 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
297 assigned-clock-rates = <0>, <100000000>;
457 assigned-clocks = <&cs2000>;
458 assigned-clock-rates = <24000000>;
[all …]
H A Dimx7d-cl-som-imx7.dts47 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
49 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
50 assigned-clock-rates = <0>, <100000000>;
75 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
77 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
78 assigned-clock-rates = <0>, <100000000>;
197 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
198 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
212 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
213 assigned-clock-rates = <400000000>;
H A Dimx7d-sdb.dts260 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
262 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
263 assigned-clock-rates = <0>, <100000000>;
287 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
289 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
290 assigned-clock-rates = <0>, <100000000>;
433 assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>,
436 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
437 assigned-clock-rates = <0>, <884736000>, <12288000>;
479 assigned
[all...]
H A Dimx7d-nitrogen7.dts122 assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
124 assigned-clock-parents = <&clks IMX7D_CKIL>;
125 assigned-clock-rates = <0>, <32768>;
139 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
141 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
142 assigned-clock-rates = <0>, <100000000>;
330 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
331 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
338 assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
339 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
[all …]
/linux/Documentation/process/
H A Dcve.rst8 regards to the kernel project, and CVE numbers were very often assigned
21 A list of all assigned CVEs for the Linux kernel can be found in the
24 assigned CVEs, please `subscribe
32 for CVE number assignments and have CVE numbers automatically assigned
45 should have a CVE assigned to it, please email them at <cve@kernel.org>
53 No CVEs will be automatically assigned for unfixed security issues in
57 have a CVE assigned before an issue is resolved with a commit, please
59 identifier assigned from their batch of reserved identifiers.
61 No CVEs will be assigned for any issue found in a version of the kernel
66 Disputes of assigned CVEs
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3568-fastrhino-r68s.dts30 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
31 assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
32 assigned-clock-rates = <0>, <125000000>;
46 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
47 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
48 assigned-clock-rates = <0>, <125000000>;
/linux/drivers/s390/char/
H A Dsclp_mem.c65 u16 assigned; member
145 for (i = 0; i < sccb->assigned; i++) { in sclp_attach_storage()
449 static void __init insert_increment(u16 rn, int standby, int assigned)
463 if (assigned && incr->rn > rn) in insert_increment()
465 if (!assigned && incr->rn - last_rn > 1) in insert_increment()
470 if (!assigned) in insert_increment()
482 int i, id, assigned, rc; in sclp_setup_memory()
493 assigned = 0; in sclp_setup_memory()
503 for (i = 0; i < sccb->assigned; i++) { in sclp_setup_memory()
506 assigned in sclp_setup_memory()
450 insert_increment(u16 rn,int standby,int assigned) insert_increment() argument
483 int i, id, assigned, rc; sclp_setup_memory() local
[all...]
/linux/arch/arm/boot/dts/microchip/
H A Dsama7g5.dtsi387 assigned-clocks = <&pmc PMC_TYPE_GCK 61>;
388 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
389 assigned-clock-rates = <40000000>;
403 assigned-clocks = <&pmc PMC_TYPE_GCK 62>;
404 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
405 assigned-clock-rates = <40000000>;
419 assigned-clocks = <&pmc PMC_TYPE_GCK 63>;
420 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
421 assigned-clock-rates = <40000000>;
435 assigned-clocks = <&pmc PMC_TYPE_GCK 64>;
[all …]
/linux/arch/x86/kernel/cpu/
H A Dtopology.c454 unsigned int assigned = topo_info.nr_assigned_cpus; in topology_init_possible_cpus() local
457 unsigned int total = assigned + disabled; in topology_init_possible_cpus()
472 if (WARN_ON_ONCE(assigned > nr_cpu_ids)) { in topology_init_possible_cpus()
473 disabled += assigned - nr_cpu_ids; in topology_init_possible_cpus()
474 assigned = nr_cpu_ids; in topology_init_possible_cpus()
482 assigned = min_t(unsigned int, allowed, assigned); in topology_init_possible_cpus()
483 disabled = allowed - assigned; in topology_init_possible_cpus()
485 topo_info.nr_assigned_cpus = assigned; in topology_init_possible_cpus()
523 pr_info("Allowing %u present CPUs plus %u hotplug CPUs\n", assigned, disabled); in topology_init_possible_cpus()

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