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Searched refs:adjusted_mode (Results 1 – 25 of 132) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_encoders.c165 struct drm_display_mode *adjusted_mode) in amdgpu_panel_mode_fixup() argument
176 adjusted_mode->clock = native_mode->clock; in amdgpu_panel_mode_fixup()
177 adjusted_mode->flags = native_mode->flags; in amdgpu_panel_mode_fixup()
179 adjusted_mode->hdisplay = native_mode->hdisplay; in amdgpu_panel_mode_fixup()
180 adjusted_mode->vdisplay = native_mode->vdisplay; in amdgpu_panel_mode_fixup()
182 adjusted_mode->htotal = native_mode->hdisplay + hblank; in amdgpu_panel_mode_fixup()
183 adjusted_mode->hsync_start = native_mode->hdisplay + hover; in amdgpu_panel_mode_fixup()
184 adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width; in amdgpu_panel_mode_fixup()
186 adjusted_mode->vtotal = native_mode->vdisplay + vblank; in amdgpu_panel_mode_fixup()
187 adjusted_mode->vsync_start = native_mode->vdisplay + vover; in amdgpu_panel_mode_fixup()
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/linux/drivers/gpu/drm/radeon/
H A Dradeon_encoders.c321 struct drm_display_mode *adjusted_mode) in radeon_panel_mode_fixup() argument
334 adjusted_mode->clock = native_mode->clock; in radeon_panel_mode_fixup()
335 adjusted_mode->flags = native_mode->flags; in radeon_panel_mode_fixup()
338 adjusted_mode->hdisplay = native_mode->hdisplay; in radeon_panel_mode_fixup()
339 adjusted_mode->vdisplay = native_mode->vdisplay; in radeon_panel_mode_fixup()
342 adjusted_mode->htotal = native_mode->hdisplay + hblank; in radeon_panel_mode_fixup()
343 adjusted_mode->hsync_start = native_mode->hdisplay + hover; in radeon_panel_mode_fixup()
344 adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width; in radeon_panel_mode_fixup()
346 adjusted_mode->vtotal = native_mode->vdisplay + vblank; in radeon_panel_mode_fixup()
347 adjusted_mode->vsync_start = native_mode->vdisplay + vover; in radeon_panel_mode_fixup()
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_vrr.c180 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in is_cmrr_frac_required() local
187 drm_mode_vrefresh(adjusted_mode) * FIXED_POINT_PRECISION; in is_cmrr_frac_required()
189 adjusted_mode->crtc_clock * 1000 / adjusted_mode->crtc_htotal; in is_cmrr_frac_required()
191 pixel_clock_per_line * FIXED_POINT_PRECISION / adjusted_mode->crtc_vtotal; in is_cmrr_frac_required()
204 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in cmrr_get_vtotal() local
206 desired_refresh_rate = drm_mode_vrefresh(adjusted_mode); in cmrr_get_vtotal()
213 crtc_state->cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate * adjusted_mode->crtc_htotal, in cmrr_get_vtotal()
215 vtotal = DIV_ROUND_UP_ULL(mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_n), in cmrr_get_vtotal()
217 adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_m); in cmrr_get_vtotal()
256 crtc_state->vrr.vmax = crtc_state->hw.adjusted_mode.crtc_vtotal; in intel_vrr_compute_fixed_rr_timings()
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H A Dintel_alpm.c128 aux_less_wake_lines = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, in _lnl_compute_aux_less_alpm_params()
160 intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, 5); in _lnl_compute_alpm_params()
225 &crtc_state->hw.adjusted_mode, io_wake_time); in intel_alpm_compute_params()
227 &crtc_state->hw.adjusted_mode, fast_wake_time); in intel_alpm_compute_params()
248 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in intel_alpm_lobf_min_guardband() local
249 int first_sdp_position = adjusted_mode->crtc_vtotal - in intel_alpm_lobf_min_guardband()
250 adjusted_mode->crtc_vsync_start; in intel_alpm_lobf_min_guardband()
269 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in intel_alpm_lobf_is_window1_sufficient() local
270 int vblank = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay; in intel_alpm_lobf_is_window1_sufficient()
287 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in intel_alpm_lobf_compute_config_late() local
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H A Ddvo_ns2501.c551 const struct drm_display_mode *adjusted_mode) in ns2501_mode_set() argument
576 adjusted_mode->crtc_clock, in ns2501_mode_set()
577 adjusted_mode->crtc_hdisplay, in ns2501_mode_set()
578 adjusted_mode->crtc_hblank_start, in ns2501_mode_set()
579 adjusted_mode->crtc_hblank_end, in ns2501_mode_set()
580 adjusted_mode->crtc_hsync_start, in ns2501_mode_set()
581 adjusted_mode->crtc_hsync_end, in ns2501_mode_set()
582 adjusted_mode->crtc_htotal, in ns2501_mode_set()
583 adjusted_mode->crtc_hskew, in ns2501_mode_set()
584 adjusted_mode->crtc_vdisplay, in ns2501_mode_set()
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H A Dintel_dvo.c180 pipe_config->hw.adjusted_mode.flags |= flags; in intel_dvo_get_config()
182 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_dvo_get_config()
211 &pipe_config->hw.adjusted_mode); in intel_enable_dvo()
260 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_dvo_compute_config() local
262 intel_panel_fixed_mode(intel_dvo->attached_connector, adjusted_mode); in intel_dvo_compute_config()
273 ret = intel_panel_compute_config(connector, adjusted_mode); in intel_dvo_compute_config()
278 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) in intel_dvo_compute_config()
294 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_dvo_pre_enable() local
308 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) in intel_dvo_pre_enable()
310 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) in intel_dvo_pre_enable()
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H A Dicl_dsi.c319 const struct drm_display_mode *adjusted_mode = in configure_dual_link_mode() local
320 &pipe_config->hw.adjusted_mode; in configure_dual_link_mode()
321 u16 hactive = adjusted_mode->crtc_hdisplay; in configure_dual_link_mode()
879 const struct drm_display_mode *adjusted_mode = in gen11_dsi_set_transcoder_timings() local
880 &crtc_state->hw.adjusted_mode; in gen11_dsi_set_transcoder_timings()
903 hactive = adjusted_mode->crtc_hdisplay; in gen11_dsi_set_transcoder_timings()
906 htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); in gen11_dsi_set_transcoder_timings()
910 hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); in gen11_dsi_set_transcoder_timings()
911 hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); in gen11_dsi_set_transcoder_timings()
913 hback_porch = (adjusted_mode->crtc_htotal - in gen11_dsi_set_transcoder_timings()
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H A Dintel_tv.c1095 struct drm_display_mode *adjusted_mode = in intel_tv_get_config() local
1096 &pipe_config->hw.adjusted_mode; in intel_tv_get_config()
1100 int hdisplay = adjusted_mode->crtc_hdisplay; in intel_tv_get_config()
1101 int vdisplay = adjusted_mode->crtc_vdisplay; in intel_tv_get_config()
1163 adjusted_mode->crtc_clock = mode.clock; in intel_tv_get_config()
1164 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) in intel_tv_get_config()
1165 adjusted_mode->crtc_clock /= 2; in intel_tv_get_config()
1201 struct drm_display_mode *adjusted_mode = in intel_tv_compute_config() local
1202 &pipe_config->hw.adjusted_mode; in intel_tv_compute_config()
1203 int hdisplay = adjusted_mode->crtc_hdisplay; in intel_tv_compute_config()
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H A Dintel_dp.c1736 int clock = crtc_state->hw.adjusted_mode.crtc_clock; in intel_dp_hdmi_compute_bpc()
1820 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in intel_dp_mode_clock() local
1824 return intel_panel_highest_mode(connector, adjusted_mode)->clock; in intel_dp_mode_clock()
1826 return adjusted_mode->crtc_clock; in intel_dp_mode_clock()
1854 const struct drm_display_mode *adjusted_mode = in intel_dp_compute_link_config_wide() local
1855 &pipe_config->hw.adjusted_mode; in intel_dp_compute_link_config_wide()
1858 clock, adjusted_mode->hdisplay, in intel_dp_compute_link_config_wide()
1987 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; in intel_dp_dsc_compute_params()
2070 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in dsc_compute_link_config() local
2113 adjusted_mode->crtc_clock, in dsc_compute_link_config()
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H A Dintel_display.c2312 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in intel_crtc_readout_derived_state() local
2318 drm_mode_copy(pipe_mode, adjusted_mode); in intel_crtc_readout_derived_state()
2328 intel_mode_from_crtc_timings(adjusted_mode, pipe_mode); in intel_crtc_readout_derived_state()
2404 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in intel_crtc_compute_pipe_mode() local
2412 drm_mode_copy(pipe_mode, adjusted_mode); in intel_crtc_compute_pipe_mode()
2467 struct drm_display_mode *adjusted_mode = in intel_crtc_compute_set_context_latency() local
2468 &crtc_state->hw.adjusted_mode; in intel_crtc_compute_set_context_latency()
2473 max_vblank_delay = adjusted_mode->crtc_vblank_end - adjusted_mode->crtc_vblank_start - 1; in intel_crtc_compute_set_context_latency()
2484 adjusted_mode->crtc_vblank_start += set_context_latency; in intel_crtc_compute_set_context_latency()
2676 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in intel_set_transcoder_timings() local
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H A Dintel_lvds.c141 crtc_state->hw.adjusted_mode.flags |= flags; in intel_lvds_get_config()
154 crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock; in intel_lvds_get_config()
246 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in intel_pre_enable_lvds() local
308 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) in intel_pre_enable_lvds()
310 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) in intel_pre_enable_lvds()
424 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in intel_lvds_compute_config() local
463 ret = intel_panel_compute_config(connector, adjusted_mode); in intel_lvds_compute_config()
467 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) in intel_lvds_compute_config()
/linux/drivers/gpu/drm/gma500/
H A Doaktrail_hdmi.c266 struct drm_display_mode *adjusted_mode, in oaktrail_crtc_hdmi_mode_set() argument
309 oaktrail_hdmi_find_dpll(crtc, adjusted_mode->clock, refclk, &clock); in oaktrail_crtc_hdmi_mode_set()
330 temp = htotal_calculate(adjusted_mode); in oaktrail_crtc_hdmi_mode_set()
332 …REG_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - … in oaktrail_crtc_hdmi_mode_set()
333 …REG_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) … in oaktrail_crtc_hdmi_mode_set()
334 REG_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) | ((adjusted_mode->crtc_vtotal - 1) << 16)); in oaktrail_crtc_hdmi_mode_set()
335 …REG_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) | ((adjusted_mode->crtc_vblank_end - … in oaktrail_crtc_hdmi_mode_set()
336 …REG_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) … in oaktrail_crtc_hdmi_mode_set()
339 …REG_WRITE(PCH_HTOTAL_B, (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << … in oaktrail_crtc_hdmi_mode_set()
340 …REG_WRITE(PCH_HBLANK_B, (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end … in oaktrail_crtc_hdmi_mode_set()
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H A Dpsb_intel_display.c96 struct drm_display_mode *adjusted_mode, in psb_intel_crtc_mode_set() argument
149 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, in psb_intel_crtc_mode_set()
153 adjusted_mode->clock, clock.dot); in psb_intel_crtc_mode_set()
167 adjusted_mode->clock / mode->clock; in psb_intel_crtc_mode_set()
268 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | in psb_intel_crtc_mode_set()
269 ((adjusted_mode->crtc_htotal - 1) << 16)); in psb_intel_crtc_mode_set()
270 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | in psb_intel_crtc_mode_set()
271 ((adjusted_mode->crtc_hblank_end - 1) << 16)); in psb_intel_crtc_mode_set()
272 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | in psb_intel_crtc_mode_set()
273 ((adjusted_mode->crtc_hsync_end - 1) << 16)); in psb_intel_crtc_mode_set()
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H A Dcdv_intel_lvds.c183 struct drm_display_mode *adjusted_mode) in cdv_intel_lvds_mode_fixup() argument
208 adjusted_mode->hdisplay = panel_fixed_mode->hdisplay; in cdv_intel_lvds_mode_fixup()
209 adjusted_mode->hsync_start = panel_fixed_mode->hsync_start; in cdv_intel_lvds_mode_fixup()
210 adjusted_mode->hsync_end = panel_fixed_mode->hsync_end; in cdv_intel_lvds_mode_fixup()
211 adjusted_mode->htotal = panel_fixed_mode->htotal; in cdv_intel_lvds_mode_fixup()
212 adjusted_mode->vdisplay = panel_fixed_mode->vdisplay; in cdv_intel_lvds_mode_fixup()
213 adjusted_mode->vsync_start = panel_fixed_mode->vsync_start; in cdv_intel_lvds_mode_fixup()
214 adjusted_mode->vsync_end = panel_fixed_mode->vsync_end; in cdv_intel_lvds_mode_fixup()
215 adjusted_mode->vtotal = panel_fixed_mode->vtotal; in cdv_intel_lvds_mode_fixup()
216 adjusted_mode->clock = panel_fixed_mode->clock; in cdv_intel_lvds_mode_fixup()
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H A Dpsb_intel_lvds.c364 struct drm_display_mode *adjusted_mode) in psb_intel_lvds_mode_fixup() argument
403 adjusted_mode->hdisplay = panel_fixed_mode->hdisplay; in psb_intel_lvds_mode_fixup()
404 adjusted_mode->hsync_start = panel_fixed_mode->hsync_start; in psb_intel_lvds_mode_fixup()
405 adjusted_mode->hsync_end = panel_fixed_mode->hsync_end; in psb_intel_lvds_mode_fixup()
406 adjusted_mode->htotal = panel_fixed_mode->htotal; in psb_intel_lvds_mode_fixup()
407 adjusted_mode->vdisplay = panel_fixed_mode->vdisplay; in psb_intel_lvds_mode_fixup()
408 adjusted_mode->vsync_start = panel_fixed_mode->vsync_start; in psb_intel_lvds_mode_fixup()
409 adjusted_mode->vsync_end = panel_fixed_mode->vsync_end; in psb_intel_lvds_mode_fixup()
410 adjusted_mode->vtotal = panel_fixed_mode->vtotal; in psb_intel_lvds_mode_fixup()
411 adjusted_mode->clock = panel_fixed_mode->clock; in psb_intel_lvds_mode_fixup()
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H A Dcdv_intel_display.c574 struct drm_display_mode *adjusted_mode, in cdv_intel_crtc_mode_set() argument
654 drm_mode_debug_printmodeline(adjusted_mode); in cdv_intel_crtc_mode_set()
658 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, in cdv_intel_crtc_mode_set()
662 adjusted_mode->clock, clock.dot); in cdv_intel_crtc_mode_set()
669 cdv_intel_dp_set_m_n(crtc, mode, adjusted_mode); in cdv_intel_crtc_mode_set()
780 int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; in cdv_intel_crtc_mode_set()
784 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | in cdv_intel_crtc_mode_set()
785 ((adjusted_mode->crtc_htotal - 1) << 16)); in cdv_intel_crtc_mode_set()
786 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | in cdv_intel_crtc_mode_set()
787 ((adjusted_mode->crtc_hblank_end - 1) << 16)); in cdv_intel_crtc_mode_set()
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H A Dcdv_intel_dp.c873 struct drm_display_mode *adjusted_mode) in cdv_intel_fixed_panel_mode() argument
875 adjusted_mode->hdisplay = fixed_mode->hdisplay; in cdv_intel_fixed_panel_mode()
876 adjusted_mode->hsync_start = fixed_mode->hsync_start; in cdv_intel_fixed_panel_mode()
877 adjusted_mode->hsync_end = fixed_mode->hsync_end; in cdv_intel_fixed_panel_mode()
878 adjusted_mode->htotal = fixed_mode->htotal; in cdv_intel_fixed_panel_mode()
880 adjusted_mode->vdisplay = fixed_mode->vdisplay; in cdv_intel_fixed_panel_mode()
881 adjusted_mode->vsync_start = fixed_mode->vsync_start; in cdv_intel_fixed_panel_mode()
882 adjusted_mode->vsync_end = fixed_mode->vsync_end; in cdv_intel_fixed_panel_mode()
883 adjusted_mode->vtotal = fixed_mode->vtotal; in cdv_intel_fixed_panel_mode()
885 adjusted_mode->clock = fixed_mode->clock; in cdv_intel_fixed_panel_mode()
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H A Doaktrail_lvds.c83 struct drm_display_mode *adjusted_mode) in oaktrail_lvds_mode_set() argument
135 if ((mode->vdisplay != adjusted_mode->crtc_vdisplay) || in oaktrail_lvds_mode_set()
136 (mode->hdisplay != adjusted_mode->crtc_hdisplay)) { in oaktrail_lvds_mode_set()
137 if ((adjusted_mode->crtc_hdisplay * mode->vdisplay) == in oaktrail_lvds_mode_set()
138 (mode->hdisplay * adjusted_mode->crtc_vdisplay)) in oaktrail_lvds_mode_set()
140 else if ((adjusted_mode->crtc_hdisplay * in oaktrail_lvds_mode_set()
142 adjusted_mode->crtc_vdisplay)) in oaktrail_lvds_mode_set()
/linux/drivers/gpu/drm/mediatek/
H A Dmtk_hdmi_common.c219 struct drm_display_mode *adjusted_mode) in mtk_hdmi_bridge_mode_fixup() argument
227 const struct drm_display_mode *adjusted_mode) in mtk_hdmi_bridge_mode_set() argument
232 adjusted_mode->name, adjusted_mode->hdisplay); in mtk_hdmi_bridge_mode_set()
234 adjusted_mode->hsync_start, adjusted_mode->hsync_end, in mtk_hdmi_bridge_mode_set()
235 adjusted_mode->htotal); in mtk_hdmi_bridge_mode_set()
237 adjusted_mode->hskew, adjusted_mode->vdisplay); in mtk_hdmi_bridge_mode_set()
239 adjusted_mode->vsync_start, adjusted_mode->vsync_end, in mtk_hdmi_bridge_mode_set()
240 adjusted_mode->vtotal); in mtk_hdmi_bridge_mode_set()
242 adjusted_mode->vscan, adjusted_mode->flags); in mtk_hdmi_bridge_mode_set()
244 drm_mode_copy(&hdmi->mode, adjusted_mode); in mtk_hdmi_bridge_mode_set()
/linux/drivers/gpu/drm/ast/
H A Dast_mode.c177 const struct drm_display_mode *adjusted_mode, in ast_set_vbios_mode_reg() argument
192 ast_set_index_reg(ast, AST_IO_VGACRI, 0x93, adjusted_mode->clock / 1000); in ast_set_vbios_mode_reg()
193 ast_set_index_reg(ast, AST_IO_VGACRI, 0x94, adjusted_mode->crtc_hdisplay); in ast_set_vbios_mode_reg()
194 ast_set_index_reg(ast, AST_IO_VGACRI, 0x95, adjusted_mode->crtc_hdisplay >> 8); in ast_set_vbios_mode_reg()
195 ast_set_index_reg(ast, AST_IO_VGACRI, 0x96, adjusted_mode->crtc_vdisplay); in ast_set_vbios_mode_reg()
196 ast_set_index_reg(ast, AST_IO_VGACRI, 0x97, adjusted_mode->crtc_vdisplay >> 8); in ast_set_vbios_mode_reg()
691 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; in ast_crtc_helper_mode_set_nofb() local
701 ast_set_vbios_mode_reg(ast, adjusted_mode, vmode); in ast_crtc_helper_mode_set_nofb()
703 ast_set_std_reg(ast, adjusted_mode, std_table); in ast_crtc_helper_mode_set_nofb()
704 ast_set_crtc_reg(ast, adjusted_mode, vmode); in ast_crtc_helper_mode_set_nofb()
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/linux/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_encoder.c21 struct drm_display_mode *adjusted_mode) in mdp5_vid_encoder_mode_set() argument
34 mode = adjusted_mode; in mdp5_vid_encoder_mode_set()
179 struct drm_display_mode *adjusted_mode) in mdp5_encoder_mode_set() argument
185 mdp5_cmd_encoder_mode_set(encoder, mode, adjusted_mode); in mdp5_encoder_mode_set()
187 mdp5_vid_encoder_mode_set(encoder, mode, adjusted_mode); in mdp5_encoder_mode_set()
208 mdp5_encoder_mode_set(encoder, &cstate->mode, &cstate->adjusted_mode); in mdp5_encoder_enable()
/linux/drivers/gpu/drm/nouveau/include/dispnv04/i2c/
H A Dencoder_i2c.h81 struct drm_display_mode *adjusted_mode);
94 struct drm_display_mode *adjusted_mode);
230 struct drm_display_mode *adjusted_mode);
/linux/drivers/gpu/drm/bridge/imx/
H A Dimx8qxp-ldb.c105 struct drm_display_mode *adj = &crtc_state->adjusted_mode; in imx8qxp_ldb_bridge_atomic_check()
138 const struct drm_display_mode *adjusted_mode) in imx8qxp_ldb_bridge_mode_set() argument
148 unsigned long di_clk = adjusted_mode->clock * 1000; in imx8qxp_ldb_bridge_mode_set()
200 ldb_bridge_mode_set_helper(bridge, mode, adjusted_mode); in imx8qxp_ldb_bridge_mode_set()
202 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) in imx8qxp_ldb_bridge_mode_set()
204 else if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) in imx8qxp_ldb_bridge_mode_set()
208 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) in imx8qxp_ldb_bridge_mode_set()
210 else if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) in imx8qxp_ldb_bridge_mode_set()
215 companion->funcs->mode_set(companion, mode, adjusted_mode); in imx8qxp_ldb_bridge_mode_set()
H A Dimx8qm-ldb.c88 struct drm_display_mode *adj = &crtc_state->adjusted_mode; in imx8qm_ldb_bridge_atomic_check()
128 const struct drm_display_mode *adjusted_mode) in imx8qm_ldb_bridge_mode_set() argument
136 unsigned long di_clk = adjusted_mode->clock * 1000; in imx8qm_ldb_bridge_mode_set()
188 ldb_bridge_mode_set_helper(bridge, mode, adjusted_mode); in imx8qm_ldb_bridge_mode_set()
190 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) in imx8qm_ldb_bridge_mode_set()
192 else if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) in imx8qm_ldb_bridge_mode_set()
196 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) in imx8qm_ldb_bridge_mode_set()
198 else if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) in imx8qm_ldb_bridge_mode_set()
/linux/drivers/gpu/drm/nouveau/dispnv04/
H A Ddfp.c184 struct drm_display_mode *adjusted_mode) in nv04_dfp_mode_fixup() argument
194 nv_encoder->mode = *adjusted_mode; in nv04_dfp_mode_fixup()
198 adjusted_mode->clock = nv_connector->native_mode->clock; in nv04_dfp_mode_fixup()
282 struct drm_display_mode *adjusted_mode) in nv04_dfp_mode_set() argument
335 else if (adjusted_mode->hdisplay == output_mode->hdisplay && in nv04_dfp_mode_set()
336 adjusted_mode->vdisplay == output_mode->vdisplay) /* native mode */ in nv04_dfp_mode_set()
375 mode_ratio = (1 << 12) * adjusted_mode->hdisplay / adjusted_mode->vdisplay; in nv04_dfp_mode_set()
389 scale = (1 << 12) * adjusted_mode->vdisplay / output_mode->vdisplay; in nv04_dfp_mode_set()
405 scale = (1 << 12) * adjusted_mode->hdisplay / output_mode->hdisplay; in nv04_dfp_mode_set()

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